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IQ.Pilot Prebuilt Release @ 27f668a

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IQ.Lvbs CI [bot]
2026-09-03 18:23:24 -05:00
commit b073c5182b
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774
artifacts/package_runtime/tinygrad/runtime/autogen/am/vega_offsets.py Normal file
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# mypy: disable-error-code="empty-body"
from __future__ import annotations
import ctypes
from typing import Literal, TypeAlias
from tinygrad.runtime.support.c import _IO, _IOW, _IOR, _IOWR
from tinygrad.runtime.support import c
@c.record
class struct_IP_BASE_INSTANCE(c.Struct):
SIZE = 24
segment: c.Array[ctypes.c_uint32, Literal[6]]
struct_IP_BASE_INSTANCE.register_fields([('segment', c.Array[ctypes.c_uint32, Literal[6]], 0)])
@c.record
class struct_IP_BASE(c.Struct):
SIZE = 144
instance: c.Array[struct_IP_BASE_INSTANCE, Literal[6]]
struct_IP_BASE.register_fields([('instance', c.Array[struct_IP_BASE_INSTANCE, Literal[6]], 0)])
MAX_INSTANCE = 6
MAX_SEGMENT = 6
ATHUB_BASE__INST0_SEG0 = 0x00000C20
ATHUB_BASE__INST0_SEG1 = 0
ATHUB_BASE__INST0_SEG2 = 0
ATHUB_BASE__INST0_SEG3 = 0
ATHUB_BASE__INST0_SEG4 = 0
ATHUB_BASE__INST0_SEG5 = 0
ATHUB_BASE__INST1_SEG0 = 0
ATHUB_BASE__INST1_SEG1 = 0
ATHUB_BASE__INST1_SEG2 = 0
ATHUB_BASE__INST1_SEG3 = 0
ATHUB_BASE__INST1_SEG4 = 0
ATHUB_BASE__INST1_SEG5 = 0
ATHUB_BASE__INST2_SEG0 = 0
ATHUB_BASE__INST2_SEG1 = 0
ATHUB_BASE__INST2_SEG2 = 0
ATHUB_BASE__INST2_SEG3 = 0
ATHUB_BASE__INST2_SEG4 = 0
ATHUB_BASE__INST2_SEG5 = 0
ATHUB_BASE__INST3_SEG0 = 0
ATHUB_BASE__INST3_SEG1 = 0
ATHUB_BASE__INST3_SEG2 = 0
ATHUB_BASE__INST3_SEG3 = 0
ATHUB_BASE__INST3_SEG4 = 0
ATHUB_BASE__INST3_SEG5 = 0
ATHUB_BASE__INST4_SEG0 = 0
ATHUB_BASE__INST4_SEG1 = 0
ATHUB_BASE__INST4_SEG2 = 0
ATHUB_BASE__INST4_SEG3 = 0
ATHUB_BASE__INST4_SEG4 = 0
ATHUB_BASE__INST4_SEG5 = 0
ATHUB_BASE__INST5_SEG0 = 0
ATHUB_BASE__INST5_SEG1 = 0
ATHUB_BASE__INST5_SEG2 = 0
ATHUB_BASE__INST5_SEG3 = 0
ATHUB_BASE__INST5_SEG4 = 0
ATHUB_BASE__INST5_SEG5 = 0
CLK_BASE__INST0_SEG0 = 0x00016C00
CLK_BASE__INST0_SEG1 = 0x00016E00
CLK_BASE__INST0_SEG2 = 0x00017000
CLK_BASE__INST0_SEG3 = 0x00017200
CLK_BASE__INST0_SEG4 = 0x0001B000
CLK_BASE__INST0_SEG5 = 0x0001B200
CLK_BASE__INST1_SEG0 = 0
CLK_BASE__INST1_SEG1 = 0
CLK_BASE__INST1_SEG2 = 0
CLK_BASE__INST1_SEG3 = 0
CLK_BASE__INST1_SEG4 = 0
CLK_BASE__INST1_SEG5 = 0
CLK_BASE__INST2_SEG0 = 0
CLK_BASE__INST2_SEG1 = 0
CLK_BASE__INST2_SEG2 = 0
CLK_BASE__INST2_SEG3 = 0
CLK_BASE__INST2_SEG4 = 0
CLK_BASE__INST2_SEG5 = 0
CLK_BASE__INST3_SEG0 = 0
CLK_BASE__INST3_SEG1 = 0
CLK_BASE__INST3_SEG2 = 0
CLK_BASE__INST3_SEG3 = 0
CLK_BASE__INST3_SEG4 = 0
CLK_BASE__INST3_SEG5 = 0
CLK_BASE__INST4_SEG0 = 0
CLK_BASE__INST4_SEG1 = 0
CLK_BASE__INST4_SEG2 = 0
CLK_BASE__INST4_SEG3 = 0
CLK_BASE__INST4_SEG4 = 0
CLK_BASE__INST4_SEG5 = 0
CLK_BASE__INST5_SEG0 = 0
CLK_BASE__INST5_SEG1 = 0
CLK_BASE__INST5_SEG2 = 0
CLK_BASE__INST5_SEG3 = 0
CLK_BASE__INST5_SEG4 = 0
CLK_BASE__INST5_SEG5 = 0
DCE_BASE__INST0_SEG0 = 0x00000012
DCE_BASE__INST0_SEG1 = 0x000000C0
DCE_BASE__INST0_SEG2 = 0x000034C0
DCE_BASE__INST0_SEG3 = 0
DCE_BASE__INST0_SEG4 = 0
DCE_BASE__INST0_SEG5 = 0
DCE_BASE__INST1_SEG0 = 0
DCE_BASE__INST1_SEG1 = 0
DCE_BASE__INST1_SEG2 = 0
DCE_BASE__INST1_SEG3 = 0
DCE_BASE__INST1_SEG4 = 0
DCE_BASE__INST1_SEG5 = 0
DCE_BASE__INST2_SEG0 = 0
DCE_BASE__INST2_SEG1 = 0
DCE_BASE__INST2_SEG2 = 0
DCE_BASE__INST2_SEG3 = 0
DCE_BASE__INST2_SEG4 = 0
DCE_BASE__INST2_SEG5 = 0
DCE_BASE__INST3_SEG0 = 0
DCE_BASE__INST3_SEG1 = 0
DCE_BASE__INST3_SEG2 = 0
DCE_BASE__INST3_SEG3 = 0
DCE_BASE__INST3_SEG4 = 0
DCE_BASE__INST3_SEG5 = 0
DCE_BASE__INST4_SEG0 = 0
DCE_BASE__INST4_SEG1 = 0
DCE_BASE__INST4_SEG2 = 0
DCE_BASE__INST4_SEG3 = 0
DCE_BASE__INST4_SEG4 = 0
DCE_BASE__INST4_SEG5 = 0
DCE_BASE__INST5_SEG0 = 0
DCE_BASE__INST5_SEG1 = 0
DCE_BASE__INST5_SEG2 = 0
DCE_BASE__INST5_SEG3 = 0
DCE_BASE__INST5_SEG4 = 0
DCE_BASE__INST5_SEG5 = 0
DF_BASE__INST0_SEG0 = 0x00007000
DF_BASE__INST0_SEG1 = 0
DF_BASE__INST0_SEG2 = 0
DF_BASE__INST0_SEG3 = 0
DF_BASE__INST0_SEG4 = 0
DF_BASE__INST0_SEG5 = 0
DF_BASE__INST1_SEG0 = 0
DF_BASE__INST1_SEG1 = 0
DF_BASE__INST1_SEG2 = 0
DF_BASE__INST1_SEG3 = 0
DF_BASE__INST1_SEG4 = 0
DF_BASE__INST1_SEG5 = 0
DF_BASE__INST2_SEG0 = 0
DF_BASE__INST2_SEG1 = 0
DF_BASE__INST2_SEG2 = 0
DF_BASE__INST2_SEG3 = 0
DF_BASE__INST2_SEG4 = 0
DF_BASE__INST2_SEG5 = 0
DF_BASE__INST3_SEG0 = 0
DF_BASE__INST3_SEG1 = 0
DF_BASE__INST3_SEG2 = 0
DF_BASE__INST3_SEG3 = 0
DF_BASE__INST3_SEG4 = 0
DF_BASE__INST3_SEG5 = 0
DF_BASE__INST4_SEG0 = 0
DF_BASE__INST4_SEG1 = 0
DF_BASE__INST4_SEG2 = 0
DF_BASE__INST4_SEG3 = 0
DF_BASE__INST4_SEG4 = 0
DF_BASE__INST4_SEG5 = 0
DF_BASE__INST5_SEG0 = 0
DF_BASE__INST5_SEG1 = 0
DF_BASE__INST5_SEG2 = 0
DF_BASE__INST5_SEG3 = 0
DF_BASE__INST5_SEG4 = 0
DF_BASE__INST5_SEG5 = 0
FUSE_BASE__INST0_SEG0 = 0x00017400
FUSE_BASE__INST0_SEG1 = 0
FUSE_BASE__INST0_SEG2 = 0
FUSE_BASE__INST0_SEG3 = 0
FUSE_BASE__INST0_SEG4 = 0
FUSE_BASE__INST0_SEG5 = 0
FUSE_BASE__INST1_SEG0 = 0
FUSE_BASE__INST1_SEG1 = 0
FUSE_BASE__INST1_SEG2 = 0
FUSE_BASE__INST1_SEG3 = 0
FUSE_BASE__INST1_SEG4 = 0
FUSE_BASE__INST1_SEG5 = 0
FUSE_BASE__INST2_SEG0 = 0
FUSE_BASE__INST2_SEG1 = 0
FUSE_BASE__INST2_SEG2 = 0
FUSE_BASE__INST2_SEG3 = 0
FUSE_BASE__INST2_SEG4 = 0
FUSE_BASE__INST2_SEG5 = 0
FUSE_BASE__INST3_SEG0 = 0
FUSE_BASE__INST3_SEG1 = 0
FUSE_BASE__INST3_SEG2 = 0
FUSE_BASE__INST3_SEG3 = 0
FUSE_BASE__INST3_SEG4 = 0
FUSE_BASE__INST3_SEG5 = 0
FUSE_BASE__INST4_SEG0 = 0
FUSE_BASE__INST4_SEG1 = 0
FUSE_BASE__INST4_SEG2 = 0
FUSE_BASE__INST4_SEG3 = 0
FUSE_BASE__INST4_SEG4 = 0
FUSE_BASE__INST4_SEG5 = 0
FUSE_BASE__INST5_SEG0 = 0
FUSE_BASE__INST5_SEG1 = 0
FUSE_BASE__INST5_SEG2 = 0
FUSE_BASE__INST5_SEG3 = 0
FUSE_BASE__INST5_SEG4 = 0
FUSE_BASE__INST5_SEG5 = 0
GC_BASE__INST0_SEG0 = 0x00002000
GC_BASE__INST0_SEG1 = 0x0000A000
GC_BASE__INST0_SEG2 = 0
GC_BASE__INST0_SEG3 = 0
GC_BASE__INST0_SEG4 = 0
GC_BASE__INST0_SEG5 = 0
GC_BASE__INST1_SEG0 = 0
GC_BASE__INST1_SEG1 = 0
GC_BASE__INST1_SEG2 = 0
GC_BASE__INST1_SEG3 = 0
GC_BASE__INST1_SEG4 = 0
GC_BASE__INST1_SEG5 = 0
GC_BASE__INST2_SEG0 = 0
GC_BASE__INST2_SEG1 = 0
GC_BASE__INST2_SEG2 = 0
GC_BASE__INST2_SEG3 = 0
GC_BASE__INST2_SEG4 = 0
GC_BASE__INST2_SEG5 = 0
GC_BASE__INST3_SEG0 = 0
GC_BASE__INST3_SEG1 = 0
GC_BASE__INST3_SEG2 = 0
GC_BASE__INST3_SEG3 = 0
GC_BASE__INST3_SEG4 = 0
GC_BASE__INST3_SEG5 = 0
GC_BASE__INST4_SEG0 = 0
GC_BASE__INST4_SEG1 = 0
GC_BASE__INST4_SEG2 = 0
GC_BASE__INST4_SEG3 = 0
GC_BASE__INST4_SEG4 = 0
GC_BASE__INST4_SEG5 = 0
GC_BASE__INST5_SEG0 = 0
GC_BASE__INST5_SEG1 = 0
GC_BASE__INST5_SEG2 = 0
GC_BASE__INST5_SEG3 = 0
GC_BASE__INST5_SEG4 = 0
GC_BASE__INST5_SEG5 = 0
HDP_BASE__INST0_SEG0 = 0x00000F20
HDP_BASE__INST0_SEG1 = 0
HDP_BASE__INST0_SEG2 = 0
HDP_BASE__INST0_SEG3 = 0
HDP_BASE__INST0_SEG4 = 0
HDP_BASE__INST0_SEG5 = 0
HDP_BASE__INST1_SEG0 = 0
HDP_BASE__INST1_SEG1 = 0
HDP_BASE__INST1_SEG2 = 0
HDP_BASE__INST1_SEG3 = 0
HDP_BASE__INST1_SEG4 = 0
HDP_BASE__INST1_SEG5 = 0
HDP_BASE__INST2_SEG0 = 0
HDP_BASE__INST2_SEG1 = 0
HDP_BASE__INST2_SEG2 = 0
HDP_BASE__INST2_SEG3 = 0
HDP_BASE__INST2_SEG4 = 0
HDP_BASE__INST2_SEG5 = 0
HDP_BASE__INST3_SEG0 = 0
HDP_BASE__INST3_SEG1 = 0
HDP_BASE__INST3_SEG2 = 0
HDP_BASE__INST3_SEG3 = 0
HDP_BASE__INST3_SEG4 = 0
HDP_BASE__INST3_SEG5 = 0
HDP_BASE__INST4_SEG0 = 0
HDP_BASE__INST4_SEG1 = 0
HDP_BASE__INST4_SEG2 = 0
HDP_BASE__INST4_SEG3 = 0
HDP_BASE__INST4_SEG4 = 0
HDP_BASE__INST4_SEG5 = 0
HDP_BASE__INST5_SEG0 = 0
HDP_BASE__INST5_SEG1 = 0
HDP_BASE__INST5_SEG2 = 0
HDP_BASE__INST5_SEG3 = 0
HDP_BASE__INST5_SEG4 = 0
HDP_BASE__INST5_SEG5 = 0
MMHUB_BASE__INST0_SEG0 = 0x0001A000
MMHUB_BASE__INST0_SEG1 = 0
MMHUB_BASE__INST0_SEG2 = 0
MMHUB_BASE__INST0_SEG3 = 0
MMHUB_BASE__INST0_SEG4 = 0
MMHUB_BASE__INST0_SEG5 = 0
MMHUB_BASE__INST1_SEG0 = 0
MMHUB_BASE__INST1_SEG1 = 0
MMHUB_BASE__INST1_SEG2 = 0
MMHUB_BASE__INST1_SEG3 = 0
MMHUB_BASE__INST1_SEG4 = 0
MMHUB_BASE__INST1_SEG5 = 0
MMHUB_BASE__INST2_SEG0 = 0
MMHUB_BASE__INST2_SEG1 = 0
MMHUB_BASE__INST2_SEG2 = 0
MMHUB_BASE__INST2_SEG3 = 0
MMHUB_BASE__INST2_SEG4 = 0
MMHUB_BASE__INST2_SEG5 = 0
MMHUB_BASE__INST3_SEG0 = 0
MMHUB_BASE__INST3_SEG1 = 0
MMHUB_BASE__INST3_SEG2 = 0
MMHUB_BASE__INST3_SEG3 = 0
MMHUB_BASE__INST3_SEG4 = 0
MMHUB_BASE__INST3_SEG5 = 0
MMHUB_BASE__INST4_SEG0 = 0
MMHUB_BASE__INST4_SEG1 = 0
MMHUB_BASE__INST4_SEG2 = 0
MMHUB_BASE__INST4_SEG3 = 0
MMHUB_BASE__INST4_SEG4 = 0
MMHUB_BASE__INST4_SEG5 = 0
MMHUB_BASE__INST5_SEG0 = 0
MMHUB_BASE__INST5_SEG1 = 0
MMHUB_BASE__INST5_SEG2 = 0
MMHUB_BASE__INST5_SEG3 = 0
MMHUB_BASE__INST5_SEG4 = 0
MMHUB_BASE__INST5_SEG5 = 0
MP0_BASE__INST0_SEG0 = 0x00016000
MP0_BASE__INST0_SEG1 = 0
MP0_BASE__INST0_SEG2 = 0
MP0_BASE__INST0_SEG3 = 0
MP0_BASE__INST0_SEG4 = 0
MP0_BASE__INST0_SEG5 = 0
MP0_BASE__INST1_SEG0 = 0
MP0_BASE__INST1_SEG1 = 0
MP0_BASE__INST1_SEG2 = 0
MP0_BASE__INST1_SEG3 = 0
MP0_BASE__INST1_SEG4 = 0
MP0_BASE__INST1_SEG5 = 0
MP0_BASE__INST2_SEG0 = 0
MP0_BASE__INST2_SEG1 = 0
MP0_BASE__INST2_SEG2 = 0
MP0_BASE__INST2_SEG3 = 0
MP0_BASE__INST2_SEG4 = 0
MP0_BASE__INST2_SEG5 = 0
MP0_BASE__INST3_SEG0 = 0
MP0_BASE__INST3_SEG1 = 0
MP0_BASE__INST3_SEG2 = 0
MP0_BASE__INST3_SEG3 = 0
MP0_BASE__INST3_SEG4 = 0
MP0_BASE__INST3_SEG5 = 0
MP0_BASE__INST4_SEG0 = 0
MP0_BASE__INST4_SEG1 = 0
MP0_BASE__INST4_SEG2 = 0
MP0_BASE__INST4_SEG3 = 0
MP0_BASE__INST4_SEG4 = 0
MP0_BASE__INST4_SEG5 = 0
MP0_BASE__INST5_SEG0 = 0
MP0_BASE__INST5_SEG1 = 0
MP0_BASE__INST5_SEG2 = 0
MP0_BASE__INST5_SEG3 = 0
MP0_BASE__INST5_SEG4 = 0
MP0_BASE__INST5_SEG5 = 0
MP1_BASE__INST0_SEG0 = 0x00016000
MP1_BASE__INST0_SEG1 = 0
MP1_BASE__INST0_SEG2 = 0
MP1_BASE__INST0_SEG3 = 0
MP1_BASE__INST0_SEG4 = 0
MP1_BASE__INST0_SEG5 = 0
MP1_BASE__INST1_SEG0 = 0
MP1_BASE__INST1_SEG1 = 0
MP1_BASE__INST1_SEG2 = 0
MP1_BASE__INST1_SEG3 = 0
MP1_BASE__INST1_SEG4 = 0
MP1_BASE__INST1_SEG5 = 0
MP1_BASE__INST2_SEG0 = 0
MP1_BASE__INST2_SEG1 = 0
MP1_BASE__INST2_SEG2 = 0
MP1_BASE__INST2_SEG3 = 0
MP1_BASE__INST2_SEG4 = 0
MP1_BASE__INST2_SEG5 = 0
MP1_BASE__INST3_SEG0 = 0
MP1_BASE__INST3_SEG1 = 0
MP1_BASE__INST3_SEG2 = 0
MP1_BASE__INST3_SEG3 = 0
MP1_BASE__INST3_SEG4 = 0
MP1_BASE__INST3_SEG5 = 0
MP1_BASE__INST4_SEG0 = 0
MP1_BASE__INST4_SEG1 = 0
MP1_BASE__INST4_SEG2 = 0
MP1_BASE__INST4_SEG3 = 0
MP1_BASE__INST4_SEG4 = 0
MP1_BASE__INST4_SEG5 = 0
MP1_BASE__INST5_SEG0 = 0
MP1_BASE__INST5_SEG1 = 0
MP1_BASE__INST5_SEG2 = 0
MP1_BASE__INST5_SEG3 = 0
MP1_BASE__INST5_SEG4 = 0
MP1_BASE__INST5_SEG5 = 0
NBIO_BASE__INST0_SEG0 = 0x00000000
NBIO_BASE__INST0_SEG1 = 0x00000014
NBIO_BASE__INST0_SEG2 = 0x00000D20
NBIO_BASE__INST0_SEG3 = 0x00010400
NBIO_BASE__INST0_SEG4 = 0
NBIO_BASE__INST0_SEG5 = 0
NBIO_BASE__INST1_SEG0 = 0
NBIO_BASE__INST1_SEG1 = 0
NBIO_BASE__INST1_SEG2 = 0
NBIO_BASE__INST1_SEG3 = 0
NBIO_BASE__INST1_SEG4 = 0
NBIO_BASE__INST1_SEG5 = 0
NBIO_BASE__INST2_SEG0 = 0
NBIO_BASE__INST2_SEG1 = 0
NBIO_BASE__INST2_SEG2 = 0
NBIO_BASE__INST2_SEG3 = 0
NBIO_BASE__INST2_SEG4 = 0
NBIO_BASE__INST2_SEG5 = 0
NBIO_BASE__INST3_SEG0 = 0
NBIO_BASE__INST3_SEG1 = 0
NBIO_BASE__INST3_SEG2 = 0
NBIO_BASE__INST3_SEG3 = 0
NBIO_BASE__INST3_SEG4 = 0
NBIO_BASE__INST3_SEG5 = 0
NBIO_BASE__INST4_SEG0 = 0
NBIO_BASE__INST4_SEG1 = 0
NBIO_BASE__INST4_SEG2 = 0
NBIO_BASE__INST4_SEG3 = 0
NBIO_BASE__INST4_SEG4 = 0
NBIO_BASE__INST4_SEG5 = 0
NBIO_BASE__INST5_SEG0 = 0
NBIO_BASE__INST5_SEG1 = 0
NBIO_BASE__INST5_SEG2 = 0
NBIO_BASE__INST5_SEG3 = 0
NBIO_BASE__INST5_SEG4 = 0
NBIO_BASE__INST5_SEG5 = 0
OSSSYS_BASE__INST0_SEG0 = 0x000010A0
OSSSYS_BASE__INST0_SEG1 = 0
OSSSYS_BASE__INST0_SEG2 = 0
OSSSYS_BASE__INST0_SEG3 = 0
OSSSYS_BASE__INST0_SEG4 = 0
OSSSYS_BASE__INST0_SEG5 = 0
OSSSYS_BASE__INST1_SEG0 = 0
OSSSYS_BASE__INST1_SEG1 = 0
OSSSYS_BASE__INST1_SEG2 = 0
OSSSYS_BASE__INST1_SEG3 = 0
OSSSYS_BASE__INST1_SEG4 = 0
OSSSYS_BASE__INST1_SEG5 = 0
OSSSYS_BASE__INST2_SEG0 = 0
OSSSYS_BASE__INST2_SEG1 = 0
OSSSYS_BASE__INST2_SEG2 = 0
OSSSYS_BASE__INST2_SEG3 = 0
OSSSYS_BASE__INST2_SEG4 = 0
OSSSYS_BASE__INST2_SEG5 = 0
OSSSYS_BASE__INST3_SEG0 = 0
OSSSYS_BASE__INST3_SEG1 = 0
OSSSYS_BASE__INST3_SEG2 = 0
OSSSYS_BASE__INST3_SEG3 = 0
OSSSYS_BASE__INST3_SEG4 = 0
OSSSYS_BASE__INST3_SEG5 = 0
OSSSYS_BASE__INST4_SEG0 = 0
OSSSYS_BASE__INST4_SEG1 = 0
OSSSYS_BASE__INST4_SEG2 = 0
OSSSYS_BASE__INST4_SEG3 = 0
OSSSYS_BASE__INST4_SEG4 = 0
OSSSYS_BASE__INST4_SEG5 = 0
OSSSYS_BASE__INST5_SEG0 = 0
OSSSYS_BASE__INST5_SEG1 = 0
OSSSYS_BASE__INST5_SEG2 = 0
OSSSYS_BASE__INST5_SEG3 = 0
OSSSYS_BASE__INST5_SEG4 = 0
OSSSYS_BASE__INST5_SEG5 = 0
SDMA0_BASE__INST0_SEG0 = 0x00001260
SDMA0_BASE__INST0_SEG1 = 0
SDMA0_BASE__INST0_SEG2 = 0
SDMA0_BASE__INST0_SEG3 = 0
SDMA0_BASE__INST0_SEG4 = 0
SDMA0_BASE__INST0_SEG5 = 0
SDMA0_BASE__INST1_SEG0 = 0
SDMA0_BASE__INST1_SEG1 = 0
SDMA0_BASE__INST1_SEG2 = 0
SDMA0_BASE__INST1_SEG3 = 0
SDMA0_BASE__INST1_SEG4 = 0
SDMA0_BASE__INST1_SEG5 = 0
SDMA0_BASE__INST2_SEG0 = 0
SDMA0_BASE__INST2_SEG1 = 0
SDMA0_BASE__INST2_SEG2 = 0
SDMA0_BASE__INST2_SEG3 = 0
SDMA0_BASE__INST2_SEG4 = 0
SDMA0_BASE__INST2_SEG5 = 0
SDMA0_BASE__INST3_SEG0 = 0
SDMA0_BASE__INST3_SEG1 = 0
SDMA0_BASE__INST3_SEG2 = 0
SDMA0_BASE__INST3_SEG3 = 0
SDMA0_BASE__INST3_SEG4 = 0
SDMA0_BASE__INST3_SEG5 = 0
SDMA0_BASE__INST4_SEG0 = 0
SDMA0_BASE__INST4_SEG1 = 0
SDMA0_BASE__INST4_SEG2 = 0
SDMA0_BASE__INST4_SEG3 = 0
SDMA0_BASE__INST4_SEG4 = 0
SDMA0_BASE__INST4_SEG5 = 0
SDMA0_BASE__INST5_SEG0 = 0
SDMA0_BASE__INST5_SEG1 = 0
SDMA0_BASE__INST5_SEG2 = 0
SDMA0_BASE__INST5_SEG3 = 0
SDMA0_BASE__INST5_SEG4 = 0
SDMA0_BASE__INST5_SEG5 = 0
SDMA1_BASE__INST0_SEG0 = 0x00001860
SDMA1_BASE__INST0_SEG1 = 0
SDMA1_BASE__INST0_SEG2 = 0
SDMA1_BASE__INST0_SEG3 = 0
SDMA1_BASE__INST0_SEG4 = 0
SDMA1_BASE__INST0_SEG5 = 0
SDMA1_BASE__INST1_SEG0 = 0
SDMA1_BASE__INST1_SEG1 = 0
SDMA1_BASE__INST1_SEG2 = 0
SDMA1_BASE__INST1_SEG3 = 0
SDMA1_BASE__INST1_SEG4 = 0
SDMA1_BASE__INST1_SEG5 = 0
SDMA1_BASE__INST2_SEG0 = 0
SDMA1_BASE__INST2_SEG1 = 0
SDMA1_BASE__INST2_SEG2 = 0
SDMA1_BASE__INST2_SEG3 = 0
SDMA1_BASE__INST2_SEG4 = 0
SDMA1_BASE__INST2_SEG5 = 0
SDMA1_BASE__INST3_SEG0 = 0
SDMA1_BASE__INST3_SEG1 = 0
SDMA1_BASE__INST3_SEG2 = 0
SDMA1_BASE__INST3_SEG3 = 0
SDMA1_BASE__INST3_SEG4 = 0
SDMA1_BASE__INST3_SEG5 = 0
SDMA1_BASE__INST4_SEG0 = 0
SDMA1_BASE__INST4_SEG1 = 0
SDMA1_BASE__INST4_SEG2 = 0
SDMA1_BASE__INST4_SEG3 = 0
SDMA1_BASE__INST4_SEG4 = 0
SDMA1_BASE__INST4_SEG5 = 0
SDMA1_BASE__INST5_SEG0 = 0
SDMA1_BASE__INST5_SEG1 = 0
SDMA1_BASE__INST5_SEG2 = 0
SDMA1_BASE__INST5_SEG3 = 0
SDMA1_BASE__INST5_SEG4 = 0
SDMA1_BASE__INST5_SEG5 = 0
SMUIO_BASE__INST0_SEG0 = 0x00016800
SMUIO_BASE__INST0_SEG1 = 0x00016A00
SMUIO_BASE__INST0_SEG2 = 0
SMUIO_BASE__INST0_SEG3 = 0
SMUIO_BASE__INST0_SEG4 = 0
SMUIO_BASE__INST0_SEG5 = 0
SMUIO_BASE__INST1_SEG0 = 0
SMUIO_BASE__INST1_SEG1 = 0
SMUIO_BASE__INST1_SEG2 = 0
SMUIO_BASE__INST1_SEG3 = 0
SMUIO_BASE__INST1_SEG4 = 0
SMUIO_BASE__INST1_SEG5 = 0
SMUIO_BASE__INST2_SEG0 = 0
SMUIO_BASE__INST2_SEG1 = 0
SMUIO_BASE__INST2_SEG2 = 0
SMUIO_BASE__INST2_SEG3 = 0
SMUIO_BASE__INST2_SEG4 = 0
SMUIO_BASE__INST2_SEG5 = 0
SMUIO_BASE__INST3_SEG0 = 0
SMUIO_BASE__INST3_SEG1 = 0
SMUIO_BASE__INST3_SEG2 = 0
SMUIO_BASE__INST3_SEG3 = 0
SMUIO_BASE__INST3_SEG4 = 0
SMUIO_BASE__INST3_SEG5 = 0
SMUIO_BASE__INST4_SEG0 = 0
SMUIO_BASE__INST4_SEG1 = 0
SMUIO_BASE__INST4_SEG2 = 0
SMUIO_BASE__INST4_SEG3 = 0
SMUIO_BASE__INST4_SEG4 = 0
SMUIO_BASE__INST4_SEG5 = 0
SMUIO_BASE__INST5_SEG0 = 0
SMUIO_BASE__INST5_SEG1 = 0
SMUIO_BASE__INST5_SEG2 = 0
SMUIO_BASE__INST5_SEG3 = 0
SMUIO_BASE__INST5_SEG4 = 0
SMUIO_BASE__INST5_SEG5 = 0
THM_BASE__INST0_SEG0 = 0x00016600
THM_BASE__INST0_SEG1 = 0
THM_BASE__INST0_SEG2 = 0
THM_BASE__INST0_SEG3 = 0
THM_BASE__INST0_SEG4 = 0
THM_BASE__INST0_SEG5 = 0
THM_BASE__INST1_SEG0 = 0
THM_BASE__INST1_SEG1 = 0
THM_BASE__INST1_SEG2 = 0
THM_BASE__INST1_SEG3 = 0
THM_BASE__INST1_SEG4 = 0
THM_BASE__INST1_SEG5 = 0
THM_BASE__INST2_SEG0 = 0
THM_BASE__INST2_SEG1 = 0
THM_BASE__INST2_SEG2 = 0
THM_BASE__INST2_SEG3 = 0
THM_BASE__INST2_SEG4 = 0
THM_BASE__INST2_SEG5 = 0
THM_BASE__INST3_SEG0 = 0
THM_BASE__INST3_SEG1 = 0
THM_BASE__INST3_SEG2 = 0
THM_BASE__INST3_SEG3 = 0
THM_BASE__INST3_SEG4 = 0
THM_BASE__INST3_SEG5 = 0
THM_BASE__INST4_SEG0 = 0
THM_BASE__INST4_SEG1 = 0
THM_BASE__INST4_SEG2 = 0
THM_BASE__INST4_SEG3 = 0
THM_BASE__INST4_SEG4 = 0
THM_BASE__INST4_SEG5 = 0
THM_BASE__INST5_SEG0 = 0
THM_BASE__INST5_SEG1 = 0
THM_BASE__INST5_SEG2 = 0
THM_BASE__INST5_SEG3 = 0
THM_BASE__INST5_SEG4 = 0
THM_BASE__INST5_SEG5 = 0
UMC_BASE__INST0_SEG0 = 0x00014000
UMC_BASE__INST0_SEG1 = 0
UMC_BASE__INST0_SEG2 = 0
UMC_BASE__INST0_SEG3 = 0
UMC_BASE__INST0_SEG4 = 0
UMC_BASE__INST0_SEG5 = 0
UMC_BASE__INST1_SEG0 = 0
UMC_BASE__INST1_SEG1 = 0
UMC_BASE__INST1_SEG2 = 0
UMC_BASE__INST1_SEG3 = 0
UMC_BASE__INST1_SEG4 = 0
UMC_BASE__INST1_SEG5 = 0
UMC_BASE__INST2_SEG0 = 0
UMC_BASE__INST2_SEG1 = 0
UMC_BASE__INST2_SEG2 = 0
UMC_BASE__INST2_SEG3 = 0
UMC_BASE__INST2_SEG4 = 0
UMC_BASE__INST2_SEG5 = 0
UMC_BASE__INST3_SEG0 = 0
UMC_BASE__INST3_SEG1 = 0
UMC_BASE__INST3_SEG2 = 0
UMC_BASE__INST3_SEG3 = 0
UMC_BASE__INST3_SEG4 = 0
UMC_BASE__INST3_SEG5 = 0
UMC_BASE__INST4_SEG0 = 0
UMC_BASE__INST4_SEG1 = 0
UMC_BASE__INST4_SEG2 = 0
UMC_BASE__INST4_SEG3 = 0
UMC_BASE__INST4_SEG4 = 0
UMC_BASE__INST4_SEG5 = 0
UMC_BASE__INST5_SEG0 = 0
UMC_BASE__INST5_SEG1 = 0
UMC_BASE__INST5_SEG2 = 0
UMC_BASE__INST5_SEG3 = 0
UMC_BASE__INST5_SEG4 = 0
UMC_BASE__INST5_SEG5 = 0
UVD_BASE__INST0_SEG0 = 0x00007800
UVD_BASE__INST0_SEG1 = 0x00007E00
UVD_BASE__INST0_SEG2 = 0
UVD_BASE__INST0_SEG3 = 0
UVD_BASE__INST0_SEG4 = 0
UVD_BASE__INST0_SEG5 = 0
UVD_BASE__INST1_SEG0 = 0
UVD_BASE__INST1_SEG1 = 0x00009000
UVD_BASE__INST1_SEG2 = 0
UVD_BASE__INST1_SEG3 = 0
UVD_BASE__INST1_SEG4 = 0
UVD_BASE__INST1_SEG5 = 0
UVD_BASE__INST2_SEG0 = 0
UVD_BASE__INST2_SEG1 = 0
UVD_BASE__INST2_SEG2 = 0
UVD_BASE__INST2_SEG3 = 0
UVD_BASE__INST2_SEG4 = 0
UVD_BASE__INST2_SEG5 = 0
UVD_BASE__INST3_SEG0 = 0
UVD_BASE__INST3_SEG1 = 0
UVD_BASE__INST3_SEG2 = 0
UVD_BASE__INST3_SEG3 = 0
UVD_BASE__INST3_SEG4 = 0
UVD_BASE__INST3_SEG5 = 0
UVD_BASE__INST4_SEG0 = 0
UVD_BASE__INST4_SEG1 = 0
UVD_BASE__INST4_SEG2 = 0
UVD_BASE__INST4_SEG3 = 0
UVD_BASE__INST4_SEG4 = 0
UVD_BASE__INST4_SEG5 = 0
UVD_BASE__INST5_SEG0 = 0
UVD_BASE__INST5_SEG1 = 0
UVD_BASE__INST5_SEG2 = 0
UVD_BASE__INST5_SEG3 = 0
UVD_BASE__INST5_SEG4 = 0
UVD_BASE__INST5_SEG5 = 0
VCE_BASE__INST0_SEG0 = 0x00008800
VCE_BASE__INST0_SEG1 = 0
VCE_BASE__INST0_SEG2 = 0
VCE_BASE__INST0_SEG3 = 0
VCE_BASE__INST0_SEG4 = 0
VCE_BASE__INST0_SEG5 = 0
VCE_BASE__INST1_SEG0 = 0
VCE_BASE__INST1_SEG1 = 0
VCE_BASE__INST1_SEG2 = 0
VCE_BASE__INST1_SEG3 = 0
VCE_BASE__INST1_SEG4 = 0
VCE_BASE__INST1_SEG5 = 0
VCE_BASE__INST2_SEG0 = 0
VCE_BASE__INST2_SEG1 = 0
VCE_BASE__INST2_SEG2 = 0
VCE_BASE__INST2_SEG3 = 0
VCE_BASE__INST2_SEG4 = 0
VCE_BASE__INST2_SEG5 = 0
VCE_BASE__INST3_SEG0 = 0
VCE_BASE__INST3_SEG1 = 0
VCE_BASE__INST3_SEG2 = 0
VCE_BASE__INST3_SEG3 = 0
VCE_BASE__INST3_SEG4 = 0
VCE_BASE__INST3_SEG5 = 0
VCE_BASE__INST4_SEG0 = 0
VCE_BASE__INST4_SEG1 = 0
VCE_BASE__INST4_SEG2 = 0
VCE_BASE__INST4_SEG3 = 0
VCE_BASE__INST4_SEG4 = 0
VCE_BASE__INST4_SEG5 = 0
VCE_BASE__INST5_SEG0 = 0
VCE_BASE__INST5_SEG1 = 0
VCE_BASE__INST5_SEG2 = 0
VCE_BASE__INST5_SEG3 = 0
VCE_BASE__INST5_SEG4 = 0
VCE_BASE__INST5_SEG5 = 0
XDMA_BASE__INST0_SEG0 = 0x00003400
XDMA_BASE__INST0_SEG1 = 0
XDMA_BASE__INST0_SEG2 = 0
XDMA_BASE__INST0_SEG3 = 0
XDMA_BASE__INST0_SEG4 = 0
XDMA_BASE__INST0_SEG5 = 0
XDMA_BASE__INST1_SEG0 = 0
XDMA_BASE__INST1_SEG1 = 0
XDMA_BASE__INST1_SEG2 = 0
XDMA_BASE__INST1_SEG3 = 0
XDMA_BASE__INST1_SEG4 = 0
XDMA_BASE__INST1_SEG5 = 0
XDMA_BASE__INST2_SEG0 = 0
XDMA_BASE__INST2_SEG1 = 0
XDMA_BASE__INST2_SEG2 = 0
XDMA_BASE__INST2_SEG3 = 0
XDMA_BASE__INST2_SEG4 = 0
XDMA_BASE__INST2_SEG5 = 0
XDMA_BASE__INST3_SEG0 = 0
XDMA_BASE__INST3_SEG1 = 0
XDMA_BASE__INST3_SEG2 = 0
XDMA_BASE__INST3_SEG3 = 0
XDMA_BASE__INST3_SEG4 = 0
XDMA_BASE__INST3_SEG5 = 0
XDMA_BASE__INST4_SEG0 = 0
XDMA_BASE__INST4_SEG1 = 0
XDMA_BASE__INST4_SEG2 = 0
XDMA_BASE__INST4_SEG3 = 0
XDMA_BASE__INST4_SEG4 = 0
XDMA_BASE__INST4_SEG5 = 0
XDMA_BASE__INST5_SEG0 = 0
XDMA_BASE__INST5_SEG1 = 0
XDMA_BASE__INST5_SEG2 = 0
XDMA_BASE__INST5_SEG3 = 0
XDMA_BASE__INST5_SEG4 = 0
XDMA_BASE__INST5_SEG5 = 0
RSMU_BASE__INST0_SEG0 = 0x00012000
RSMU_BASE__INST0_SEG1 = 0
RSMU_BASE__INST0_SEG2 = 0
RSMU_BASE__INST0_SEG3 = 0
RSMU_BASE__INST0_SEG4 = 0
RSMU_BASE__INST0_SEG5 = 0
RSMU_BASE__INST1_SEG0 = 0
RSMU_BASE__INST1_SEG1 = 0
RSMU_BASE__INST1_SEG2 = 0
RSMU_BASE__INST1_SEG3 = 0
RSMU_BASE__INST1_SEG4 = 0
RSMU_BASE__INST1_SEG5 = 0
RSMU_BASE__INST2_SEG0 = 0
RSMU_BASE__INST2_SEG1 = 0
RSMU_BASE__INST2_SEG2 = 0
RSMU_BASE__INST2_SEG3 = 0
RSMU_BASE__INST2_SEG4 = 0
RSMU_BASE__INST2_SEG5 = 0
RSMU_BASE__INST3_SEG0 = 0
RSMU_BASE__INST3_SEG1 = 0
RSMU_BASE__INST3_SEG2 = 0
RSMU_BASE__INST3_SEG3 = 0
RSMU_BASE__INST3_SEG4 = 0
RSMU_BASE__INST3_SEG5 = 0
RSMU_BASE__INST4_SEG0 = 0
RSMU_BASE__INST4_SEG1 = 0
RSMU_BASE__INST4_SEG2 = 0
RSMU_BASE__INST4_SEG3 = 0
RSMU_BASE__INST4_SEG4 = 0
RSMU_BASE__INST4_SEG5 = 0
RSMU_BASE__INST5_SEG0 = 0
RSMU_BASE__INST5_SEG1 = 0
RSMU_BASE__INST5_SEG2 = 0
RSMU_BASE__INST5_SEG3 = 0
RSMU_BASE__INST5_SEG4 = 0
RSMU_BASE__INST5_SEG5 = 0