823 lines
22 KiB
Python
823 lines
22 KiB
Python
# mypy: disable-error-code="empty-body"
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from __future__ import annotations
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import ctypes
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from typing import Literal, TypeAlias
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from tinygrad.runtime.support.c import _IO, _IOW, _IOR, _IOWR
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from tinygrad.runtime.support import c
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@c.record
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class struct_IP_BASE_INSTANCE(c.Struct):
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SIZE = 20
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segment: c.Array[ctypes.c_uint32, Literal[5]]
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struct_IP_BASE_INSTANCE.register_fields([('segment', c.Array[ctypes.c_uint32, Literal[5]], 0)])
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@c.record
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class struct_IP_BASE(c.Struct):
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SIZE = 140
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instance: c.Array[struct_IP_BASE_INSTANCE, Literal[7]]
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struct_IP_BASE.register_fields([('instance', c.Array[struct_IP_BASE_INSTANCE, Literal[7]], 0)])
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MAX_INSTANCE = 7
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MAX_SEGMENT = 5
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ATHUB_BASE__INST0_SEG0 = 0x00000C00
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ATHUB_BASE__INST0_SEG1 = 0x02408C00
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ATHUB_BASE__INST0_SEG2 = 0
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ATHUB_BASE__INST0_SEG3 = 0
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ATHUB_BASE__INST0_SEG4 = 0
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ATHUB_BASE__INST1_SEG0 = 0
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ATHUB_BASE__INST1_SEG1 = 0
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ATHUB_BASE__INST1_SEG2 = 0
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ATHUB_BASE__INST1_SEG3 = 0
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ATHUB_BASE__INST1_SEG4 = 0
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ATHUB_BASE__INST2_SEG0 = 0
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ATHUB_BASE__INST2_SEG1 = 0
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ATHUB_BASE__INST2_SEG2 = 0
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ATHUB_BASE__INST2_SEG3 = 0
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ATHUB_BASE__INST2_SEG4 = 0
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ATHUB_BASE__INST3_SEG0 = 0
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ATHUB_BASE__INST3_SEG1 = 0
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ATHUB_BASE__INST3_SEG2 = 0
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ATHUB_BASE__INST3_SEG3 = 0
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ATHUB_BASE__INST3_SEG4 = 0
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ATHUB_BASE__INST4_SEG0 = 0
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ATHUB_BASE__INST4_SEG1 = 0
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ATHUB_BASE__INST4_SEG2 = 0
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ATHUB_BASE__INST4_SEG3 = 0
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ATHUB_BASE__INST4_SEG4 = 0
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ATHUB_BASE__INST5_SEG0 = 0
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ATHUB_BASE__INST5_SEG1 = 0
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ATHUB_BASE__INST5_SEG2 = 0
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ATHUB_BASE__INST5_SEG3 = 0
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ATHUB_BASE__INST5_SEG4 = 0
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ATHUB_BASE__INST6_SEG0 = 0
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ATHUB_BASE__INST6_SEG1 = 0
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ATHUB_BASE__INST6_SEG2 = 0
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ATHUB_BASE__INST6_SEG3 = 0
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ATHUB_BASE__INST6_SEG4 = 0
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CLK_BASE__INST0_SEG0 = 0x00016C00
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CLK_BASE__INST0_SEG1 = 0x02401800
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CLK_BASE__INST0_SEG2 = 0
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CLK_BASE__INST0_SEG3 = 0
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CLK_BASE__INST0_SEG4 = 0
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CLK_BASE__INST1_SEG0 = 0x00016E00
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CLK_BASE__INST1_SEG1 = 0x02401C00
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CLK_BASE__INST1_SEG2 = 0
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CLK_BASE__INST1_SEG3 = 0
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CLK_BASE__INST1_SEG4 = 0
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CLK_BASE__INST2_SEG0 = 0x00017000
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CLK_BASE__INST2_SEG1 = 0x02402000
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CLK_BASE__INST2_SEG2 = 0
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CLK_BASE__INST2_SEG3 = 0
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CLK_BASE__INST2_SEG4 = 0
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CLK_BASE__INST3_SEG0 = 0x00017200
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CLK_BASE__INST3_SEG1 = 0x02402400
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CLK_BASE__INST3_SEG2 = 0
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CLK_BASE__INST3_SEG3 = 0
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CLK_BASE__INST3_SEG4 = 0
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CLK_BASE__INST4_SEG0 = 0x0001B000
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CLK_BASE__INST4_SEG1 = 0x0242D800
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CLK_BASE__INST4_SEG2 = 0
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CLK_BASE__INST4_SEG3 = 0
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CLK_BASE__INST4_SEG4 = 0
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CLK_BASE__INST5_SEG0 = 0x0001B200
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CLK_BASE__INST5_SEG1 = 0x0242DC00
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CLK_BASE__INST5_SEG2 = 0
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CLK_BASE__INST5_SEG3 = 0
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CLK_BASE__INST5_SEG4 = 0
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CLK_BASE__INST6_SEG0 = 0x0001B400
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CLK_BASE__INST6_SEG1 = 0x0242E000
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CLK_BASE__INST6_SEG2 = 0
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CLK_BASE__INST6_SEG3 = 0
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CLK_BASE__INST6_SEG4 = 0
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DF_BASE__INST0_SEG0 = 0x00007000
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DF_BASE__INST0_SEG1 = 0x0240B800
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DF_BASE__INST0_SEG2 = 0
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DF_BASE__INST0_SEG3 = 0
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DF_BASE__INST0_SEG4 = 0
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DF_BASE__INST1_SEG0 = 0
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DF_BASE__INST1_SEG1 = 0
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DF_BASE__INST1_SEG2 = 0
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DF_BASE__INST1_SEG3 = 0
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DF_BASE__INST1_SEG4 = 0
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DF_BASE__INST2_SEG0 = 0
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DF_BASE__INST2_SEG1 = 0
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DF_BASE__INST2_SEG2 = 0
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DF_BASE__INST2_SEG3 = 0
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DF_BASE__INST2_SEG4 = 0
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DF_BASE__INST3_SEG0 = 0
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DF_BASE__INST3_SEG1 = 0
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DF_BASE__INST3_SEG2 = 0
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DF_BASE__INST3_SEG3 = 0
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DF_BASE__INST3_SEG4 = 0
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DF_BASE__INST4_SEG0 = 0
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DF_BASE__INST4_SEG1 = 0
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DF_BASE__INST4_SEG2 = 0
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DF_BASE__INST4_SEG3 = 0
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DF_BASE__INST4_SEG4 = 0
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DF_BASE__INST5_SEG0 = 0
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DF_BASE__INST5_SEG1 = 0
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DF_BASE__INST5_SEG2 = 0
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DF_BASE__INST5_SEG3 = 0
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DF_BASE__INST5_SEG4 = 0
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DF_BASE__INST6_SEG0 = 0
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DF_BASE__INST6_SEG1 = 0
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DF_BASE__INST6_SEG2 = 0
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DF_BASE__INST6_SEG3 = 0
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DF_BASE__INST6_SEG4 = 0
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DIO_BASE__INST0_SEG0 = 0x02404000
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DIO_BASE__INST0_SEG1 = 0
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DIO_BASE__INST0_SEG2 = 0
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DIO_BASE__INST0_SEG3 = 0
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DIO_BASE__INST0_SEG4 = 0
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DIO_BASE__INST1_SEG0 = 0
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DIO_BASE__INST1_SEG1 = 0
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DIO_BASE__INST1_SEG2 = 0
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DIO_BASE__INST1_SEG3 = 0
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DIO_BASE__INST1_SEG4 = 0
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DIO_BASE__INST2_SEG0 = 0
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DIO_BASE__INST2_SEG1 = 0
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DIO_BASE__INST2_SEG2 = 0
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DIO_BASE__INST2_SEG3 = 0
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DIO_BASE__INST2_SEG4 = 0
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DIO_BASE__INST3_SEG0 = 0
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DIO_BASE__INST3_SEG1 = 0
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DIO_BASE__INST3_SEG2 = 0
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DIO_BASE__INST3_SEG3 = 0
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DIO_BASE__INST3_SEG4 = 0
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DIO_BASE__INST4_SEG0 = 0
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DIO_BASE__INST4_SEG1 = 0
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DIO_BASE__INST4_SEG2 = 0
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DIO_BASE__INST4_SEG3 = 0
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DIO_BASE__INST4_SEG4 = 0
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DIO_BASE__INST5_SEG0 = 0
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DIO_BASE__INST5_SEG1 = 0
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DIO_BASE__INST5_SEG2 = 0
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DIO_BASE__INST5_SEG3 = 0
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DIO_BASE__INST5_SEG4 = 0
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DIO_BASE__INST6_SEG0 = 0
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DIO_BASE__INST6_SEG1 = 0
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DIO_BASE__INST6_SEG2 = 0
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DIO_BASE__INST6_SEG3 = 0
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DIO_BASE__INST6_SEG4 = 0
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DCN_BASE__INST0_SEG0 = 0x00000012
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DCN_BASE__INST0_SEG1 = 0x000000C0
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DCN_BASE__INST0_SEG2 = 0x000034C0
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DCN_BASE__INST0_SEG3 = 0x00009000
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DCN_BASE__INST0_SEG4 = 0x02403C00
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DCN_BASE__INST1_SEG0 = 0
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DCN_BASE__INST1_SEG1 = 0
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DCN_BASE__INST1_SEG2 = 0
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DCN_BASE__INST1_SEG3 = 0
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DCN_BASE__INST1_SEG4 = 0
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DCN_BASE__INST2_SEG0 = 0
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DCN_BASE__INST2_SEG1 = 0
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DCN_BASE__INST2_SEG2 = 0
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DCN_BASE__INST2_SEG3 = 0
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DCN_BASE__INST2_SEG4 = 0
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DCN_BASE__INST3_SEG0 = 0
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DCN_BASE__INST3_SEG1 = 0
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DCN_BASE__INST3_SEG2 = 0
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DCN_BASE__INST3_SEG3 = 0
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DCN_BASE__INST3_SEG4 = 0
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DCN_BASE__INST4_SEG0 = 0
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DCN_BASE__INST4_SEG1 = 0
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DCN_BASE__INST4_SEG2 = 0
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DCN_BASE__INST4_SEG3 = 0
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DCN_BASE__INST4_SEG4 = 0
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DCN_BASE__INST5_SEG0 = 0
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DCN_BASE__INST5_SEG1 = 0
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DCN_BASE__INST5_SEG2 = 0
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DCN_BASE__INST5_SEG3 = 0
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DCN_BASE__INST5_SEG4 = 0
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DCN_BASE__INST6_SEG0 = 0
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DCN_BASE__INST6_SEG1 = 0
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DCN_BASE__INST6_SEG2 = 0
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DCN_BASE__INST6_SEG3 = 0
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DCN_BASE__INST6_SEG4 = 0
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DPCS_BASE__INST0_SEG0 = 0x00000012
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DPCS_BASE__INST0_SEG1 = 0x000000C0
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DPCS_BASE__INST0_SEG2 = 0x000034C0
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DPCS_BASE__INST0_SEG3 = 0x00009000
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DPCS_BASE__INST0_SEG4 = 0x02403C00
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DPCS_BASE__INST1_SEG0 = 0
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DPCS_BASE__INST1_SEG1 = 0
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DPCS_BASE__INST1_SEG2 = 0
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DPCS_BASE__INST1_SEG3 = 0
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DPCS_BASE__INST1_SEG4 = 0
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DPCS_BASE__INST2_SEG0 = 0
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DPCS_BASE__INST2_SEG1 = 0
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DPCS_BASE__INST2_SEG2 = 0
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DPCS_BASE__INST2_SEG3 = 0
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DPCS_BASE__INST2_SEG4 = 0
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DPCS_BASE__INST3_SEG0 = 0
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DPCS_BASE__INST3_SEG1 = 0
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DPCS_BASE__INST3_SEG2 = 0
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DPCS_BASE__INST3_SEG3 = 0
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DPCS_BASE__INST3_SEG4 = 0
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DPCS_BASE__INST4_SEG0 = 0
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DPCS_BASE__INST4_SEG1 = 0
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DPCS_BASE__INST4_SEG2 = 0
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DPCS_BASE__INST4_SEG3 = 0
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DPCS_BASE__INST4_SEG4 = 0
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DPCS_BASE__INST5_SEG0 = 0
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DPCS_BASE__INST5_SEG1 = 0
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|
DPCS_BASE__INST5_SEG2 = 0
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|
DPCS_BASE__INST5_SEG3 = 0
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DPCS_BASE__INST5_SEG4 = 0
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DPCS_BASE__INST6_SEG0 = 0
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DPCS_BASE__INST6_SEG1 = 0
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DPCS_BASE__INST6_SEG2 = 0
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DPCS_BASE__INST6_SEG3 = 0
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DPCS_BASE__INST6_SEG4 = 0
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FUSE_BASE__INST0_SEG0 = 0x00017400
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FUSE_BASE__INST0_SEG1 = 0x02401400
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FUSE_BASE__INST0_SEG2 = 0
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|
FUSE_BASE__INST0_SEG3 = 0
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FUSE_BASE__INST0_SEG4 = 0
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|
FUSE_BASE__INST1_SEG0 = 0
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FUSE_BASE__INST1_SEG1 = 0
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FUSE_BASE__INST1_SEG2 = 0
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FUSE_BASE__INST1_SEG3 = 0
|
|
FUSE_BASE__INST1_SEG4 = 0
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|
FUSE_BASE__INST2_SEG0 = 0
|
|
FUSE_BASE__INST2_SEG1 = 0
|
|
FUSE_BASE__INST2_SEG2 = 0
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FUSE_BASE__INST2_SEG3 = 0
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FUSE_BASE__INST2_SEG4 = 0
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|
FUSE_BASE__INST3_SEG0 = 0
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FUSE_BASE__INST3_SEG1 = 0
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|
FUSE_BASE__INST3_SEG2 = 0
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FUSE_BASE__INST3_SEG3 = 0
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FUSE_BASE__INST3_SEG4 = 0
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|
FUSE_BASE__INST4_SEG0 = 0
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|
FUSE_BASE__INST4_SEG1 = 0
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FUSE_BASE__INST4_SEG2 = 0
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FUSE_BASE__INST4_SEG3 = 0
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|
FUSE_BASE__INST4_SEG4 = 0
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|
FUSE_BASE__INST5_SEG0 = 0
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|
FUSE_BASE__INST5_SEG1 = 0
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|
FUSE_BASE__INST5_SEG2 = 0
|
|
FUSE_BASE__INST5_SEG3 = 0
|
|
FUSE_BASE__INST5_SEG4 = 0
|
|
FUSE_BASE__INST6_SEG0 = 0
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FUSE_BASE__INST6_SEG1 = 0
|
|
FUSE_BASE__INST6_SEG2 = 0
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|
FUSE_BASE__INST6_SEG3 = 0
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|
FUSE_BASE__INST6_SEG4 = 0
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GC_BASE__INST0_SEG0 = 0x00001260
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GC_BASE__INST0_SEG1 = 0x0000A000
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GC_BASE__INST0_SEG2 = 0x0001C000
|
|
GC_BASE__INST0_SEG3 = 0x02402C00
|
|
GC_BASE__INST0_SEG4 = 0
|
|
GC_BASE__INST1_SEG0 = 0
|
|
GC_BASE__INST1_SEG1 = 0
|
|
GC_BASE__INST1_SEG2 = 0
|
|
GC_BASE__INST1_SEG3 = 0
|
|
GC_BASE__INST1_SEG4 = 0
|
|
GC_BASE__INST2_SEG0 = 0
|
|
GC_BASE__INST2_SEG1 = 0
|
|
GC_BASE__INST2_SEG2 = 0
|
|
GC_BASE__INST2_SEG3 = 0
|
|
GC_BASE__INST2_SEG4 = 0
|
|
GC_BASE__INST3_SEG0 = 0
|
|
GC_BASE__INST3_SEG1 = 0
|
|
GC_BASE__INST3_SEG2 = 0
|
|
GC_BASE__INST3_SEG3 = 0
|
|
GC_BASE__INST3_SEG4 = 0
|
|
GC_BASE__INST4_SEG0 = 0
|
|
GC_BASE__INST4_SEG1 = 0
|
|
GC_BASE__INST4_SEG2 = 0
|
|
GC_BASE__INST4_SEG3 = 0
|
|
GC_BASE__INST4_SEG4 = 0
|
|
GC_BASE__INST5_SEG0 = 0
|
|
GC_BASE__INST5_SEG1 = 0
|
|
GC_BASE__INST5_SEG2 = 0
|
|
GC_BASE__INST5_SEG3 = 0
|
|
GC_BASE__INST5_SEG4 = 0
|
|
GC_BASE__INST6_SEG0 = 0
|
|
GC_BASE__INST6_SEG1 = 0
|
|
GC_BASE__INST6_SEG2 = 0
|
|
GC_BASE__INST6_SEG3 = 0
|
|
GC_BASE__INST6_SEG4 = 0
|
|
HDA_BASE__INST0_SEG0 = 0x004C0000
|
|
HDA_BASE__INST0_SEG1 = 0x02404800
|
|
HDA_BASE__INST0_SEG2 = 0
|
|
HDA_BASE__INST0_SEG3 = 0
|
|
HDA_BASE__INST0_SEG4 = 0
|
|
HDA_BASE__INST1_SEG0 = 0
|
|
HDA_BASE__INST1_SEG1 = 0
|
|
HDA_BASE__INST1_SEG2 = 0
|
|
HDA_BASE__INST1_SEG3 = 0
|
|
HDA_BASE__INST1_SEG4 = 0
|
|
HDA_BASE__INST2_SEG0 = 0
|
|
HDA_BASE__INST2_SEG1 = 0
|
|
HDA_BASE__INST2_SEG2 = 0
|
|
HDA_BASE__INST2_SEG3 = 0
|
|
HDA_BASE__INST2_SEG4 = 0
|
|
HDA_BASE__INST3_SEG0 = 0
|
|
HDA_BASE__INST3_SEG1 = 0
|
|
HDA_BASE__INST3_SEG2 = 0
|
|
HDA_BASE__INST3_SEG3 = 0
|
|
HDA_BASE__INST3_SEG4 = 0
|
|
HDA_BASE__INST4_SEG0 = 0
|
|
HDA_BASE__INST4_SEG1 = 0
|
|
HDA_BASE__INST4_SEG2 = 0
|
|
HDA_BASE__INST4_SEG3 = 0
|
|
HDA_BASE__INST4_SEG4 = 0
|
|
HDA_BASE__INST5_SEG0 = 0
|
|
HDA_BASE__INST5_SEG1 = 0
|
|
HDA_BASE__INST5_SEG2 = 0
|
|
HDA_BASE__INST5_SEG3 = 0
|
|
HDA_BASE__INST5_SEG4 = 0
|
|
HDA_BASE__INST6_SEG0 = 0
|
|
HDA_BASE__INST6_SEG1 = 0
|
|
HDA_BASE__INST6_SEG2 = 0
|
|
HDA_BASE__INST6_SEG3 = 0
|
|
HDA_BASE__INST6_SEG4 = 0
|
|
HDP_BASE__INST0_SEG0 = 0x00000F20
|
|
HDP_BASE__INST0_SEG1 = 0x0240A400
|
|
HDP_BASE__INST0_SEG2 = 0
|
|
HDP_BASE__INST0_SEG3 = 0
|
|
HDP_BASE__INST0_SEG4 = 0
|
|
HDP_BASE__INST1_SEG0 = 0
|
|
HDP_BASE__INST1_SEG1 = 0
|
|
HDP_BASE__INST1_SEG2 = 0
|
|
HDP_BASE__INST1_SEG3 = 0
|
|
HDP_BASE__INST1_SEG4 = 0
|
|
HDP_BASE__INST2_SEG0 = 0
|
|
HDP_BASE__INST2_SEG1 = 0
|
|
HDP_BASE__INST2_SEG2 = 0
|
|
HDP_BASE__INST2_SEG3 = 0
|
|
HDP_BASE__INST2_SEG4 = 0
|
|
HDP_BASE__INST3_SEG0 = 0
|
|
HDP_BASE__INST3_SEG1 = 0
|
|
HDP_BASE__INST3_SEG2 = 0
|
|
HDP_BASE__INST3_SEG3 = 0
|
|
HDP_BASE__INST3_SEG4 = 0
|
|
HDP_BASE__INST4_SEG0 = 0
|
|
HDP_BASE__INST4_SEG1 = 0
|
|
HDP_BASE__INST4_SEG2 = 0
|
|
HDP_BASE__INST4_SEG3 = 0
|
|
HDP_BASE__INST4_SEG4 = 0
|
|
HDP_BASE__INST5_SEG0 = 0
|
|
HDP_BASE__INST5_SEG1 = 0
|
|
HDP_BASE__INST5_SEG2 = 0
|
|
HDP_BASE__INST5_SEG3 = 0
|
|
HDP_BASE__INST5_SEG4 = 0
|
|
HDP_BASE__INST6_SEG0 = 0
|
|
HDP_BASE__INST6_SEG1 = 0
|
|
HDP_BASE__INST6_SEG2 = 0
|
|
HDP_BASE__INST6_SEG3 = 0
|
|
HDP_BASE__INST6_SEG4 = 0
|
|
MMHUB_BASE__INST0_SEG0 = 0x0001A000
|
|
MMHUB_BASE__INST0_SEG1 = 0x02408800
|
|
MMHUB_BASE__INST0_SEG2 = 0
|
|
MMHUB_BASE__INST0_SEG3 = 0
|
|
MMHUB_BASE__INST0_SEG4 = 0
|
|
MMHUB_BASE__INST1_SEG0 = 0
|
|
MMHUB_BASE__INST1_SEG1 = 0
|
|
MMHUB_BASE__INST1_SEG2 = 0
|
|
MMHUB_BASE__INST1_SEG3 = 0
|
|
MMHUB_BASE__INST1_SEG4 = 0
|
|
MMHUB_BASE__INST2_SEG0 = 0
|
|
MMHUB_BASE__INST2_SEG1 = 0
|
|
MMHUB_BASE__INST2_SEG2 = 0
|
|
MMHUB_BASE__INST2_SEG3 = 0
|
|
MMHUB_BASE__INST2_SEG4 = 0
|
|
MMHUB_BASE__INST3_SEG0 = 0
|
|
MMHUB_BASE__INST3_SEG1 = 0
|
|
MMHUB_BASE__INST3_SEG2 = 0
|
|
MMHUB_BASE__INST3_SEG3 = 0
|
|
MMHUB_BASE__INST3_SEG4 = 0
|
|
MMHUB_BASE__INST4_SEG0 = 0
|
|
MMHUB_BASE__INST4_SEG1 = 0
|
|
MMHUB_BASE__INST4_SEG2 = 0
|
|
MMHUB_BASE__INST4_SEG3 = 0
|
|
MMHUB_BASE__INST4_SEG4 = 0
|
|
MMHUB_BASE__INST5_SEG0 = 0
|
|
MMHUB_BASE__INST5_SEG1 = 0
|
|
MMHUB_BASE__INST5_SEG2 = 0
|
|
MMHUB_BASE__INST5_SEG3 = 0
|
|
MMHUB_BASE__INST5_SEG4 = 0
|
|
MMHUB_BASE__INST6_SEG0 = 0
|
|
MMHUB_BASE__INST6_SEG1 = 0
|
|
MMHUB_BASE__INST6_SEG2 = 0
|
|
MMHUB_BASE__INST6_SEG3 = 0
|
|
MMHUB_BASE__INST6_SEG4 = 0
|
|
MP0_BASE__INST0_SEG0 = 0x00016000
|
|
MP0_BASE__INST0_SEG1 = 0x00DC0000
|
|
MP0_BASE__INST0_SEG2 = 0x00E00000
|
|
MP0_BASE__INST0_SEG3 = 0x00E40000
|
|
MP0_BASE__INST0_SEG4 = 0x0243FC00
|
|
MP0_BASE__INST1_SEG0 = 0
|
|
MP0_BASE__INST1_SEG1 = 0
|
|
MP0_BASE__INST1_SEG2 = 0
|
|
MP0_BASE__INST1_SEG3 = 0
|
|
MP0_BASE__INST1_SEG4 = 0
|
|
MP0_BASE__INST2_SEG0 = 0
|
|
MP0_BASE__INST2_SEG1 = 0
|
|
MP0_BASE__INST2_SEG2 = 0
|
|
MP0_BASE__INST2_SEG3 = 0
|
|
MP0_BASE__INST2_SEG4 = 0
|
|
MP0_BASE__INST3_SEG0 = 0
|
|
MP0_BASE__INST3_SEG1 = 0
|
|
MP0_BASE__INST3_SEG2 = 0
|
|
MP0_BASE__INST3_SEG3 = 0
|
|
MP0_BASE__INST3_SEG4 = 0
|
|
MP0_BASE__INST4_SEG0 = 0
|
|
MP0_BASE__INST4_SEG1 = 0
|
|
MP0_BASE__INST4_SEG2 = 0
|
|
MP0_BASE__INST4_SEG3 = 0
|
|
MP0_BASE__INST4_SEG4 = 0
|
|
MP0_BASE__INST5_SEG0 = 0
|
|
MP0_BASE__INST5_SEG1 = 0
|
|
MP0_BASE__INST5_SEG2 = 0
|
|
MP0_BASE__INST5_SEG3 = 0
|
|
MP0_BASE__INST5_SEG4 = 0
|
|
MP0_BASE__INST6_SEG0 = 0
|
|
MP0_BASE__INST6_SEG1 = 0
|
|
MP0_BASE__INST6_SEG2 = 0
|
|
MP0_BASE__INST6_SEG3 = 0
|
|
MP0_BASE__INST6_SEG4 = 0
|
|
MP1_BASE__INST0_SEG0 = 0x00016000
|
|
MP1_BASE__INST0_SEG1 = 0x00DC0000
|
|
MP1_BASE__INST0_SEG2 = 0x00E00000
|
|
MP1_BASE__INST0_SEG3 = 0x00E40000
|
|
MP1_BASE__INST0_SEG4 = 0x0243FC00
|
|
MP1_BASE__INST1_SEG0 = 0
|
|
MP1_BASE__INST1_SEG1 = 0
|
|
MP1_BASE__INST1_SEG2 = 0
|
|
MP1_BASE__INST1_SEG3 = 0
|
|
MP1_BASE__INST1_SEG4 = 0
|
|
MP1_BASE__INST2_SEG0 = 0
|
|
MP1_BASE__INST2_SEG1 = 0
|
|
MP1_BASE__INST2_SEG2 = 0
|
|
MP1_BASE__INST2_SEG3 = 0
|
|
MP1_BASE__INST2_SEG4 = 0
|
|
MP1_BASE__INST3_SEG0 = 0
|
|
MP1_BASE__INST3_SEG1 = 0
|
|
MP1_BASE__INST3_SEG2 = 0
|
|
MP1_BASE__INST3_SEG3 = 0
|
|
MP1_BASE__INST3_SEG4 = 0
|
|
MP1_BASE__INST4_SEG0 = 0
|
|
MP1_BASE__INST4_SEG1 = 0
|
|
MP1_BASE__INST4_SEG2 = 0
|
|
MP1_BASE__INST4_SEG3 = 0
|
|
MP1_BASE__INST4_SEG4 = 0
|
|
MP1_BASE__INST5_SEG0 = 0
|
|
MP1_BASE__INST5_SEG1 = 0
|
|
MP1_BASE__INST5_SEG2 = 0
|
|
MP1_BASE__INST5_SEG3 = 0
|
|
MP1_BASE__INST5_SEG4 = 0
|
|
MP1_BASE__INST6_SEG0 = 0
|
|
MP1_BASE__INST6_SEG1 = 0
|
|
MP1_BASE__INST6_SEG2 = 0
|
|
MP1_BASE__INST6_SEG3 = 0
|
|
MP1_BASE__INST6_SEG4 = 0
|
|
NBIO_BASE__INST0_SEG0 = 0x00000000
|
|
NBIO_BASE__INST0_SEG1 = 0x00000014
|
|
NBIO_BASE__INST0_SEG2 = 0x00000D20
|
|
NBIO_BASE__INST0_SEG3 = 0x00010400
|
|
NBIO_BASE__INST0_SEG4 = 0x0241B000
|
|
NBIO_BASE__INST1_SEG0 = 0
|
|
NBIO_BASE__INST1_SEG1 = 0
|
|
NBIO_BASE__INST1_SEG2 = 0
|
|
NBIO_BASE__INST1_SEG3 = 0
|
|
NBIO_BASE__INST1_SEG4 = 0
|
|
NBIO_BASE__INST2_SEG0 = 0
|
|
NBIO_BASE__INST2_SEG1 = 0
|
|
NBIO_BASE__INST2_SEG2 = 0
|
|
NBIO_BASE__INST2_SEG3 = 0
|
|
NBIO_BASE__INST2_SEG4 = 0
|
|
NBIO_BASE__INST3_SEG0 = 0
|
|
NBIO_BASE__INST3_SEG1 = 0
|
|
NBIO_BASE__INST3_SEG2 = 0
|
|
NBIO_BASE__INST3_SEG3 = 0
|
|
NBIO_BASE__INST3_SEG4 = 0
|
|
NBIO_BASE__INST4_SEG0 = 0
|
|
NBIO_BASE__INST4_SEG1 = 0
|
|
NBIO_BASE__INST4_SEG2 = 0
|
|
NBIO_BASE__INST4_SEG3 = 0
|
|
NBIO_BASE__INST4_SEG4 = 0
|
|
NBIO_BASE__INST5_SEG0 = 0
|
|
NBIO_BASE__INST5_SEG1 = 0
|
|
NBIO_BASE__INST5_SEG2 = 0
|
|
NBIO_BASE__INST5_SEG3 = 0
|
|
NBIO_BASE__INST5_SEG4 = 0
|
|
NBIO_BASE__INST6_SEG0 = 0
|
|
NBIO_BASE__INST6_SEG1 = 0
|
|
NBIO_BASE__INST6_SEG2 = 0
|
|
NBIO_BASE__INST6_SEG3 = 0
|
|
NBIO_BASE__INST6_SEG4 = 0
|
|
OSSSYS_BASE__INST0_SEG0 = 0x000010A0
|
|
OSSSYS_BASE__INST0_SEG1 = 0x0240A000
|
|
OSSSYS_BASE__INST0_SEG2 = 0
|
|
OSSSYS_BASE__INST0_SEG3 = 0
|
|
OSSSYS_BASE__INST0_SEG4 = 0
|
|
OSSSYS_BASE__INST1_SEG0 = 0
|
|
OSSSYS_BASE__INST1_SEG1 = 0
|
|
OSSSYS_BASE__INST1_SEG2 = 0
|
|
OSSSYS_BASE__INST1_SEG3 = 0
|
|
OSSSYS_BASE__INST1_SEG4 = 0
|
|
OSSSYS_BASE__INST2_SEG0 = 0
|
|
OSSSYS_BASE__INST2_SEG1 = 0
|
|
OSSSYS_BASE__INST2_SEG2 = 0
|
|
OSSSYS_BASE__INST2_SEG3 = 0
|
|
OSSSYS_BASE__INST2_SEG4 = 0
|
|
OSSSYS_BASE__INST3_SEG0 = 0
|
|
OSSSYS_BASE__INST3_SEG1 = 0
|
|
OSSSYS_BASE__INST3_SEG2 = 0
|
|
OSSSYS_BASE__INST3_SEG3 = 0
|
|
OSSSYS_BASE__INST3_SEG4 = 0
|
|
OSSSYS_BASE__INST4_SEG0 = 0
|
|
OSSSYS_BASE__INST4_SEG1 = 0
|
|
OSSSYS_BASE__INST4_SEG2 = 0
|
|
OSSSYS_BASE__INST4_SEG3 = 0
|
|
OSSSYS_BASE__INST4_SEG4 = 0
|
|
OSSSYS_BASE__INST5_SEG0 = 0
|
|
OSSSYS_BASE__INST5_SEG1 = 0
|
|
OSSSYS_BASE__INST5_SEG2 = 0
|
|
OSSSYS_BASE__INST5_SEG3 = 0
|
|
OSSSYS_BASE__INST5_SEG4 = 0
|
|
OSSSYS_BASE__INST6_SEG0 = 0
|
|
OSSSYS_BASE__INST6_SEG1 = 0
|
|
OSSSYS_BASE__INST6_SEG2 = 0
|
|
OSSSYS_BASE__INST6_SEG3 = 0
|
|
OSSSYS_BASE__INST6_SEG4 = 0
|
|
PCIE0_BASE__INST0_SEG0 = 0x00000000
|
|
PCIE0_BASE__INST0_SEG1 = 0x00000014
|
|
PCIE0_BASE__INST0_SEG2 = 0x00000D20
|
|
PCIE0_BASE__INST0_SEG3 = 0x00010400
|
|
PCIE0_BASE__INST0_SEG4 = 0x0241B000
|
|
PCIE0_BASE__INST1_SEG0 = 0
|
|
PCIE0_BASE__INST1_SEG1 = 0
|
|
PCIE0_BASE__INST1_SEG2 = 0
|
|
PCIE0_BASE__INST1_SEG3 = 0
|
|
PCIE0_BASE__INST1_SEG4 = 0
|
|
PCIE0_BASE__INST2_SEG0 = 0
|
|
PCIE0_BASE__INST2_SEG1 = 0
|
|
PCIE0_BASE__INST2_SEG2 = 0
|
|
PCIE0_BASE__INST2_SEG3 = 0
|
|
PCIE0_BASE__INST2_SEG4 = 0
|
|
PCIE0_BASE__INST3_SEG0 = 0
|
|
PCIE0_BASE__INST3_SEG1 = 0
|
|
PCIE0_BASE__INST3_SEG2 = 0
|
|
PCIE0_BASE__INST3_SEG3 = 0
|
|
PCIE0_BASE__INST3_SEG4 = 0
|
|
PCIE0_BASE__INST4_SEG0 = 0
|
|
PCIE0_BASE__INST4_SEG1 = 0
|
|
PCIE0_BASE__INST4_SEG2 = 0
|
|
PCIE0_BASE__INST4_SEG3 = 0
|
|
PCIE0_BASE__INST4_SEG4 = 0
|
|
PCIE0_BASE__INST5_SEG0 = 0
|
|
PCIE0_BASE__INST5_SEG1 = 0
|
|
PCIE0_BASE__INST5_SEG2 = 0
|
|
PCIE0_BASE__INST5_SEG3 = 0
|
|
PCIE0_BASE__INST5_SEG4 = 0
|
|
PCIE0_BASE__INST6_SEG0 = 0
|
|
PCIE0_BASE__INST6_SEG1 = 0
|
|
PCIE0_BASE__INST6_SEG2 = 0
|
|
PCIE0_BASE__INST6_SEG3 = 0
|
|
PCIE0_BASE__INST6_SEG4 = 0
|
|
SDMA0_BASE__INST0_SEG0 = 0x00001260
|
|
SDMA0_BASE__INST0_SEG1 = 0x0000A000
|
|
SDMA0_BASE__INST0_SEG2 = 0x0001C000
|
|
SDMA0_BASE__INST0_SEG3 = 0x02402C00
|
|
SDMA0_BASE__INST0_SEG4 = 0
|
|
SDMA0_BASE__INST1_SEG0 = 0
|
|
SDMA0_BASE__INST1_SEG1 = 0
|
|
SDMA0_BASE__INST1_SEG2 = 0
|
|
SDMA0_BASE__INST1_SEG3 = 0
|
|
SDMA0_BASE__INST1_SEG4 = 0
|
|
SDMA0_BASE__INST2_SEG0 = 0
|
|
SDMA0_BASE__INST2_SEG1 = 0
|
|
SDMA0_BASE__INST2_SEG2 = 0
|
|
SDMA0_BASE__INST2_SEG3 = 0
|
|
SDMA0_BASE__INST2_SEG4 = 0
|
|
SDMA0_BASE__INST3_SEG0 = 0
|
|
SDMA0_BASE__INST3_SEG1 = 0
|
|
SDMA0_BASE__INST3_SEG2 = 0
|
|
SDMA0_BASE__INST3_SEG3 = 0
|
|
SDMA0_BASE__INST3_SEG4 = 0
|
|
SDMA0_BASE__INST4_SEG0 = 0
|
|
SDMA0_BASE__INST4_SEG1 = 0
|
|
SDMA0_BASE__INST4_SEG2 = 0
|
|
SDMA0_BASE__INST4_SEG3 = 0
|
|
SDMA0_BASE__INST4_SEG4 = 0
|
|
SDMA0_BASE__INST5_SEG0 = 0
|
|
SDMA0_BASE__INST5_SEG1 = 0
|
|
SDMA0_BASE__INST5_SEG2 = 0
|
|
SDMA0_BASE__INST5_SEG3 = 0
|
|
SDMA0_BASE__INST5_SEG4 = 0
|
|
SDMA0_BASE__INST6_SEG0 = 0
|
|
SDMA0_BASE__INST6_SEG1 = 0
|
|
SDMA0_BASE__INST6_SEG2 = 0
|
|
SDMA0_BASE__INST6_SEG3 = 0
|
|
SDMA0_BASE__INST6_SEG4 = 0
|
|
SDMA1_BASE__INST0_SEG0 = 0x00001260
|
|
SDMA1_BASE__INST0_SEG1 = 0x0000A000
|
|
SDMA1_BASE__INST0_SEG2 = 0x0001C000
|
|
SDMA1_BASE__INST0_SEG3 = 0x02402C00
|
|
SDMA1_BASE__INST0_SEG4 = 0
|
|
SDMA1_BASE__INST1_SEG0 = 0
|
|
SDMA1_BASE__INST1_SEG1 = 0
|
|
SDMA1_BASE__INST1_SEG2 = 0
|
|
SDMA1_BASE__INST1_SEG3 = 0
|
|
SDMA1_BASE__INST1_SEG4 = 0
|
|
SDMA1_BASE__INST2_SEG0 = 0
|
|
SDMA1_BASE__INST2_SEG1 = 0
|
|
SDMA1_BASE__INST2_SEG2 = 0
|
|
SDMA1_BASE__INST2_SEG3 = 0
|
|
SDMA1_BASE__INST2_SEG4 = 0
|
|
SDMA1_BASE__INST3_SEG0 = 0
|
|
SDMA1_BASE__INST3_SEG1 = 0
|
|
SDMA1_BASE__INST3_SEG2 = 0
|
|
SDMA1_BASE__INST3_SEG3 = 0
|
|
SDMA1_BASE__INST3_SEG4 = 0
|
|
SDMA1_BASE__INST4_SEG0 = 0
|
|
SDMA1_BASE__INST4_SEG1 = 0
|
|
SDMA1_BASE__INST4_SEG2 = 0
|
|
SDMA1_BASE__INST4_SEG3 = 0
|
|
SDMA1_BASE__INST4_SEG4 = 0
|
|
SDMA1_BASE__INST5_SEG0 = 0
|
|
SDMA1_BASE__INST5_SEG1 = 0
|
|
SDMA1_BASE__INST5_SEG2 = 0
|
|
SDMA1_BASE__INST5_SEG3 = 0
|
|
SDMA1_BASE__INST5_SEG4 = 0
|
|
SDMA1_BASE__INST6_SEG0 = 0
|
|
SDMA1_BASE__INST6_SEG1 = 0
|
|
SDMA1_BASE__INST6_SEG2 = 0
|
|
SDMA1_BASE__INST6_SEG3 = 0
|
|
SDMA1_BASE__INST6_SEG4 = 0
|
|
SMUIO_BASE__INST0_SEG0 = 0x00016800
|
|
SMUIO_BASE__INST0_SEG1 = 0x00016A00
|
|
SMUIO_BASE__INST0_SEG2 = 0x00440000
|
|
SMUIO_BASE__INST0_SEG3 = 0x02401000
|
|
SMUIO_BASE__INST0_SEG4 = 0
|
|
SMUIO_BASE__INST1_SEG0 = 0
|
|
SMUIO_BASE__INST1_SEG1 = 0
|
|
SMUIO_BASE__INST1_SEG2 = 0
|
|
SMUIO_BASE__INST1_SEG3 = 0
|
|
SMUIO_BASE__INST1_SEG4 = 0
|
|
SMUIO_BASE__INST2_SEG0 = 0
|
|
SMUIO_BASE__INST2_SEG1 = 0
|
|
SMUIO_BASE__INST2_SEG2 = 0
|
|
SMUIO_BASE__INST2_SEG3 = 0
|
|
SMUIO_BASE__INST2_SEG4 = 0
|
|
SMUIO_BASE__INST3_SEG0 = 0
|
|
SMUIO_BASE__INST3_SEG1 = 0
|
|
SMUIO_BASE__INST3_SEG2 = 0
|
|
SMUIO_BASE__INST3_SEG3 = 0
|
|
SMUIO_BASE__INST3_SEG4 = 0
|
|
SMUIO_BASE__INST4_SEG0 = 0
|
|
SMUIO_BASE__INST4_SEG1 = 0
|
|
SMUIO_BASE__INST4_SEG2 = 0
|
|
SMUIO_BASE__INST4_SEG3 = 0
|
|
SMUIO_BASE__INST4_SEG4 = 0
|
|
SMUIO_BASE__INST5_SEG0 = 0
|
|
SMUIO_BASE__INST5_SEG1 = 0
|
|
SMUIO_BASE__INST5_SEG2 = 0
|
|
SMUIO_BASE__INST5_SEG3 = 0
|
|
SMUIO_BASE__INST5_SEG4 = 0
|
|
SMUIO_BASE__INST6_SEG0 = 0
|
|
SMUIO_BASE__INST6_SEG1 = 0
|
|
SMUIO_BASE__INST6_SEG2 = 0
|
|
SMUIO_BASE__INST6_SEG3 = 0
|
|
SMUIO_BASE__INST6_SEG4 = 0
|
|
THM_BASE__INST0_SEG0 = 0x00016600
|
|
THM_BASE__INST0_SEG1 = 0x02400C00
|
|
THM_BASE__INST0_SEG2 = 0
|
|
THM_BASE__INST0_SEG3 = 0
|
|
THM_BASE__INST0_SEG4 = 0
|
|
THM_BASE__INST1_SEG0 = 0
|
|
THM_BASE__INST1_SEG1 = 0
|
|
THM_BASE__INST1_SEG2 = 0
|
|
THM_BASE__INST1_SEG3 = 0
|
|
THM_BASE__INST1_SEG4 = 0
|
|
THM_BASE__INST2_SEG0 = 0
|
|
THM_BASE__INST2_SEG1 = 0
|
|
THM_BASE__INST2_SEG2 = 0
|
|
THM_BASE__INST2_SEG3 = 0
|
|
THM_BASE__INST2_SEG4 = 0
|
|
THM_BASE__INST3_SEG0 = 0
|
|
THM_BASE__INST3_SEG1 = 0
|
|
THM_BASE__INST3_SEG2 = 0
|
|
THM_BASE__INST3_SEG3 = 0
|
|
THM_BASE__INST3_SEG4 = 0
|
|
THM_BASE__INST4_SEG0 = 0
|
|
THM_BASE__INST4_SEG1 = 0
|
|
THM_BASE__INST4_SEG2 = 0
|
|
THM_BASE__INST4_SEG3 = 0
|
|
THM_BASE__INST4_SEG4 = 0
|
|
THM_BASE__INST5_SEG0 = 0
|
|
THM_BASE__INST5_SEG1 = 0
|
|
THM_BASE__INST5_SEG2 = 0
|
|
THM_BASE__INST5_SEG3 = 0
|
|
THM_BASE__INST5_SEG4 = 0
|
|
THM_BASE__INST6_SEG0 = 0
|
|
THM_BASE__INST6_SEG1 = 0
|
|
THM_BASE__INST6_SEG2 = 0
|
|
THM_BASE__INST6_SEG3 = 0
|
|
THM_BASE__INST6_SEG4 = 0
|
|
UMC_BASE__INST0_SEG0 = 0x00014000
|
|
UMC_BASE__INST0_SEG1 = 0x02425800
|
|
UMC_BASE__INST0_SEG2 = 0
|
|
UMC_BASE__INST0_SEG3 = 0
|
|
UMC_BASE__INST0_SEG4 = 0
|
|
UMC_BASE__INST1_SEG0 = 0x00054000
|
|
UMC_BASE__INST1_SEG1 = 0x02425C00
|
|
UMC_BASE__INST1_SEG2 = 0
|
|
UMC_BASE__INST1_SEG3 = 0
|
|
UMC_BASE__INST1_SEG4 = 0
|
|
UMC_BASE__INST2_SEG0 = 0x00094000
|
|
UMC_BASE__INST2_SEG1 = 0x02426000
|
|
UMC_BASE__INST2_SEG2 = 0
|
|
UMC_BASE__INST2_SEG3 = 0
|
|
UMC_BASE__INST2_SEG4 = 0
|
|
UMC_BASE__INST3_SEG0 = 0x000D4000
|
|
UMC_BASE__INST3_SEG1 = 0x02426400
|
|
UMC_BASE__INST3_SEG2 = 0
|
|
UMC_BASE__INST3_SEG3 = 0
|
|
UMC_BASE__INST3_SEG4 = 0
|
|
UMC_BASE__INST4_SEG0 = 0x00114000
|
|
UMC_BASE__INST4_SEG1 = 0x02426800
|
|
UMC_BASE__INST4_SEG2 = 0
|
|
UMC_BASE__INST4_SEG3 = 0
|
|
UMC_BASE__INST4_SEG4 = 0
|
|
UMC_BASE__INST5_SEG0 = 0x00154000
|
|
UMC_BASE__INST5_SEG1 = 0x02426C00
|
|
UMC_BASE__INST5_SEG2 = 0
|
|
UMC_BASE__INST5_SEG3 = 0
|
|
UMC_BASE__INST5_SEG4 = 0
|
|
UMC_BASE__INST6_SEG0 = 0x00194000
|
|
UMC_BASE__INST6_SEG1 = 0x02427000
|
|
UMC_BASE__INST6_SEG2 = 0
|
|
UMC_BASE__INST6_SEG3 = 0
|
|
UMC_BASE__INST6_SEG4 = 0
|
|
USB0_BASE__INST0_SEG0 = 0x0242A800
|
|
USB0_BASE__INST0_SEG1 = 0x05B00000
|
|
USB0_BASE__INST0_SEG2 = 0
|
|
USB0_BASE__INST0_SEG3 = 0
|
|
USB0_BASE__INST0_SEG4 = 0
|
|
USB0_BASE__INST1_SEG0 = 0
|
|
USB0_BASE__INST1_SEG1 = 0
|
|
USB0_BASE__INST1_SEG2 = 0
|
|
USB0_BASE__INST1_SEG3 = 0
|
|
USB0_BASE__INST1_SEG4 = 0
|
|
USB0_BASE__INST2_SEG0 = 0
|
|
USB0_BASE__INST2_SEG1 = 0
|
|
USB0_BASE__INST2_SEG2 = 0
|
|
USB0_BASE__INST2_SEG3 = 0
|
|
USB0_BASE__INST2_SEG4 = 0
|
|
USB0_BASE__INST3_SEG0 = 0
|
|
USB0_BASE__INST3_SEG1 = 0
|
|
USB0_BASE__INST3_SEG2 = 0
|
|
USB0_BASE__INST3_SEG3 = 0
|
|
USB0_BASE__INST3_SEG4 = 0
|
|
USB0_BASE__INST4_SEG0 = 0
|
|
USB0_BASE__INST4_SEG1 = 0
|
|
USB0_BASE__INST4_SEG2 = 0
|
|
USB0_BASE__INST4_SEG3 = 0
|
|
USB0_BASE__INST4_SEG4 = 0
|
|
USB0_BASE__INST5_SEG0 = 0
|
|
USB0_BASE__INST5_SEG1 = 0
|
|
USB0_BASE__INST5_SEG2 = 0
|
|
USB0_BASE__INST5_SEG3 = 0
|
|
USB0_BASE__INST5_SEG4 = 0
|
|
USB0_BASE__INST6_SEG0 = 0
|
|
USB0_BASE__INST6_SEG1 = 0
|
|
USB0_BASE__INST6_SEG2 = 0
|
|
USB0_BASE__INST6_SEG3 = 0
|
|
USB0_BASE__INST6_SEG4 = 0
|
|
VCN_BASE__INST0_SEG0 = 0x00007800
|
|
VCN_BASE__INST0_SEG1 = 0x00007E00
|
|
VCN_BASE__INST0_SEG2 = 0x02403000
|
|
VCN_BASE__INST0_SEG3 = 0
|
|
VCN_BASE__INST0_SEG4 = 0
|
|
VCN_BASE__INST1_SEG0 = 0x00007B00
|
|
VCN_BASE__INST1_SEG1 = 0x00012000
|
|
VCN_BASE__INST1_SEG2 = 0x02445000
|
|
VCN_BASE__INST1_SEG3 = 0
|
|
VCN_BASE__INST1_SEG4 = 0
|
|
VCN_BASE__INST2_SEG0 = 0
|
|
VCN_BASE__INST2_SEG1 = 0
|
|
VCN_BASE__INST2_SEG2 = 0
|
|
VCN_BASE__INST2_SEG3 = 0
|
|
VCN_BASE__INST2_SEG4 = 0
|
|
VCN_BASE__INST3_SEG0 = 0
|
|
VCN_BASE__INST3_SEG1 = 0
|
|
VCN_BASE__INST3_SEG2 = 0
|
|
VCN_BASE__INST3_SEG3 = 0
|
|
VCN_BASE__INST3_SEG4 = 0
|
|
VCN_BASE__INST4_SEG0 = 0
|
|
VCN_BASE__INST4_SEG1 = 0
|
|
VCN_BASE__INST4_SEG2 = 0
|
|
VCN_BASE__INST4_SEG3 = 0
|
|
VCN_BASE__INST4_SEG4 = 0
|
|
VCN_BASE__INST5_SEG0 = 0
|
|
VCN_BASE__INST5_SEG1 = 0
|
|
VCN_BASE__INST5_SEG2 = 0
|
|
VCN_BASE__INST5_SEG3 = 0
|
|
VCN_BASE__INST5_SEG4 = 0
|
|
VCN_BASE__INST6_SEG0 = 0
|
|
VCN_BASE__INST6_SEG1 = 0
|
|
VCN_BASE__INST6_SEG2 = 0
|
|
VCN_BASE__INST6_SEG3 = 0
|
|
VCN_BASE__INST6_SEG4 = 0 |