774 lines
20 KiB
Python
774 lines
20 KiB
Python
# mypy: disable-error-code="empty-body"
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from __future__ import annotations
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import ctypes
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from typing import Literal, TypeAlias
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from tinygrad.runtime.support.c import _IO, _IOW, _IOR, _IOWR
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from tinygrad.runtime.support import c
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@c.record
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class struct_IP_BASE_INSTANCE(c.Struct):
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SIZE = 24
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segment: c.Array[ctypes.c_uint32, Literal[6]]
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struct_IP_BASE_INSTANCE.register_fields([('segment', c.Array[ctypes.c_uint32, Literal[6]], 0)])
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@c.record
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class struct_IP_BASE(c.Struct):
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SIZE = 144
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instance: c.Array[struct_IP_BASE_INSTANCE, Literal[6]]
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struct_IP_BASE.register_fields([('instance', c.Array[struct_IP_BASE_INSTANCE, Literal[6]], 0)])
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MAX_INSTANCE = 6
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MAX_SEGMENT = 6
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ATHUB_BASE__INST0_SEG0 = 0x00000C20
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ATHUB_BASE__INST0_SEG1 = 0
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ATHUB_BASE__INST0_SEG2 = 0
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ATHUB_BASE__INST0_SEG3 = 0
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ATHUB_BASE__INST0_SEG4 = 0
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ATHUB_BASE__INST0_SEG5 = 0
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ATHUB_BASE__INST1_SEG0 = 0
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ATHUB_BASE__INST1_SEG1 = 0
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ATHUB_BASE__INST1_SEG2 = 0
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ATHUB_BASE__INST1_SEG3 = 0
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ATHUB_BASE__INST1_SEG4 = 0
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ATHUB_BASE__INST1_SEG5 = 0
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ATHUB_BASE__INST2_SEG0 = 0
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ATHUB_BASE__INST2_SEG1 = 0
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ATHUB_BASE__INST2_SEG2 = 0
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ATHUB_BASE__INST2_SEG3 = 0
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ATHUB_BASE__INST2_SEG4 = 0
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ATHUB_BASE__INST2_SEG5 = 0
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ATHUB_BASE__INST3_SEG0 = 0
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ATHUB_BASE__INST3_SEG1 = 0
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ATHUB_BASE__INST3_SEG2 = 0
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ATHUB_BASE__INST3_SEG3 = 0
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ATHUB_BASE__INST3_SEG4 = 0
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ATHUB_BASE__INST3_SEG5 = 0
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ATHUB_BASE__INST4_SEG0 = 0
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ATHUB_BASE__INST4_SEG1 = 0
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ATHUB_BASE__INST4_SEG2 = 0
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ATHUB_BASE__INST4_SEG3 = 0
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ATHUB_BASE__INST4_SEG4 = 0
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ATHUB_BASE__INST4_SEG5 = 0
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ATHUB_BASE__INST5_SEG0 = 0
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ATHUB_BASE__INST5_SEG1 = 0
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ATHUB_BASE__INST5_SEG2 = 0
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ATHUB_BASE__INST5_SEG3 = 0
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ATHUB_BASE__INST5_SEG4 = 0
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ATHUB_BASE__INST5_SEG5 = 0
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CLK_BASE__INST0_SEG0 = 0x00016C00
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CLK_BASE__INST0_SEG1 = 0x00016E00
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CLK_BASE__INST0_SEG2 = 0x00017000
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CLK_BASE__INST0_SEG3 = 0x00017200
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CLK_BASE__INST0_SEG4 = 0x0001B000
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CLK_BASE__INST0_SEG5 = 0x0001B200
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CLK_BASE__INST1_SEG0 = 0
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CLK_BASE__INST1_SEG1 = 0
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CLK_BASE__INST1_SEG2 = 0
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CLK_BASE__INST1_SEG3 = 0
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CLK_BASE__INST1_SEG4 = 0
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CLK_BASE__INST1_SEG5 = 0
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CLK_BASE__INST2_SEG0 = 0
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CLK_BASE__INST2_SEG1 = 0
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CLK_BASE__INST2_SEG2 = 0
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CLK_BASE__INST2_SEG3 = 0
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CLK_BASE__INST2_SEG4 = 0
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CLK_BASE__INST2_SEG5 = 0
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CLK_BASE__INST3_SEG0 = 0
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CLK_BASE__INST3_SEG1 = 0
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CLK_BASE__INST3_SEG2 = 0
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CLK_BASE__INST3_SEG3 = 0
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CLK_BASE__INST3_SEG4 = 0
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CLK_BASE__INST3_SEG5 = 0
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CLK_BASE__INST4_SEG0 = 0
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CLK_BASE__INST4_SEG1 = 0
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CLK_BASE__INST4_SEG2 = 0
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CLK_BASE__INST4_SEG3 = 0
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CLK_BASE__INST4_SEG4 = 0
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CLK_BASE__INST4_SEG5 = 0
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CLK_BASE__INST5_SEG0 = 0
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CLK_BASE__INST5_SEG1 = 0
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CLK_BASE__INST5_SEG2 = 0
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CLK_BASE__INST5_SEG3 = 0
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CLK_BASE__INST5_SEG4 = 0
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CLK_BASE__INST5_SEG5 = 0
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DCE_BASE__INST0_SEG0 = 0x00000012
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DCE_BASE__INST0_SEG1 = 0x000000C0
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DCE_BASE__INST0_SEG2 = 0x000034C0
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DCE_BASE__INST0_SEG3 = 0
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DCE_BASE__INST0_SEG4 = 0
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DCE_BASE__INST0_SEG5 = 0
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DCE_BASE__INST1_SEG0 = 0
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DCE_BASE__INST1_SEG1 = 0
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DCE_BASE__INST1_SEG2 = 0
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DCE_BASE__INST1_SEG3 = 0
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DCE_BASE__INST1_SEG4 = 0
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DCE_BASE__INST1_SEG5 = 0
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DCE_BASE__INST2_SEG0 = 0
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DCE_BASE__INST2_SEG1 = 0
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DCE_BASE__INST2_SEG2 = 0
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DCE_BASE__INST2_SEG3 = 0
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DCE_BASE__INST2_SEG4 = 0
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DCE_BASE__INST2_SEG5 = 0
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DCE_BASE__INST3_SEG0 = 0
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DCE_BASE__INST3_SEG1 = 0
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DCE_BASE__INST3_SEG2 = 0
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DCE_BASE__INST3_SEG3 = 0
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DCE_BASE__INST3_SEG4 = 0
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DCE_BASE__INST3_SEG5 = 0
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DCE_BASE__INST4_SEG0 = 0
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DCE_BASE__INST4_SEG1 = 0
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DCE_BASE__INST4_SEG2 = 0
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DCE_BASE__INST4_SEG3 = 0
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DCE_BASE__INST4_SEG4 = 0
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DCE_BASE__INST4_SEG5 = 0
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DCE_BASE__INST5_SEG0 = 0
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DCE_BASE__INST5_SEG1 = 0
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DCE_BASE__INST5_SEG2 = 0
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DCE_BASE__INST5_SEG3 = 0
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DCE_BASE__INST5_SEG4 = 0
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DCE_BASE__INST5_SEG5 = 0
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DF_BASE__INST0_SEG0 = 0x00007000
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DF_BASE__INST0_SEG1 = 0
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DF_BASE__INST0_SEG2 = 0
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DF_BASE__INST0_SEG3 = 0
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DF_BASE__INST0_SEG4 = 0
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DF_BASE__INST0_SEG5 = 0
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DF_BASE__INST1_SEG0 = 0
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DF_BASE__INST1_SEG1 = 0
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DF_BASE__INST1_SEG2 = 0
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DF_BASE__INST1_SEG3 = 0
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DF_BASE__INST1_SEG4 = 0
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DF_BASE__INST1_SEG5 = 0
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DF_BASE__INST2_SEG0 = 0
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DF_BASE__INST2_SEG1 = 0
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DF_BASE__INST2_SEG2 = 0
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DF_BASE__INST2_SEG3 = 0
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DF_BASE__INST2_SEG4 = 0
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DF_BASE__INST2_SEG5 = 0
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DF_BASE__INST3_SEG0 = 0
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DF_BASE__INST3_SEG1 = 0
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DF_BASE__INST3_SEG2 = 0
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DF_BASE__INST3_SEG3 = 0
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DF_BASE__INST3_SEG4 = 0
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DF_BASE__INST3_SEG5 = 0
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DF_BASE__INST4_SEG0 = 0
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DF_BASE__INST4_SEG1 = 0
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DF_BASE__INST4_SEG2 = 0
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DF_BASE__INST4_SEG3 = 0
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DF_BASE__INST4_SEG4 = 0
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DF_BASE__INST4_SEG5 = 0
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DF_BASE__INST5_SEG0 = 0
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DF_BASE__INST5_SEG1 = 0
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DF_BASE__INST5_SEG2 = 0
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DF_BASE__INST5_SEG3 = 0
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DF_BASE__INST5_SEG4 = 0
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DF_BASE__INST5_SEG5 = 0
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FUSE_BASE__INST0_SEG0 = 0x00017400
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FUSE_BASE__INST0_SEG1 = 0
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FUSE_BASE__INST0_SEG2 = 0
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FUSE_BASE__INST0_SEG3 = 0
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FUSE_BASE__INST0_SEG4 = 0
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FUSE_BASE__INST0_SEG5 = 0
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FUSE_BASE__INST1_SEG0 = 0
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FUSE_BASE__INST1_SEG1 = 0
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FUSE_BASE__INST1_SEG2 = 0
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FUSE_BASE__INST1_SEG3 = 0
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FUSE_BASE__INST1_SEG4 = 0
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FUSE_BASE__INST1_SEG5 = 0
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FUSE_BASE__INST2_SEG0 = 0
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FUSE_BASE__INST2_SEG1 = 0
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FUSE_BASE__INST2_SEG2 = 0
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FUSE_BASE__INST2_SEG3 = 0
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FUSE_BASE__INST2_SEG4 = 0
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FUSE_BASE__INST2_SEG5 = 0
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FUSE_BASE__INST3_SEG0 = 0
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FUSE_BASE__INST3_SEG1 = 0
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FUSE_BASE__INST3_SEG2 = 0
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FUSE_BASE__INST3_SEG3 = 0
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FUSE_BASE__INST3_SEG4 = 0
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FUSE_BASE__INST3_SEG5 = 0
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FUSE_BASE__INST4_SEG0 = 0
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FUSE_BASE__INST4_SEG1 = 0
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FUSE_BASE__INST4_SEG2 = 0
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FUSE_BASE__INST4_SEG3 = 0
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FUSE_BASE__INST4_SEG4 = 0
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FUSE_BASE__INST4_SEG5 = 0
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FUSE_BASE__INST5_SEG0 = 0
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FUSE_BASE__INST5_SEG1 = 0
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FUSE_BASE__INST5_SEG2 = 0
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FUSE_BASE__INST5_SEG3 = 0
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FUSE_BASE__INST5_SEG4 = 0
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FUSE_BASE__INST5_SEG5 = 0
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GC_BASE__INST0_SEG0 = 0x00002000
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GC_BASE__INST0_SEG1 = 0x0000A000
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GC_BASE__INST0_SEG2 = 0
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GC_BASE__INST0_SEG3 = 0
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GC_BASE__INST0_SEG4 = 0
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GC_BASE__INST0_SEG5 = 0
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GC_BASE__INST1_SEG0 = 0
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GC_BASE__INST1_SEG1 = 0
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GC_BASE__INST1_SEG2 = 0
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GC_BASE__INST1_SEG3 = 0
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GC_BASE__INST1_SEG4 = 0
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GC_BASE__INST1_SEG5 = 0
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GC_BASE__INST2_SEG0 = 0
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GC_BASE__INST2_SEG1 = 0
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GC_BASE__INST2_SEG2 = 0
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GC_BASE__INST2_SEG3 = 0
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GC_BASE__INST2_SEG4 = 0
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GC_BASE__INST2_SEG5 = 0
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GC_BASE__INST3_SEG0 = 0
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GC_BASE__INST3_SEG1 = 0
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GC_BASE__INST3_SEG2 = 0
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GC_BASE__INST3_SEG3 = 0
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GC_BASE__INST3_SEG4 = 0
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GC_BASE__INST3_SEG5 = 0
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GC_BASE__INST4_SEG0 = 0
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GC_BASE__INST4_SEG1 = 0
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GC_BASE__INST4_SEG2 = 0
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GC_BASE__INST4_SEG3 = 0
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GC_BASE__INST4_SEG4 = 0
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GC_BASE__INST4_SEG5 = 0
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GC_BASE__INST5_SEG0 = 0
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GC_BASE__INST5_SEG1 = 0
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GC_BASE__INST5_SEG2 = 0
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GC_BASE__INST5_SEG3 = 0
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GC_BASE__INST5_SEG4 = 0
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GC_BASE__INST5_SEG5 = 0
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HDP_BASE__INST0_SEG0 = 0x00000F20
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HDP_BASE__INST0_SEG1 = 0
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HDP_BASE__INST0_SEG2 = 0
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HDP_BASE__INST0_SEG3 = 0
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HDP_BASE__INST0_SEG4 = 0
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HDP_BASE__INST0_SEG5 = 0
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HDP_BASE__INST1_SEG0 = 0
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HDP_BASE__INST1_SEG1 = 0
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HDP_BASE__INST1_SEG2 = 0
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HDP_BASE__INST1_SEG3 = 0
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HDP_BASE__INST1_SEG4 = 0
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HDP_BASE__INST1_SEG5 = 0
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HDP_BASE__INST2_SEG0 = 0
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HDP_BASE__INST2_SEG1 = 0
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HDP_BASE__INST2_SEG2 = 0
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HDP_BASE__INST2_SEG3 = 0
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HDP_BASE__INST2_SEG4 = 0
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HDP_BASE__INST2_SEG5 = 0
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HDP_BASE__INST3_SEG0 = 0
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HDP_BASE__INST3_SEG1 = 0
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HDP_BASE__INST3_SEG2 = 0
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HDP_BASE__INST3_SEG3 = 0
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HDP_BASE__INST3_SEG4 = 0
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HDP_BASE__INST3_SEG5 = 0
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HDP_BASE__INST4_SEG0 = 0
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HDP_BASE__INST4_SEG1 = 0
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HDP_BASE__INST4_SEG2 = 0
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HDP_BASE__INST4_SEG3 = 0
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HDP_BASE__INST4_SEG4 = 0
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HDP_BASE__INST4_SEG5 = 0
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HDP_BASE__INST5_SEG0 = 0
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HDP_BASE__INST5_SEG1 = 0
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HDP_BASE__INST5_SEG2 = 0
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HDP_BASE__INST5_SEG3 = 0
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HDP_BASE__INST5_SEG4 = 0
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HDP_BASE__INST5_SEG5 = 0
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MMHUB_BASE__INST0_SEG0 = 0x0001A000
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MMHUB_BASE__INST0_SEG1 = 0
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MMHUB_BASE__INST0_SEG2 = 0
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MMHUB_BASE__INST0_SEG3 = 0
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MMHUB_BASE__INST0_SEG4 = 0
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MMHUB_BASE__INST0_SEG5 = 0
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MMHUB_BASE__INST1_SEG0 = 0
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MMHUB_BASE__INST1_SEG1 = 0
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MMHUB_BASE__INST1_SEG2 = 0
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MMHUB_BASE__INST1_SEG3 = 0
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MMHUB_BASE__INST1_SEG4 = 0
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MMHUB_BASE__INST1_SEG5 = 0
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MMHUB_BASE__INST2_SEG0 = 0
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MMHUB_BASE__INST2_SEG1 = 0
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MMHUB_BASE__INST2_SEG2 = 0
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MMHUB_BASE__INST2_SEG3 = 0
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MMHUB_BASE__INST2_SEG4 = 0
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MMHUB_BASE__INST2_SEG5 = 0
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MMHUB_BASE__INST3_SEG0 = 0
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MMHUB_BASE__INST3_SEG1 = 0
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MMHUB_BASE__INST3_SEG2 = 0
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MMHUB_BASE__INST3_SEG3 = 0
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MMHUB_BASE__INST3_SEG4 = 0
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MMHUB_BASE__INST3_SEG5 = 0
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MMHUB_BASE__INST4_SEG0 = 0
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MMHUB_BASE__INST4_SEG1 = 0
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MMHUB_BASE__INST4_SEG2 = 0
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MMHUB_BASE__INST4_SEG3 = 0
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MMHUB_BASE__INST4_SEG4 = 0
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MMHUB_BASE__INST4_SEG5 = 0
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MMHUB_BASE__INST5_SEG0 = 0
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MMHUB_BASE__INST5_SEG1 = 0
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MMHUB_BASE__INST5_SEG2 = 0
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MMHUB_BASE__INST5_SEG3 = 0
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MMHUB_BASE__INST5_SEG4 = 0
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MMHUB_BASE__INST5_SEG5 = 0
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MP0_BASE__INST0_SEG0 = 0x00016000
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MP0_BASE__INST0_SEG1 = 0
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MP0_BASE__INST0_SEG2 = 0
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MP0_BASE__INST0_SEG3 = 0
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MP0_BASE__INST0_SEG4 = 0
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MP0_BASE__INST0_SEG5 = 0
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MP0_BASE__INST1_SEG0 = 0
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MP0_BASE__INST1_SEG1 = 0
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MP0_BASE__INST1_SEG2 = 0
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MP0_BASE__INST1_SEG3 = 0
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MP0_BASE__INST1_SEG4 = 0
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MP0_BASE__INST1_SEG5 = 0
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MP0_BASE__INST2_SEG0 = 0
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MP0_BASE__INST2_SEG1 = 0
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MP0_BASE__INST2_SEG2 = 0
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MP0_BASE__INST2_SEG3 = 0
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MP0_BASE__INST2_SEG4 = 0
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MP0_BASE__INST2_SEG5 = 0
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MP0_BASE__INST3_SEG0 = 0
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MP0_BASE__INST3_SEG1 = 0
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MP0_BASE__INST3_SEG2 = 0
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MP0_BASE__INST3_SEG3 = 0
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MP0_BASE__INST3_SEG4 = 0
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MP0_BASE__INST3_SEG5 = 0
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MP0_BASE__INST4_SEG0 = 0
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MP0_BASE__INST4_SEG1 = 0
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MP0_BASE__INST4_SEG2 = 0
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MP0_BASE__INST4_SEG3 = 0
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MP0_BASE__INST4_SEG4 = 0
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MP0_BASE__INST4_SEG5 = 0
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MP0_BASE__INST5_SEG0 = 0
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MP0_BASE__INST5_SEG1 = 0
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MP0_BASE__INST5_SEG2 = 0
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MP0_BASE__INST5_SEG3 = 0
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MP0_BASE__INST5_SEG4 = 0
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MP0_BASE__INST5_SEG5 = 0
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MP1_BASE__INST0_SEG0 = 0x00016000
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MP1_BASE__INST0_SEG1 = 0
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MP1_BASE__INST0_SEG2 = 0
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MP1_BASE__INST0_SEG3 = 0
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MP1_BASE__INST0_SEG4 = 0
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MP1_BASE__INST0_SEG5 = 0
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MP1_BASE__INST1_SEG0 = 0
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MP1_BASE__INST1_SEG1 = 0
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MP1_BASE__INST1_SEG2 = 0
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MP1_BASE__INST1_SEG3 = 0
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MP1_BASE__INST1_SEG4 = 0
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MP1_BASE__INST1_SEG5 = 0
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MP1_BASE__INST2_SEG0 = 0
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MP1_BASE__INST2_SEG1 = 0
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MP1_BASE__INST2_SEG2 = 0
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MP1_BASE__INST2_SEG3 = 0
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MP1_BASE__INST2_SEG4 = 0
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MP1_BASE__INST2_SEG5 = 0
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MP1_BASE__INST3_SEG0 = 0
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MP1_BASE__INST3_SEG1 = 0
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MP1_BASE__INST3_SEG2 = 0
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MP1_BASE__INST3_SEG3 = 0
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MP1_BASE__INST3_SEG4 = 0
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MP1_BASE__INST3_SEG5 = 0
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MP1_BASE__INST4_SEG0 = 0
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MP1_BASE__INST4_SEG1 = 0
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MP1_BASE__INST4_SEG2 = 0
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MP1_BASE__INST4_SEG3 = 0
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MP1_BASE__INST4_SEG4 = 0
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MP1_BASE__INST4_SEG5 = 0
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MP1_BASE__INST5_SEG0 = 0
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MP1_BASE__INST5_SEG1 = 0
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MP1_BASE__INST5_SEG2 = 0
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MP1_BASE__INST5_SEG3 = 0
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MP1_BASE__INST5_SEG4 = 0
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MP1_BASE__INST5_SEG5 = 0
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NBIO_BASE__INST0_SEG0 = 0x00000000
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NBIO_BASE__INST0_SEG1 = 0x00000014
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NBIO_BASE__INST0_SEG2 = 0x00000D20
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NBIO_BASE__INST0_SEG3 = 0x00010400
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NBIO_BASE__INST0_SEG4 = 0
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NBIO_BASE__INST0_SEG5 = 0
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NBIO_BASE__INST1_SEG0 = 0
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NBIO_BASE__INST1_SEG1 = 0
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NBIO_BASE__INST1_SEG2 = 0
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NBIO_BASE__INST1_SEG3 = 0
|
|
NBIO_BASE__INST1_SEG4 = 0
|
|
NBIO_BASE__INST1_SEG5 = 0
|
|
NBIO_BASE__INST2_SEG0 = 0
|
|
NBIO_BASE__INST2_SEG1 = 0
|
|
NBIO_BASE__INST2_SEG2 = 0
|
|
NBIO_BASE__INST2_SEG3 = 0
|
|
NBIO_BASE__INST2_SEG4 = 0
|
|
NBIO_BASE__INST2_SEG5 = 0
|
|
NBIO_BASE__INST3_SEG0 = 0
|
|
NBIO_BASE__INST3_SEG1 = 0
|
|
NBIO_BASE__INST3_SEG2 = 0
|
|
NBIO_BASE__INST3_SEG3 = 0
|
|
NBIO_BASE__INST3_SEG4 = 0
|
|
NBIO_BASE__INST3_SEG5 = 0
|
|
NBIO_BASE__INST4_SEG0 = 0
|
|
NBIO_BASE__INST4_SEG1 = 0
|
|
NBIO_BASE__INST4_SEG2 = 0
|
|
NBIO_BASE__INST4_SEG3 = 0
|
|
NBIO_BASE__INST4_SEG4 = 0
|
|
NBIO_BASE__INST4_SEG5 = 0
|
|
NBIO_BASE__INST5_SEG0 = 0
|
|
NBIO_BASE__INST5_SEG1 = 0
|
|
NBIO_BASE__INST5_SEG2 = 0
|
|
NBIO_BASE__INST5_SEG3 = 0
|
|
NBIO_BASE__INST5_SEG4 = 0
|
|
NBIO_BASE__INST5_SEG5 = 0
|
|
OSSSYS_BASE__INST0_SEG0 = 0x000010A0
|
|
OSSSYS_BASE__INST0_SEG1 = 0
|
|
OSSSYS_BASE__INST0_SEG2 = 0
|
|
OSSSYS_BASE__INST0_SEG3 = 0
|
|
OSSSYS_BASE__INST0_SEG4 = 0
|
|
OSSSYS_BASE__INST0_SEG5 = 0
|
|
OSSSYS_BASE__INST1_SEG0 = 0
|
|
OSSSYS_BASE__INST1_SEG1 = 0
|
|
OSSSYS_BASE__INST1_SEG2 = 0
|
|
OSSSYS_BASE__INST1_SEG3 = 0
|
|
OSSSYS_BASE__INST1_SEG4 = 0
|
|
OSSSYS_BASE__INST1_SEG5 = 0
|
|
OSSSYS_BASE__INST2_SEG0 = 0
|
|
OSSSYS_BASE__INST2_SEG1 = 0
|
|
OSSSYS_BASE__INST2_SEG2 = 0
|
|
OSSSYS_BASE__INST2_SEG3 = 0
|
|
OSSSYS_BASE__INST2_SEG4 = 0
|
|
OSSSYS_BASE__INST2_SEG5 = 0
|
|
OSSSYS_BASE__INST3_SEG0 = 0
|
|
OSSSYS_BASE__INST3_SEG1 = 0
|
|
OSSSYS_BASE__INST3_SEG2 = 0
|
|
OSSSYS_BASE__INST3_SEG3 = 0
|
|
OSSSYS_BASE__INST3_SEG4 = 0
|
|
OSSSYS_BASE__INST3_SEG5 = 0
|
|
OSSSYS_BASE__INST4_SEG0 = 0
|
|
OSSSYS_BASE__INST4_SEG1 = 0
|
|
OSSSYS_BASE__INST4_SEG2 = 0
|
|
OSSSYS_BASE__INST4_SEG3 = 0
|
|
OSSSYS_BASE__INST4_SEG4 = 0
|
|
OSSSYS_BASE__INST4_SEG5 = 0
|
|
OSSSYS_BASE__INST5_SEG0 = 0
|
|
OSSSYS_BASE__INST5_SEG1 = 0
|
|
OSSSYS_BASE__INST5_SEG2 = 0
|
|
OSSSYS_BASE__INST5_SEG3 = 0
|
|
OSSSYS_BASE__INST5_SEG4 = 0
|
|
OSSSYS_BASE__INST5_SEG5 = 0
|
|
SDMA0_BASE__INST0_SEG0 = 0x00001260
|
|
SDMA0_BASE__INST0_SEG1 = 0
|
|
SDMA0_BASE__INST0_SEG2 = 0
|
|
SDMA0_BASE__INST0_SEG3 = 0
|
|
SDMA0_BASE__INST0_SEG4 = 0
|
|
SDMA0_BASE__INST0_SEG5 = 0
|
|
SDMA0_BASE__INST1_SEG0 = 0
|
|
SDMA0_BASE__INST1_SEG1 = 0
|
|
SDMA0_BASE__INST1_SEG2 = 0
|
|
SDMA0_BASE__INST1_SEG3 = 0
|
|
SDMA0_BASE__INST1_SEG4 = 0
|
|
SDMA0_BASE__INST1_SEG5 = 0
|
|
SDMA0_BASE__INST2_SEG0 = 0
|
|
SDMA0_BASE__INST2_SEG1 = 0
|
|
SDMA0_BASE__INST2_SEG2 = 0
|
|
SDMA0_BASE__INST2_SEG3 = 0
|
|
SDMA0_BASE__INST2_SEG4 = 0
|
|
SDMA0_BASE__INST2_SEG5 = 0
|
|
SDMA0_BASE__INST3_SEG0 = 0
|
|
SDMA0_BASE__INST3_SEG1 = 0
|
|
SDMA0_BASE__INST3_SEG2 = 0
|
|
SDMA0_BASE__INST3_SEG3 = 0
|
|
SDMA0_BASE__INST3_SEG4 = 0
|
|
SDMA0_BASE__INST3_SEG5 = 0
|
|
SDMA0_BASE__INST4_SEG0 = 0
|
|
SDMA0_BASE__INST4_SEG1 = 0
|
|
SDMA0_BASE__INST4_SEG2 = 0
|
|
SDMA0_BASE__INST4_SEG3 = 0
|
|
SDMA0_BASE__INST4_SEG4 = 0
|
|
SDMA0_BASE__INST4_SEG5 = 0
|
|
SDMA0_BASE__INST5_SEG0 = 0
|
|
SDMA0_BASE__INST5_SEG1 = 0
|
|
SDMA0_BASE__INST5_SEG2 = 0
|
|
SDMA0_BASE__INST5_SEG3 = 0
|
|
SDMA0_BASE__INST5_SEG4 = 0
|
|
SDMA0_BASE__INST5_SEG5 = 0
|
|
SDMA1_BASE__INST0_SEG0 = 0x00001860
|
|
SDMA1_BASE__INST0_SEG1 = 0
|
|
SDMA1_BASE__INST0_SEG2 = 0
|
|
SDMA1_BASE__INST0_SEG3 = 0
|
|
SDMA1_BASE__INST0_SEG4 = 0
|
|
SDMA1_BASE__INST0_SEG5 = 0
|
|
SDMA1_BASE__INST1_SEG0 = 0
|
|
SDMA1_BASE__INST1_SEG1 = 0
|
|
SDMA1_BASE__INST1_SEG2 = 0
|
|
SDMA1_BASE__INST1_SEG3 = 0
|
|
SDMA1_BASE__INST1_SEG4 = 0
|
|
SDMA1_BASE__INST1_SEG5 = 0
|
|
SDMA1_BASE__INST2_SEG0 = 0
|
|
SDMA1_BASE__INST2_SEG1 = 0
|
|
SDMA1_BASE__INST2_SEG2 = 0
|
|
SDMA1_BASE__INST2_SEG3 = 0
|
|
SDMA1_BASE__INST2_SEG4 = 0
|
|
SDMA1_BASE__INST2_SEG5 = 0
|
|
SDMA1_BASE__INST3_SEG0 = 0
|
|
SDMA1_BASE__INST3_SEG1 = 0
|
|
SDMA1_BASE__INST3_SEG2 = 0
|
|
SDMA1_BASE__INST3_SEG3 = 0
|
|
SDMA1_BASE__INST3_SEG4 = 0
|
|
SDMA1_BASE__INST3_SEG5 = 0
|
|
SDMA1_BASE__INST4_SEG0 = 0
|
|
SDMA1_BASE__INST4_SEG1 = 0
|
|
SDMA1_BASE__INST4_SEG2 = 0
|
|
SDMA1_BASE__INST4_SEG3 = 0
|
|
SDMA1_BASE__INST4_SEG4 = 0
|
|
SDMA1_BASE__INST4_SEG5 = 0
|
|
SDMA1_BASE__INST5_SEG0 = 0
|
|
SDMA1_BASE__INST5_SEG1 = 0
|
|
SDMA1_BASE__INST5_SEG2 = 0
|
|
SDMA1_BASE__INST5_SEG3 = 0
|
|
SDMA1_BASE__INST5_SEG4 = 0
|
|
SDMA1_BASE__INST5_SEG5 = 0
|
|
SMUIO_BASE__INST0_SEG0 = 0x00016800
|
|
SMUIO_BASE__INST0_SEG1 = 0x00016A00
|
|
SMUIO_BASE__INST0_SEG2 = 0
|
|
SMUIO_BASE__INST0_SEG3 = 0
|
|
SMUIO_BASE__INST0_SEG4 = 0
|
|
SMUIO_BASE__INST0_SEG5 = 0
|
|
SMUIO_BASE__INST1_SEG0 = 0
|
|
SMUIO_BASE__INST1_SEG1 = 0
|
|
SMUIO_BASE__INST1_SEG2 = 0
|
|
SMUIO_BASE__INST1_SEG3 = 0
|
|
SMUIO_BASE__INST1_SEG4 = 0
|
|
SMUIO_BASE__INST1_SEG5 = 0
|
|
SMUIO_BASE__INST2_SEG0 = 0
|
|
SMUIO_BASE__INST2_SEG1 = 0
|
|
SMUIO_BASE__INST2_SEG2 = 0
|
|
SMUIO_BASE__INST2_SEG3 = 0
|
|
SMUIO_BASE__INST2_SEG4 = 0
|
|
SMUIO_BASE__INST2_SEG5 = 0
|
|
SMUIO_BASE__INST3_SEG0 = 0
|
|
SMUIO_BASE__INST3_SEG1 = 0
|
|
SMUIO_BASE__INST3_SEG2 = 0
|
|
SMUIO_BASE__INST3_SEG3 = 0
|
|
SMUIO_BASE__INST3_SEG4 = 0
|
|
SMUIO_BASE__INST3_SEG5 = 0
|
|
SMUIO_BASE__INST4_SEG0 = 0
|
|
SMUIO_BASE__INST4_SEG1 = 0
|
|
SMUIO_BASE__INST4_SEG2 = 0
|
|
SMUIO_BASE__INST4_SEG3 = 0
|
|
SMUIO_BASE__INST4_SEG4 = 0
|
|
SMUIO_BASE__INST4_SEG5 = 0
|
|
SMUIO_BASE__INST5_SEG0 = 0
|
|
SMUIO_BASE__INST5_SEG1 = 0
|
|
SMUIO_BASE__INST5_SEG2 = 0
|
|
SMUIO_BASE__INST5_SEG3 = 0
|
|
SMUIO_BASE__INST5_SEG4 = 0
|
|
SMUIO_BASE__INST5_SEG5 = 0
|
|
THM_BASE__INST0_SEG0 = 0x00016600
|
|
THM_BASE__INST0_SEG1 = 0
|
|
THM_BASE__INST0_SEG2 = 0
|
|
THM_BASE__INST0_SEG3 = 0
|
|
THM_BASE__INST0_SEG4 = 0
|
|
THM_BASE__INST0_SEG5 = 0
|
|
THM_BASE__INST1_SEG0 = 0
|
|
THM_BASE__INST1_SEG1 = 0
|
|
THM_BASE__INST1_SEG2 = 0
|
|
THM_BASE__INST1_SEG3 = 0
|
|
THM_BASE__INST1_SEG4 = 0
|
|
THM_BASE__INST1_SEG5 = 0
|
|
THM_BASE__INST2_SEG0 = 0
|
|
THM_BASE__INST2_SEG1 = 0
|
|
THM_BASE__INST2_SEG2 = 0
|
|
THM_BASE__INST2_SEG3 = 0
|
|
THM_BASE__INST2_SEG4 = 0
|
|
THM_BASE__INST2_SEG5 = 0
|
|
THM_BASE__INST3_SEG0 = 0
|
|
THM_BASE__INST3_SEG1 = 0
|
|
THM_BASE__INST3_SEG2 = 0
|
|
THM_BASE__INST3_SEG3 = 0
|
|
THM_BASE__INST3_SEG4 = 0
|
|
THM_BASE__INST3_SEG5 = 0
|
|
THM_BASE__INST4_SEG0 = 0
|
|
THM_BASE__INST4_SEG1 = 0
|
|
THM_BASE__INST4_SEG2 = 0
|
|
THM_BASE__INST4_SEG3 = 0
|
|
THM_BASE__INST4_SEG4 = 0
|
|
THM_BASE__INST4_SEG5 = 0
|
|
THM_BASE__INST5_SEG0 = 0
|
|
THM_BASE__INST5_SEG1 = 0
|
|
THM_BASE__INST5_SEG2 = 0
|
|
THM_BASE__INST5_SEG3 = 0
|
|
THM_BASE__INST5_SEG4 = 0
|
|
THM_BASE__INST5_SEG5 = 0
|
|
UMC_BASE__INST0_SEG0 = 0x00014000
|
|
UMC_BASE__INST0_SEG1 = 0
|
|
UMC_BASE__INST0_SEG2 = 0
|
|
UMC_BASE__INST0_SEG3 = 0
|
|
UMC_BASE__INST0_SEG4 = 0
|
|
UMC_BASE__INST0_SEG5 = 0
|
|
UMC_BASE__INST1_SEG0 = 0
|
|
UMC_BASE__INST1_SEG1 = 0
|
|
UMC_BASE__INST1_SEG2 = 0
|
|
UMC_BASE__INST1_SEG3 = 0
|
|
UMC_BASE__INST1_SEG4 = 0
|
|
UMC_BASE__INST1_SEG5 = 0
|
|
UMC_BASE__INST2_SEG0 = 0
|
|
UMC_BASE__INST2_SEG1 = 0
|
|
UMC_BASE__INST2_SEG2 = 0
|
|
UMC_BASE__INST2_SEG3 = 0
|
|
UMC_BASE__INST2_SEG4 = 0
|
|
UMC_BASE__INST2_SEG5 = 0
|
|
UMC_BASE__INST3_SEG0 = 0
|
|
UMC_BASE__INST3_SEG1 = 0
|
|
UMC_BASE__INST3_SEG2 = 0
|
|
UMC_BASE__INST3_SEG3 = 0
|
|
UMC_BASE__INST3_SEG4 = 0
|
|
UMC_BASE__INST3_SEG5 = 0
|
|
UMC_BASE__INST4_SEG0 = 0
|
|
UMC_BASE__INST4_SEG1 = 0
|
|
UMC_BASE__INST4_SEG2 = 0
|
|
UMC_BASE__INST4_SEG3 = 0
|
|
UMC_BASE__INST4_SEG4 = 0
|
|
UMC_BASE__INST4_SEG5 = 0
|
|
UMC_BASE__INST5_SEG0 = 0
|
|
UMC_BASE__INST5_SEG1 = 0
|
|
UMC_BASE__INST5_SEG2 = 0
|
|
UMC_BASE__INST5_SEG3 = 0
|
|
UMC_BASE__INST5_SEG4 = 0
|
|
UMC_BASE__INST5_SEG5 = 0
|
|
UVD_BASE__INST0_SEG0 = 0x00007800
|
|
UVD_BASE__INST0_SEG1 = 0x00007E00
|
|
UVD_BASE__INST0_SEG2 = 0
|
|
UVD_BASE__INST0_SEG3 = 0
|
|
UVD_BASE__INST0_SEG4 = 0
|
|
UVD_BASE__INST0_SEG5 = 0
|
|
UVD_BASE__INST1_SEG0 = 0
|
|
UVD_BASE__INST1_SEG1 = 0x00009000
|
|
UVD_BASE__INST1_SEG2 = 0
|
|
UVD_BASE__INST1_SEG3 = 0
|
|
UVD_BASE__INST1_SEG4 = 0
|
|
UVD_BASE__INST1_SEG5 = 0
|
|
UVD_BASE__INST2_SEG0 = 0
|
|
UVD_BASE__INST2_SEG1 = 0
|
|
UVD_BASE__INST2_SEG2 = 0
|
|
UVD_BASE__INST2_SEG3 = 0
|
|
UVD_BASE__INST2_SEG4 = 0
|
|
UVD_BASE__INST2_SEG5 = 0
|
|
UVD_BASE__INST3_SEG0 = 0
|
|
UVD_BASE__INST3_SEG1 = 0
|
|
UVD_BASE__INST3_SEG2 = 0
|
|
UVD_BASE__INST3_SEG3 = 0
|
|
UVD_BASE__INST3_SEG4 = 0
|
|
UVD_BASE__INST3_SEG5 = 0
|
|
UVD_BASE__INST4_SEG0 = 0
|
|
UVD_BASE__INST4_SEG1 = 0
|
|
UVD_BASE__INST4_SEG2 = 0
|
|
UVD_BASE__INST4_SEG3 = 0
|
|
UVD_BASE__INST4_SEG4 = 0
|
|
UVD_BASE__INST4_SEG5 = 0
|
|
UVD_BASE__INST5_SEG0 = 0
|
|
UVD_BASE__INST5_SEG1 = 0
|
|
UVD_BASE__INST5_SEG2 = 0
|
|
UVD_BASE__INST5_SEG3 = 0
|
|
UVD_BASE__INST5_SEG4 = 0
|
|
UVD_BASE__INST5_SEG5 = 0
|
|
VCE_BASE__INST0_SEG0 = 0x00008800
|
|
VCE_BASE__INST0_SEG1 = 0
|
|
VCE_BASE__INST0_SEG2 = 0
|
|
VCE_BASE__INST0_SEG3 = 0
|
|
VCE_BASE__INST0_SEG4 = 0
|
|
VCE_BASE__INST0_SEG5 = 0
|
|
VCE_BASE__INST1_SEG0 = 0
|
|
VCE_BASE__INST1_SEG1 = 0
|
|
VCE_BASE__INST1_SEG2 = 0
|
|
VCE_BASE__INST1_SEG3 = 0
|
|
VCE_BASE__INST1_SEG4 = 0
|
|
VCE_BASE__INST1_SEG5 = 0
|
|
VCE_BASE__INST2_SEG0 = 0
|
|
VCE_BASE__INST2_SEG1 = 0
|
|
VCE_BASE__INST2_SEG2 = 0
|
|
VCE_BASE__INST2_SEG3 = 0
|
|
VCE_BASE__INST2_SEG4 = 0
|
|
VCE_BASE__INST2_SEG5 = 0
|
|
VCE_BASE__INST3_SEG0 = 0
|
|
VCE_BASE__INST3_SEG1 = 0
|
|
VCE_BASE__INST3_SEG2 = 0
|
|
VCE_BASE__INST3_SEG3 = 0
|
|
VCE_BASE__INST3_SEG4 = 0
|
|
VCE_BASE__INST3_SEG5 = 0
|
|
VCE_BASE__INST4_SEG0 = 0
|
|
VCE_BASE__INST4_SEG1 = 0
|
|
VCE_BASE__INST4_SEG2 = 0
|
|
VCE_BASE__INST4_SEG3 = 0
|
|
VCE_BASE__INST4_SEG4 = 0
|
|
VCE_BASE__INST4_SEG5 = 0
|
|
VCE_BASE__INST5_SEG0 = 0
|
|
VCE_BASE__INST5_SEG1 = 0
|
|
VCE_BASE__INST5_SEG2 = 0
|
|
VCE_BASE__INST5_SEG3 = 0
|
|
VCE_BASE__INST5_SEG4 = 0
|
|
VCE_BASE__INST5_SEG5 = 0
|
|
XDMA_BASE__INST0_SEG0 = 0x00003400
|
|
XDMA_BASE__INST0_SEG1 = 0
|
|
XDMA_BASE__INST0_SEG2 = 0
|
|
XDMA_BASE__INST0_SEG3 = 0
|
|
XDMA_BASE__INST0_SEG4 = 0
|
|
XDMA_BASE__INST0_SEG5 = 0
|
|
XDMA_BASE__INST1_SEG0 = 0
|
|
XDMA_BASE__INST1_SEG1 = 0
|
|
XDMA_BASE__INST1_SEG2 = 0
|
|
XDMA_BASE__INST1_SEG3 = 0
|
|
XDMA_BASE__INST1_SEG4 = 0
|
|
XDMA_BASE__INST1_SEG5 = 0
|
|
XDMA_BASE__INST2_SEG0 = 0
|
|
XDMA_BASE__INST2_SEG1 = 0
|
|
XDMA_BASE__INST2_SEG2 = 0
|
|
XDMA_BASE__INST2_SEG3 = 0
|
|
XDMA_BASE__INST2_SEG4 = 0
|
|
XDMA_BASE__INST2_SEG5 = 0
|
|
XDMA_BASE__INST3_SEG0 = 0
|
|
XDMA_BASE__INST3_SEG1 = 0
|
|
XDMA_BASE__INST3_SEG2 = 0
|
|
XDMA_BASE__INST3_SEG3 = 0
|
|
XDMA_BASE__INST3_SEG4 = 0
|
|
XDMA_BASE__INST3_SEG5 = 0
|
|
XDMA_BASE__INST4_SEG0 = 0
|
|
XDMA_BASE__INST4_SEG1 = 0
|
|
XDMA_BASE__INST4_SEG2 = 0
|
|
XDMA_BASE__INST4_SEG3 = 0
|
|
XDMA_BASE__INST4_SEG4 = 0
|
|
XDMA_BASE__INST4_SEG5 = 0
|
|
XDMA_BASE__INST5_SEG0 = 0
|
|
XDMA_BASE__INST5_SEG1 = 0
|
|
XDMA_BASE__INST5_SEG2 = 0
|
|
XDMA_BASE__INST5_SEG3 = 0
|
|
XDMA_BASE__INST5_SEG4 = 0
|
|
XDMA_BASE__INST5_SEG5 = 0
|
|
RSMU_BASE__INST0_SEG0 = 0x00012000
|
|
RSMU_BASE__INST0_SEG1 = 0
|
|
RSMU_BASE__INST0_SEG2 = 0
|
|
RSMU_BASE__INST0_SEG3 = 0
|
|
RSMU_BASE__INST0_SEG4 = 0
|
|
RSMU_BASE__INST0_SEG5 = 0
|
|
RSMU_BASE__INST1_SEG0 = 0
|
|
RSMU_BASE__INST1_SEG1 = 0
|
|
RSMU_BASE__INST1_SEG2 = 0
|
|
RSMU_BASE__INST1_SEG3 = 0
|
|
RSMU_BASE__INST1_SEG4 = 0
|
|
RSMU_BASE__INST1_SEG5 = 0
|
|
RSMU_BASE__INST2_SEG0 = 0
|
|
RSMU_BASE__INST2_SEG1 = 0
|
|
RSMU_BASE__INST2_SEG2 = 0
|
|
RSMU_BASE__INST2_SEG3 = 0
|
|
RSMU_BASE__INST2_SEG4 = 0
|
|
RSMU_BASE__INST2_SEG5 = 0
|
|
RSMU_BASE__INST3_SEG0 = 0
|
|
RSMU_BASE__INST3_SEG1 = 0
|
|
RSMU_BASE__INST3_SEG2 = 0
|
|
RSMU_BASE__INST3_SEG3 = 0
|
|
RSMU_BASE__INST3_SEG4 = 0
|
|
RSMU_BASE__INST3_SEG5 = 0
|
|
RSMU_BASE__INST4_SEG0 = 0
|
|
RSMU_BASE__INST4_SEG1 = 0
|
|
RSMU_BASE__INST4_SEG2 = 0
|
|
RSMU_BASE__INST4_SEG3 = 0
|
|
RSMU_BASE__INST4_SEG4 = 0
|
|
RSMU_BASE__INST4_SEG5 = 0
|
|
RSMU_BASE__INST5_SEG0 = 0
|
|
RSMU_BASE__INST5_SEG1 = 0
|
|
RSMU_BASE__INST5_SEG2 = 0
|
|
RSMU_BASE__INST5_SEG3 = 0
|
|
RSMU_BASE__INST5_SEG4 = 0
|
|
RSMU_BASE__INST5_SEG5 = 0 |