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IQ.Lvbs history cleanup
2026-08-22 23:42:41 -05:00
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artifacts/package_sources/tinygrad/extra/nv_gpu_driver/clc6c0qmd.h Normal file
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/*******************************************************************************
Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved.
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
to deal in the Software without restriction, including without limitation
the rights to use, copy, modify, merge, publish, distribute, sublicense,
and/or sell copies of the Software, and to permit persons to whom the
Software is furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
DEALINGS IN THE SOFTWARE.
*******************************************************************************/
/* AUTO GENERATED FILE -- DO NOT EDIT */
#ifndef __CLC6C0QMD_H__
#define __CLC6C0QMD_H__
/*
** Queue Meta Data, Version 02_03
*/
// The below C preprocessor definitions describe "multi-word" structures, where
// fields may have bit numbers beyond 32. For example, MW(127:96) means
// the field is in bits 0-31 of word number 3 of the structure. The "MW(X:Y)"
// syntax is to distinguish from similar "X:Y" single-word definitions: the
// macros historically used for single-word definitions would fail with
// multi-word definitions.
//
// See nvmisc.h:DRF_VAL_MW() in the source code of the kernel
// interface layer of nvidia.ko for an example of how to manipulate
// these MW(X:Y) definitions.
#define NVC6C0_QMDV02_03_OUTER_PUT MW(30:0)
#define NVC6C0_QMDV02_03_OUTER_OVERFLOW MW(31:31)
#define NVC6C0_QMDV02_03_OUTER_GET MW(62:32)
#define NVC6C0_QMDV02_03_OUTER_STICKY_OVERFLOW MW(63:63)
#define NVC6C0_QMDV02_03_INNER_GET MW(94:64)
#define NVC6C0_QMDV02_03_INNER_OVERFLOW MW(95:95)
#define NVC6C0_QMDV02_03_INNER_PUT MW(126:96)
#define NVC6C0_QMDV02_03_INNER_STICKY_OVERFLOW MW(127:127)
#define NVC6C0_QMDV02_03_QMD_GROUP_ID MW(133:128)
#define NVC6C0_QMDV02_03_SM_GLOBAL_CACHING_ENABLE MW(134:134)
#define NVC6C0_QMDV02_03_RUN_CTA_IN_ONE_SM_PARTITION MW(135:135)
#define NVC6C0_QMDV02_03_RUN_CTA_IN_ONE_SM_PARTITION_FALSE 0x00000000
#define NVC6C0_QMDV02_03_RUN_CTA_IN_ONE_SM_PARTITION_TRUE 0x00000001
#define NVC6C0_QMDV02_03_IS_QUEUE MW(136:136)
#define NVC6C0_QMDV02_03_IS_QUEUE_FALSE 0x00000000
#define NVC6C0_QMDV02_03_IS_QUEUE_TRUE 0x00000001
#define NVC6C0_QMDV02_03_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST MW(137:137)
#define NVC6C0_QMDV02_03_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_FALSE 0x00000000
#define NVC6C0_QMDV02_03_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_TRUE 0x00000001
#define NVC6C0_QMDV02_03_SEMAPHORE_RELEASE_ENABLE0 MW(138:138)
#define NVC6C0_QMDV02_03_SEMAPHORE_RELEASE_ENABLE0_FALSE 0x00000000
#define NVC6C0_QMDV02_03_SEMAPHORE_RELEASE_ENABLE0_TRUE 0x00000001
#define NVC6C0_QMDV02_03_SEMAPHORE_RELEASE_ENABLE1 MW(139:139)
#define NVC6C0_QMDV02_03_SEMAPHORE_RELEASE_ENABLE1_FALSE 0x00000000
#define NVC6C0_QMDV02_03_SEMAPHORE_RELEASE_ENABLE1_TRUE 0x00000001
#define NVC6C0_QMDV02_03_REQUIRE_SCHEDULING_PCAS MW(140:140)
#define NVC6C0_QMDV02_03_REQUIRE_SCHEDULING_PCAS_FALSE 0x00000000
#define NVC6C0_QMDV02_03_REQUIRE_SCHEDULING_PCAS_TRUE 0x00000001
#define NVC6C0_QMDV02_03_DEPENDENT_QMD_SCHEDULE_ENABLE MW(141:141)
#define NVC6C0_QMDV02_03_DEPENDENT_QMD_SCHEDULE_ENABLE_FALSE 0x00000000
#define NVC6C0_QMDV02_03_DEPENDENT_QMD_SCHEDULE_ENABLE_TRUE 0x00000001
#define NVC6C0_QMDV02_03_DEPENDENT_QMD_TYPE MW(142:142)
#define NVC6C0_QMDV02_03_DEPENDENT_QMD_TYPE_QUEUE 0x00000000
#define NVC6C0_QMDV02_03_DEPENDENT_QMD_TYPE_GRID 0x00000001
#define NVC6C0_QMDV02_03_DEPENDENT_QMD_FIELD_COPY MW(143:143)
#define NVC6C0_QMDV02_03_DEPENDENT_QMD_FIELD_COPY_FALSE 0x00000000
#define NVC6C0_QMDV02_03_DEPENDENT_QMD_FIELD_COPY_TRUE 0x00000001
#define NVC6C0_QMDV02_03_QMD_RESERVED_B MW(159:144)
#define NVC6C0_QMDV02_03_CIRCULAR_QUEUE_SIZE MW(184:160)
#define NVC6C0_QMDV02_03_QMD_RESERVED_C MW(185:185)
#define NVC6C0_QMDV02_03_INVALIDATE_TEXTURE_HEADER_CACHE MW(186:186)
#define NVC6C0_QMDV02_03_INVALIDATE_TEXTURE_HEADER_CACHE_FALSE 0x00000000
#define NVC6C0_QMDV02_03_INVALIDATE_TEXTURE_HEADER_CACHE_TRUE 0x00000001
#define NVC6C0_QMDV02_03_INVALIDATE_TEXTURE_SAMPLER_CACHE MW(187:187)
#define NVC6C0_QMDV02_03_INVALIDATE_TEXTURE_SAMPLER_CACHE_FALSE 0x00000000
#define NVC6C0_QMDV02_03_INVALIDATE_TEXTURE_SAMPLER_CACHE_TRUE 0x00000001
#define NVC6C0_QMDV02_03_INVALIDATE_TEXTURE_DATA_CACHE MW(188:188)
#define NVC6C0_QMDV02_03_INVALIDATE_TEXTURE_DATA_CACHE_FALSE 0x00000000
#define NVC6C0_QMDV02_03_INVALIDATE_TEXTURE_DATA_CACHE_TRUE 0x00000001
#define NVC6C0_QMDV02_03_INVALIDATE_SHADER_DATA_CACHE MW(189:189)
#define NVC6C0_QMDV02_03_INVALIDATE_SHADER_DATA_CACHE_FALSE 0x00000000
#define NVC6C0_QMDV02_03_INVALIDATE_SHADER_DATA_CACHE_TRUE 0x00000001
#define NVC6C0_QMDV02_03_INVALIDATE_INSTRUCTION_CACHE MW(190:190)
#define NVC6C0_QMDV02_03_INVALIDATE_INSTRUCTION_CACHE_FALSE 0x00000000
#define NVC6C0_QMDV02_03_INVALIDATE_INSTRUCTION_CACHE_TRUE 0x00000001
#define NVC6C0_QMDV02_03_INVALIDATE_SHADER_CONSTANT_CACHE MW(191:191)
#define NVC6C0_QMDV02_03_INVALIDATE_SHADER_CONSTANT_CACHE_FALSE 0x00000000
#define NVC6C0_QMDV02_03_INVALIDATE_SHADER_CONSTANT_CACHE_TRUE 0x00000001
#define NVC6C0_QMDV02_03_CTA_RASTER_WIDTH_RESUME MW(223:192)
#define NVC6C0_QMDV02_03_CTA_RASTER_HEIGHT_RESUME MW(239:224)
#define NVC6C0_QMDV02_03_CTA_RASTER_DEPTH_RESUME MW(255:240)
#define NVC6C0_QMDV02_03_PROGRAM_PREFETCH_ADDR_LOWER_SHIFTED MW(287:256)
#define NVC6C0_QMDV02_03_CIRCULAR_QUEUE_ADDR_LOWER MW(319:288)
#define NVC6C0_QMDV02_03_CIRCULAR_QUEUE_ADDR_UPPER MW(327:320)
#define NVC6C0_QMDV02_03_QMD_RESERVED_D MW(335:328)
#define NVC6C0_QMDV02_03_CIRCULAR_QUEUE_ENTRY_SIZE MW(351:336)
#define NVC6C0_QMDV02_03_CWD_REFERENCE_COUNT_ID MW(357:352)
#define NVC6C0_QMDV02_03_CWD_REFERENCE_COUNT_DELTA_MINUS_ONE MW(365:358)
#define NVC6C0_QMDV02_03_RELEASE_MEMBAR_TYPE MW(366:366)
#define NVC6C0_QMDV02_03_RELEASE_MEMBAR_TYPE_FE_NONE 0x00000000
#define NVC6C0_QMDV02_03_RELEASE_MEMBAR_TYPE_FE_SYSMEMBAR 0x00000001
#define NVC6C0_QMDV02_03_CWD_REFERENCE_COUNT_INCR_ENABLE MW(367:367)
#define NVC6C0_QMDV02_03_CWD_REFERENCE_COUNT_INCR_ENABLE_FALSE 0x00000000
#define NVC6C0_QMDV02_03_CWD_REFERENCE_COUNT_INCR_ENABLE_TRUE 0x00000001
#define NVC6C0_QMDV02_03_CWD_MEMBAR_TYPE MW(369:368)
#define NVC6C0_QMDV02_03_CWD_MEMBAR_TYPE_L1_NONE 0x00000000
#define NVC6C0_QMDV02_03_CWD_MEMBAR_TYPE_L1_SYSMEMBAR 0x00000001
#define NVC6C0_QMDV02_03_CWD_MEMBAR_TYPE_L1_MEMBAR 0x00000003
#define NVC6C0_QMDV02_03_SEQUENTIALLY_RUN_CTAS MW(370:370)
#define NVC6C0_QMDV02_03_SEQUENTIALLY_RUN_CTAS_FALSE 0x00000000
#define NVC6C0_QMDV02_03_SEQUENTIALLY_RUN_CTAS_TRUE 0x00000001
#define NVC6C0_QMDV02_03_CWD_REFERENCE_COUNT_DECR_ENABLE MW(371:371)
#define NVC6C0_QMDV02_03_CWD_REFERENCE_COUNT_DECR_ENABLE_FALSE 0x00000000
#define NVC6C0_QMDV02_03_CWD_REFERENCE_COUNT_DECR_ENABLE_TRUE 0x00000001
#define NVC6C0_QMDV02_03_API_VISIBLE_CALL_LIMIT MW(378:378)
#define NVC6C0_QMDV02_03_API_VISIBLE_CALL_LIMIT__32 0x00000000
#define NVC6C0_QMDV02_03_API_VISIBLE_CALL_LIMIT_NO_CHECK 0x00000001
#define NVC6C0_QMDV02_03_SAMPLER_INDEX MW(382:382)
#define NVC6C0_QMDV02_03_SAMPLER_INDEX_INDEPENDENTLY 0x00000000
#define NVC6C0_QMDV02_03_SAMPLER_INDEX_VIA_HEADER_INDEX 0x00000001
#define NVC6C0_QMDV02_03_CTA_RASTER_WIDTH MW(415:384)
#define NVC6C0_QMDV02_03_CTA_RASTER_HEIGHT MW(431:416)
#define NVC6C0_QMDV02_03_QMD_RESERVED13A MW(447:432)
#define NVC6C0_QMDV02_03_CTA_RASTER_DEPTH MW(463:448)
#define NVC6C0_QMDV02_03_QMD_RESERVED14A MW(479:464)
#define NVC6C0_QMDV02_03_DEPENDENT_QMD_POINTER MW(511:480)
#define NVC6C0_QMDV02_03_COALESCE_WAITING_PERIOD MW(529:522)
#define NVC6C0_QMDV02_03_QUEUE_ENTRIES_PER_CTA_LOG2 MW(534:530)
#define NVC6C0_QMDV02_03_SHARED_MEMORY_SIZE MW(561:544)
#define NVC6C0_QMDV02_03_MIN_SM_CONFIG_SHARED_MEM_SIZE MW(568:562)
#define NVC6C0_QMDV02_03_MAX_SM_CONFIG_SHARED_MEM_SIZE MW(575:569)
#define NVC6C0_QMDV02_03_QMD_VERSION MW(579:576)
#define NVC6C0_QMDV02_03_QMD_MAJOR_VERSION MW(583:580)
#define NVC6C0_QMDV02_03_QMD_RESERVED_H MW(591:584)
#define NVC6C0_QMDV02_03_CTA_THREAD_DIMENSION0 MW(607:592)
#define NVC6C0_QMDV02_03_CTA_THREAD_DIMENSION1 MW(623:608)
#define NVC6C0_QMDV02_03_CTA_THREAD_DIMENSION2 MW(639:624)
#define NVC6C0_QMDV02_03_CONSTANT_BUFFER_VALID(i) MW((640+(i)*1):(640+(i)*1))
#define NVC6C0_QMDV02_03_CONSTANT_BUFFER_VALID_FALSE 0x00000000
#define NVC6C0_QMDV02_03_CONSTANT_BUFFER_VALID_TRUE 0x00000001
#define NVC6C0_QMDV02_03_REGISTER_COUNT_V MW(656:648)
#define NVC6C0_QMDV02_03_TARGET_SM_CONFIG_SHARED_MEM_SIZE MW(663:657)
#define NVC6C0_QMDV02_03_FREE_CTA_SLOTS_EMPTY_SM MW(671:664)
#define NVC6C0_QMDV02_03_SM_DISABLE_MASK_LOWER MW(703:672)
#define NVC6C0_QMDV02_03_SM_DISABLE_MASK_UPPER MW(735:704)
#define NVC6C0_QMDV02_03_RELEASE0_ADDRESS_LOWER MW(767:736)
#define NVC6C0_QMDV02_03_RELEASE0_ADDRESS_UPPER MW(775:768)
#define NVC6C0_QMDV02_03_QMD_RESERVED_J MW(783:776)
#define NVC6C0_QMDV02_03_RELEASE0_REDUCTION_OP MW(790:788)
#define NVC6C0_QMDV02_03_RELEASE0_REDUCTION_OP_RED_ADD 0x00000000
#define NVC6C0_QMDV02_03_RELEASE0_REDUCTION_OP_RED_MIN 0x00000001
#define NVC6C0_QMDV02_03_RELEASE0_REDUCTION_OP_RED_MAX 0x00000002
#define NVC6C0_QMDV02_03_RELEASE0_REDUCTION_OP_RED_INC 0x00000003
#define NVC6C0_QMDV02_03_RELEASE0_REDUCTION_OP_RED_DEC 0x00000004
#define NVC6C0_QMDV02_03_RELEASE0_REDUCTION_OP_RED_AND 0x00000005
#define NVC6C0_QMDV02_03_RELEASE0_REDUCTION_OP_RED_OR 0x00000006
#define NVC6C0_QMDV02_03_RELEASE0_REDUCTION_OP_RED_XOR 0x00000007
#define NVC6C0_QMDV02_03_QMD_RESERVED_K MW(791:791)
#define NVC6C0_QMDV02_03_RELEASE0_REDUCTION_FORMAT MW(793:792)
#define NVC6C0_QMDV02_03_RELEASE0_REDUCTION_FORMAT_UNSIGNED_32 0x00000000
#define NVC6C0_QMDV02_03_RELEASE0_REDUCTION_FORMAT_SIGNED_32 0x00000001
#define NVC6C0_QMDV02_03_RELEASE0_REDUCTION_ENABLE MW(794:794)
#define NVC6C0_QMDV02_03_RELEASE0_REDUCTION_ENABLE_FALSE 0x00000000
#define NVC6C0_QMDV02_03_RELEASE0_REDUCTION_ENABLE_TRUE 0x00000001
#define NVC6C0_QMDV02_03_RELEASE0_STRUCTURE_SIZE MW(799:799)
#define NVC6C0_QMDV02_03_RELEASE0_STRUCTURE_SIZE_FOUR_WORDS 0x00000000
#define NVC6C0_QMDV02_03_RELEASE0_STRUCTURE_SIZE_ONE_WORD 0x00000001
#define NVC6C0_QMDV02_03_RELEASE0_PAYLOAD MW(831:800)
#define NVC6C0_QMDV02_03_RELEASE1_ADDRESS_LOWER MW(863:832)
#define NVC6C0_QMDV02_03_RELEASE1_ADDRESS_UPPER MW(871:864)
#define NVC6C0_QMDV02_03_QMD_RESERVED_L MW(879:872)
#define NVC6C0_QMDV02_03_RELEASE1_REDUCTION_OP MW(886:884)
#define NVC6C0_QMDV02_03_RELEASE1_REDUCTION_OP_RED_ADD 0x00000000
#define NVC6C0_QMDV02_03_RELEASE1_REDUCTION_OP_RED_MIN 0x00000001
#define NVC6C0_QMDV02_03_RELEASE1_REDUCTION_OP_RED_MAX 0x00000002
#define NVC6C0_QMDV02_03_RELEASE1_REDUCTION_OP_RED_INC 0x00000003
#define NVC6C0_QMDV02_03_RELEASE1_REDUCTION_OP_RED_DEC 0x00000004
#define NVC6C0_QMDV02_03_RELEASE1_REDUCTION_OP_RED_AND 0x00000005
#define NVC6C0_QMDV02_03_RELEASE1_REDUCTION_OP_RED_OR 0x00000006
#define NVC6C0_QMDV02_03_RELEASE1_REDUCTION_OP_RED_XOR 0x00000007
#define NVC6C0_QMDV02_03_QMD_RESERVED_M MW(887:887)
#define NVC6C0_QMDV02_03_RELEASE1_REDUCTION_FORMAT MW(889:888)
#define NVC6C0_QMDV02_03_RELEASE1_REDUCTION_FORMAT_UNSIGNED_32 0x00000000
#define NVC6C0_QMDV02_03_RELEASE1_REDUCTION_FORMAT_SIGNED_32 0x00000001
#define NVC6C0_QMDV02_03_RELEASE1_REDUCTION_ENABLE MW(890:890)
#define NVC6C0_QMDV02_03_RELEASE1_REDUCTION_ENABLE_FALSE 0x00000000
#define NVC6C0_QMDV02_03_RELEASE1_REDUCTION_ENABLE_TRUE 0x00000001
#define NVC6C0_QMDV02_03_RELEASE1_STRUCTURE_SIZE MW(895:895)
#define NVC6C0_QMDV02_03_RELEASE1_STRUCTURE_SIZE_FOUR_WORDS 0x00000000
#define NVC6C0_QMDV02_03_RELEASE1_STRUCTURE_SIZE_ONE_WORD 0x00000001
#define NVC6C0_QMDV02_03_RELEASE1_PAYLOAD MW(927:896)
#define NVC6C0_QMDV02_03_SHADER_LOCAL_MEMORY_LOW_SIZE MW(951:928)
#define NVC6C0_QMDV02_03_QMD_RESERVED_N MW(954:952)
#define NVC6C0_QMDV02_03_BARRIER_COUNT MW(959:955)
#define NVC6C0_QMDV02_03_SHADER_LOCAL_MEMORY_HIGH_SIZE MW(983:960)
#define NVC6C0_QMDV02_03_REGISTER_COUNT MW(991:984)
#define NVC6C0_QMDV02_03_PROGRAM_PREFETCH_ADDR_UPPER_SHIFTED MW(1000:992)
#define NVC6C0_QMDV02_03_PROGRAM_PREFETCH_SIZE MW(1009:1001)
#define NVC6C0_QMDV02_03_QMD_RESERVED_A MW(1015:1010)
#define NVC6C0_QMDV02_03_SASS_VERSION MW(1023:1016)
#define NVC6C0_QMDV02_03_CONSTANT_BUFFER_ADDR_LOWER(i) MW((1055+(i)*64):(1024+(i)*64))
#define NVC6C0_QMDV02_03_CONSTANT_BUFFER_ADDR_UPPER(i) MW((1072+(i)*64):(1056+(i)*64))
#define NVC6C0_QMDV02_03_CONSTANT_BUFFER_PREFETCH_POST(i) MW((1073+(i)*64):(1073+(i)*64))
#define NVC6C0_QMDV02_03_CONSTANT_BUFFER_PREFETCH_POST_FALSE 0x00000000
#define NVC6C0_QMDV02_03_CONSTANT_BUFFER_PREFETCH_POST_TRUE 0x00000001
#define NVC6C0_QMDV02_03_CONSTANT_BUFFER_INVALIDATE(i) MW((1074+(i)*64):(1074+(i)*64))
#define NVC6C0_QMDV02_03_CONSTANT_BUFFER_INVALIDATE_FALSE 0x00000000
#define NVC6C0_QMDV02_03_CONSTANT_BUFFER_INVALIDATE_TRUE 0x00000001
#define NVC6C0_QMDV02_03_CONSTANT_BUFFER_SIZE_SHIFTED4(i) MW((1087+(i)*64):(1075+(i)*64))
#define NVC6C0_QMDV02_03_PROGRAM_ADDRESS_LOWER MW(1567:1536)
#define NVC6C0_QMDV02_03_PROGRAM_ADDRESS_UPPER MW(1584:1568)
#define NVC6C0_QMDV02_03_QMD_RESERVED_S MW(1599:1585)
#define NVC6C0_QMDV02_03_HW_ONLY_INNER_GET MW(1630:1600)
#define NVC6C0_QMDV02_03_HW_ONLY_REQUIRE_SCHEDULING_PCAS MW(1631:1631)
#define NVC6C0_QMDV02_03_HW_ONLY_INNER_PUT MW(1662:1632)
#define NVC6C0_QMDV02_03_HW_ONLY_SCG_TYPE MW(1663:1663)
#define NVC6C0_QMDV02_03_HW_ONLY_SPAN_LIST_HEAD_INDEX MW(1693:1664)
#define NVC6C0_QMDV02_03_QMD_RESERVED_Q MW(1694:1694)
#define NVC6C0_QMDV02_03_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID MW(1695:1695)
#define NVC6C0_QMDV02_03_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_FALSE 0x00000000
#define NVC6C0_QMDV02_03_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_TRUE 0x00000001
#define NVC6C0_QMDV02_03_HW_ONLY_SKED_NEXT_QMD_POINTER MW(1727:1696)
#define NVC6C0_QMDV02_03_QMD_SPARE_G MW(1759:1728)
#define NVC6C0_QMDV02_03_QMD_SPARE_H MW(1791:1760)
#define NVC6C0_QMDV02_03_QMD_SPARE_I MW(1823:1792)
#define NVC6C0_QMDV02_03_QMD_SPARE_J MW(1855:1824)
#define NVC6C0_QMDV02_03_QMD_SPARE_K MW(1887:1856)
#define NVC6C0_QMDV02_03_QMD_SPARE_L MW(1919:1888)
#define NVC6C0_QMDV02_03_QMD_SPARE_M MW(1951:1920)
#define NVC6C0_QMDV02_03_QMD_SPARE_N MW(1983:1952)
#define NVC6C0_QMDV02_03_DEBUG_ID_UPPER MW(2015:1984)
#define NVC6C0_QMDV02_03_DEBUG_ID_LOWER MW(2047:2016)
/*
** Queue Meta Data, Version 02_04
*/
#define NVC6C0_QMDV02_04_OUTER_PUT MW(30:0)
#define NVC6C0_QMDV02_04_OUTER_OVERFLOW MW(31:31)
#define NVC6C0_QMDV02_04_OUTER_GET MW(62:32)
#define NVC6C0_QMDV02_04_OUTER_STICKY_OVERFLOW MW(63:63)
#define NVC6C0_QMDV02_04_INNER_GET MW(94:64)
#define NVC6C0_QMDV02_04_INNER_OVERFLOW MW(95:95)
#define NVC6C0_QMDV02_04_INNER_PUT MW(126:96)
#define NVC6C0_QMDV02_04_INNER_STICKY_OVERFLOW MW(127:127)
#define NVC6C0_QMDV02_04_QMD_GROUP_ID MW(133:128)
#define NVC6C0_QMDV02_04_SM_GLOBAL_CACHING_ENABLE MW(134:134)
#define NVC6C0_QMDV02_04_RUN_CTA_IN_ONE_SM_PARTITION MW(135:135)
#define NVC6C0_QMDV02_04_RUN_CTA_IN_ONE_SM_PARTITION_FALSE 0x00000000
#define NVC6C0_QMDV02_04_RUN_CTA_IN_ONE_SM_PARTITION_TRUE 0x00000001
#define NVC6C0_QMDV02_04_IS_QUEUE MW(136:136)
#define NVC6C0_QMDV02_04_IS_QUEUE_FALSE 0x00000000
#define NVC6C0_QMDV02_04_IS_QUEUE_TRUE 0x00000001
#define NVC6C0_QMDV02_04_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST MW(137:137)
#define NVC6C0_QMDV02_04_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_FALSE 0x00000000
#define NVC6C0_QMDV02_04_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_TRUE 0x00000001
#define NVC6C0_QMDV02_04_SEMAPHORE_RELEASE_ENABLE0 MW(138:138)
#define NVC6C0_QMDV02_04_SEMAPHORE_RELEASE_ENABLE0_FALSE 0x00000000
#define NVC6C0_QMDV02_04_SEMAPHORE_RELEASE_ENABLE0_TRUE 0x00000001
#define NVC6C0_QMDV02_04_SEMAPHORE_RELEASE_ENABLE1 MW(139:139)
#define NVC6C0_QMDV02_04_SEMAPHORE_RELEASE_ENABLE1_FALSE 0x00000000
#define NVC6C0_QMDV02_04_SEMAPHORE_RELEASE_ENABLE1_TRUE 0x00000001
#define NVC6C0_QMDV02_04_REQUIRE_SCHEDULING_PCAS MW(140:140)
#define NVC6C0_QMDV02_04_REQUIRE_SCHEDULING_PCAS_FALSE 0x00000000
#define NVC6C0_QMDV02_04_REQUIRE_SCHEDULING_PCAS_TRUE 0x00000001
#define NVC6C0_QMDV02_04_DEPENDENT_QMD0_ENABLE MW(141:141)
#define NVC6C0_QMDV02_04_DEPENDENT_QMD0_ENABLE_FALSE 0x00000000
#define NVC6C0_QMDV02_04_DEPENDENT_QMD0_ENABLE_TRUE 0x00000001
#define NVC6C0_QMDV02_04_DEPENDENT_QMD0_ACTION MW(144:142)
#define NVC6C0_QMDV02_04_DEPENDENT_QMD0_ACTION_QMD_INCREMENT_PUT 0x00000000
#define NVC6C0_QMDV02_04_DEPENDENT_QMD0_ACTION_QMD_SCHEDULE 0x00000001
#define NVC6C0_QMDV02_04_DEPENDENT_QMD0_ACTION_QMD_INVALIDATE_COPY_SCHEDULE 0x00000003
#define NVC6C0_QMDV02_04_DEPENDENT_QMD0_ACTION_QMD_DECREMENT_DEPENDENCE 0x00000004
#define NVC6C0_QMDV02_04_DEPENDENT_QMD0_PREFETCH MW(145:145)
#define NVC6C0_QMDV02_04_DEPENDENT_QMD0_PREFETCH_FALSE 0x00000000
#define NVC6C0_QMDV02_04_DEPENDENT_QMD0_PREFETCH_TRUE 0x00000001
#define NVC6C0_QMDV02_04_DEPENDENT_QMD1_ENABLE MW(146:146)
#define NVC6C0_QMDV02_04_DEPENDENT_QMD1_ENABLE_FALSE 0x00000000
#define NVC6C0_QMDV02_04_DEPENDENT_QMD1_ENABLE_TRUE 0x00000001
#define NVC6C0_QMDV02_04_DEPENDENT_QMD1_ACTION MW(149:147)
#define NVC6C0_QMDV02_04_DEPENDENT_QMD1_ACTION_QMD_INCREMENT_PUT 0x00000000
#define NVC6C0_QMDV02_04_DEPENDENT_QMD1_ACTION_QMD_SCHEDULE 0x00000001
#define NVC6C0_QMDV02_04_DEPENDENT_QMD1_ACTION_QMD_INVALIDATE_COPY_SCHEDULE 0x00000003
#define NVC6C0_QMDV02_04_DEPENDENT_QMD1_ACTION_QMD_DECREMENT_DEPENDENCE 0x00000004
#define NVC6C0_QMDV02_04_DEPENDENT_QMD1_PREFETCH MW(150:150)
#define NVC6C0_QMDV02_04_DEPENDENT_QMD1_PREFETCH_FALSE 0x00000000
#define NVC6C0_QMDV02_04_DEPENDENT_QMD1_PREFETCH_TRUE 0x00000001
#define NVC6C0_QMDV02_04_DEPENDENCE_COUNTER MW(157:151)
#define NVC6C0_QMDV02_04_SELF_COPY_ON_COMPLETION MW(158:158)
#define NVC6C0_QMDV02_04_SELF_COPY_ON_COMPLETION_FALSE 0x00000000
#define NVC6C0_QMDV02_04_SELF_COPY_ON_COMPLETION_TRUE 0x00000001
#define NVC6C0_QMDV02_04_QMD_RESERVED_B MW(159:159)
#define NVC6C0_QMDV02_04_CIRCULAR_QUEUE_SIZE MW(184:160)
#define NVC6C0_QMDV02_04_DEMOTE_L2_EVICT_LAST MW(185:185)
#define NVC6C0_QMDV02_04_INVALIDATE_TEXTURE_HEADER_CACHE MW(186:186)
#define NVC6C0_QMDV02_04_INVALIDATE_TEXTURE_HEADER_CACHE_FALSE 0x00000000
#define NVC6C0_QMDV02_04_INVALIDATE_TEXTURE_HEADER_CACHE_TRUE 0x00000001
#define NVC6C0_QMDV02_04_INVALIDATE_TEXTURE_SAMPLER_CACHE MW(187:187)
#define NVC6C0_QMDV02_04_INVALIDATE_TEXTURE_SAMPLER_CACHE_FALSE 0x00000000
#define NVC6C0_QMDV02_04_INVALIDATE_TEXTURE_SAMPLER_CACHE_TRUE 0x00000001
#define NVC6C0_QMDV02_04_INVALIDATE_TEXTURE_DATA_CACHE MW(188:188)
#define NVC6C0_QMDV02_04_INVALIDATE_TEXTURE_DATA_CACHE_FALSE 0x00000000
#define NVC6C0_QMDV02_04_INVALIDATE_TEXTURE_DATA_CACHE_TRUE 0x00000001
#define NVC6C0_QMDV02_04_INVALIDATE_SHADER_DATA_CACHE MW(189:189)
#define NVC6C0_QMDV02_04_INVALIDATE_SHADER_DATA_CACHE_FALSE 0x00000000
#define NVC6C0_QMDV02_04_INVALIDATE_SHADER_DATA_CACHE_TRUE 0x00000001
#define NVC6C0_QMDV02_04_INVALIDATE_INSTRUCTION_CACHE MW(190:190)
#define NVC6C0_QMDV02_04_INVALIDATE_INSTRUCTION_CACHE_FALSE 0x00000000
#define NVC6C0_QMDV02_04_INVALIDATE_INSTRUCTION_CACHE_TRUE 0x00000001
#define NVC6C0_QMDV02_04_INVALIDATE_SHADER_CONSTANT_CACHE MW(191:191)
#define NVC6C0_QMDV02_04_INVALIDATE_SHADER_CONSTANT_CACHE_FALSE 0x00000000
#define NVC6C0_QMDV02_04_INVALIDATE_SHADER_CONSTANT_CACHE_TRUE 0x00000001
#define NVC6C0_QMDV02_04_CTA_RASTER_WIDTH_RESUME MW(223:192)
#define NVC6C0_QMDV02_04_CTA_RASTER_HEIGHT_RESUME MW(239:224)
#define NVC6C0_QMDV02_04_CTA_RASTER_DEPTH_RESUME MW(255:240)
#define NVC6C0_QMDV02_04_PROGRAM_PREFETCH_ADDR_LOWER_SHIFTED MW(287:256)
#define NVC6C0_QMDV02_04_CIRCULAR_QUEUE_ADDR_LOWER MW(319:288)
#define NVC6C0_QMDV02_04_CIRCULAR_QUEUE_ADDR_UPPER MW(327:320)
#define NVC6C0_QMDV02_04_QMD_RESERVED_D MW(335:328)
#define NVC6C0_QMDV02_04_CIRCULAR_QUEUE_ENTRY_SIZE MW(351:336)
#define NVC6C0_QMDV02_04_CWD_REFERENCE_COUNT_ID MW(357:352)
#define NVC6C0_QMDV02_04_CWD_REFERENCE_COUNT_DELTA_MINUS_ONE MW(365:358)
#define NVC6C0_QMDV02_04_RELEASE_MEMBAR_TYPE MW(366:366)
#define NVC6C0_QMDV02_04_RELEASE_MEMBAR_TYPE_FE_NONE 0x00000000
#define NVC6C0_QMDV02_04_RELEASE_MEMBAR_TYPE_FE_SYSMEMBAR 0x00000001
#define NVC6C0_QMDV02_04_CWD_REFERENCE_COUNT_INCR_ENABLE MW(367:367)
#define NVC6C0_QMDV02_04_CWD_REFERENCE_COUNT_INCR_ENABLE_FALSE 0x00000000
#define NVC6C0_QMDV02_04_CWD_REFERENCE_COUNT_INCR_ENABLE_TRUE 0x00000001
#define NVC6C0_QMDV02_04_CWD_MEMBAR_TYPE MW(369:368)
#define NVC6C0_QMDV02_04_CWD_MEMBAR_TYPE_L1_NONE 0x00000000
#define NVC6C0_QMDV02_04_CWD_MEMBAR_TYPE_L1_SYSMEMBAR 0x00000001
#define NVC6C0_QMDV02_04_CWD_MEMBAR_TYPE_L1_MEMBAR 0x00000003
#define NVC6C0_QMDV02_04_SEQUENTIALLY_RUN_CTAS MW(370:370)
#define NVC6C0_QMDV02_04_SEQUENTIALLY_RUN_CTAS_FALSE 0x00000000
#define NVC6C0_QMDV02_04_SEQUENTIALLY_RUN_CTAS_TRUE 0x00000001
#define NVC6C0_QMDV02_04_CWD_REFERENCE_COUNT_DECR_ENABLE MW(371:371)
#define NVC6C0_QMDV02_04_CWD_REFERENCE_COUNT_DECR_ENABLE_FALSE 0x00000000
#define NVC6C0_QMDV02_04_CWD_REFERENCE_COUNT_DECR_ENABLE_TRUE 0x00000001
#define NVC6C0_QMDV02_04_API_VISIBLE_CALL_LIMIT MW(378:378)
#define NVC6C0_QMDV02_04_API_VISIBLE_CALL_LIMIT__32 0x00000000
#define NVC6C0_QMDV02_04_API_VISIBLE_CALL_LIMIT_NO_CHECK 0x00000001
#define NVC6C0_QMDV02_04_SAMPLER_INDEX MW(382:382)
#define NVC6C0_QMDV02_04_SAMPLER_INDEX_INDEPENDENTLY 0x00000000
#define NVC6C0_QMDV02_04_SAMPLER_INDEX_VIA_HEADER_INDEX 0x00000001
#define NVC6C0_QMDV02_04_DISABLE_AUTO_INVALIDATE MW(383:383)
#define NVC6C0_QMDV02_04_DISABLE_AUTO_INVALIDATE_FALSE 0x00000000
#define NVC6C0_QMDV02_04_DISABLE_AUTO_INVALIDATE_TRUE 0x00000001
#define NVC6C0_QMDV02_04_CTA_RASTER_WIDTH MW(415:384)
#define NVC6C0_QMDV02_04_CTA_RASTER_HEIGHT MW(431:416)
#define NVC6C0_QMDV02_04_QMD_RESERVED13A MW(447:432)
#define NVC6C0_QMDV02_04_CTA_RASTER_DEPTH MW(463:448)
#define NVC6C0_QMDV02_04_QMD_RESERVED14A MW(479:464)
#define NVC6C0_QMDV02_04_DEPENDENT_QMD0_POINTER MW(511:480)
#define NVC6C0_QMDV02_04_COALESCE_WAITING_PERIOD MW(529:522)
#define NVC6C0_QMDV02_04_QUEUE_ENTRIES_PER_CTA_LOG2 MW(534:530)
#define NVC6C0_QMDV02_04_SHARED_MEMORY_SIZE MW(561:544)
#define NVC6C0_QMDV02_04_MIN_SM_CONFIG_SHARED_MEM_SIZE MW(568:562)
#define NVC6C0_QMDV02_04_MAX_SM_CONFIG_SHARED_MEM_SIZE MW(575:569)
#define NVC6C0_QMDV02_04_QMD_VERSION MW(579:576)
#define NVC6C0_QMDV02_04_QMD_MAJOR_VERSION MW(583:580)
#define NVC6C0_QMDV02_04_QMD_RESERVED_H MW(591:584)
#define NVC6C0_QMDV02_04_CTA_THREAD_DIMENSION0 MW(607:592)
#define NVC6C0_QMDV02_04_CTA_THREAD_DIMENSION1 MW(623:608)
#define NVC6C0_QMDV02_04_CTA_THREAD_DIMENSION2 MW(639:624)
#define NVC6C0_QMDV02_04_CONSTANT_BUFFER_VALID(i) MW((640+(i)*1):(640+(i)*1))
#define NVC6C0_QMDV02_04_CONSTANT_BUFFER_VALID_FALSE 0x00000000
#define NVC6C0_QMDV02_04_CONSTANT_BUFFER_VALID_TRUE 0x00000001
#define NVC6C0_QMDV02_04_REGISTER_COUNT_V MW(656:648)
#define NVC6C0_QMDV02_04_TARGET_SM_CONFIG_SHARED_MEM_SIZE MW(663:657)
#define NVC6C0_QMDV02_04_FREE_CTA_SLOTS_EMPTY_SM MW(671:664)
#define NVC6C0_QMDV02_04_SM_DISABLE_MASK_LOWER MW(703:672)
#define NVC6C0_QMDV02_04_SM_DISABLE_MASK_UPPER MW(735:704)
#define NVC6C0_QMDV02_04_RELEASE0_ADDRESS_LOWER MW(767:736)
#define NVC6C0_QMDV02_04_RELEASE0_ADDRESS_UPPER MW(775:768)
#define NVC6C0_QMDV02_04_QMD_RESERVED_J MW(783:776)
#define NVC6C0_QMDV02_04_RELEASE0_REDUCTION_OP MW(790:788)
#define NVC6C0_QMDV02_04_RELEASE0_REDUCTION_OP_RED_ADD 0x00000000
#define NVC6C0_QMDV02_04_RELEASE0_REDUCTION_OP_RED_MIN 0x00000001
#define NVC6C0_QMDV02_04_RELEASE0_REDUCTION_OP_RED_MAX 0x00000002
#define NVC6C0_QMDV02_04_RELEASE0_REDUCTION_OP_RED_INC 0x00000003
#define NVC6C0_QMDV02_04_RELEASE0_REDUCTION_OP_RED_DEC 0x00000004
#define NVC6C0_QMDV02_04_RELEASE0_REDUCTION_OP_RED_AND 0x00000005
#define NVC6C0_QMDV02_04_RELEASE0_REDUCTION_OP_RED_OR 0x00000006
#define NVC6C0_QMDV02_04_RELEASE0_REDUCTION_OP_RED_XOR 0x00000007
#define NVC6C0_QMDV02_04_QMD_RESERVED_K MW(791:791)
#define NVC6C0_QMDV02_04_RELEASE0_REDUCTION_FORMAT MW(793:792)
#define NVC6C0_QMDV02_04_RELEASE0_REDUCTION_FORMAT_UNSIGNED_32 0x00000000
#define NVC6C0_QMDV02_04_RELEASE0_REDUCTION_FORMAT_SIGNED_32 0x00000001
#define NVC6C0_QMDV02_04_RELEASE0_REDUCTION_ENABLE MW(794:794)
#define NVC6C0_QMDV02_04_RELEASE0_REDUCTION_ENABLE_FALSE 0x00000000
#define NVC6C0_QMDV02_04_RELEASE0_REDUCTION_ENABLE_TRUE 0x00000001
#define NVC6C0_QMDV02_04_RELEASE0_STRUCTURE_SIZE MW(799:799)
#define NVC6C0_QMDV02_04_RELEASE0_STRUCTURE_SIZE_FOUR_WORDS 0x00000000
#define NVC6C0_QMDV02_04_RELEASE0_STRUCTURE_SIZE_ONE_WORD 0x00000001
#define NVC6C0_QMDV02_04_RELEASE0_PAYLOAD MW(831:800)
#define NVC6C0_QMDV02_04_RELEASE1_ADDRESS_LOWER MW(863:832)
#define NVC6C0_QMDV02_04_RELEASE1_ADDRESS_UPPER MW(871:864)
#define NVC6C0_QMDV02_04_QMD_RESERVED_L MW(879:872)
#define NVC6C0_QMDV02_04_RELEASE1_REDUCTION_OP MW(886:884)
#define NVC6C0_QMDV02_04_RELEASE1_REDUCTION_OP_RED_ADD 0x00000000
#define NVC6C0_QMDV02_04_RELEASE1_REDUCTION_OP_RED_MIN 0x00000001
#define NVC6C0_QMDV02_04_RELEASE1_REDUCTION_OP_RED_MAX 0x00000002
#define NVC6C0_QMDV02_04_RELEASE1_REDUCTION_OP_RED_INC 0x00000003
#define NVC6C0_QMDV02_04_RELEASE1_REDUCTION_OP_RED_DEC 0x00000004
#define NVC6C0_QMDV02_04_RELEASE1_REDUCTION_OP_RED_AND 0x00000005
#define NVC6C0_QMDV02_04_RELEASE1_REDUCTION_OP_RED_OR 0x00000006
#define NVC6C0_QMDV02_04_RELEASE1_REDUCTION_OP_RED_XOR 0x00000007
#define NVC6C0_QMDV02_04_QMD_RESERVED_M MW(887:887)
#define NVC6C0_QMDV02_04_RELEASE1_REDUCTION_FORMAT MW(889:888)
#define NVC6C0_QMDV02_04_RELEASE1_REDUCTION_FORMAT_UNSIGNED_32 0x00000000
#define NVC6C0_QMDV02_04_RELEASE1_REDUCTION_FORMAT_SIGNED_32 0x00000001
#define NVC6C0_QMDV02_04_RELEASE1_REDUCTION_ENABLE MW(890:890)
#define NVC6C0_QMDV02_04_RELEASE1_REDUCTION_ENABLE_FALSE 0x00000000
#define NVC6C0_QMDV02_04_RELEASE1_REDUCTION_ENABLE_TRUE 0x00000001
#define NVC6C0_QMDV02_04_RELEASE1_STRUCTURE_SIZE MW(895:895)
#define NVC6C0_QMDV02_04_RELEASE1_STRUCTURE_SIZE_FOUR_WORDS 0x00000000
#define NVC6C0_QMDV02_04_RELEASE1_STRUCTURE_SIZE_ONE_WORD 0x00000001
#define NVC6C0_QMDV02_04_RELEASE1_PAYLOAD MW(927:896)
#define NVC6C0_QMDV02_04_SHADER_LOCAL_MEMORY_LOW_SIZE MW(951:928)
#define NVC6C0_QMDV02_04_QMD_RESERVED_N MW(954:952)
#define NVC6C0_QMDV02_04_BARRIER_COUNT MW(959:955)
#define NVC6C0_QMDV02_04_SHADER_LOCAL_MEMORY_HIGH_SIZE MW(983:960)
#define NVC6C0_QMDV02_04_QMD_RESERVED_G MW(991:984)
#define NVC6C0_QMDV02_04_PROGRAM_PREFETCH_ADDR_UPPER_SHIFTED MW(1000:992)
#define NVC6C0_QMDV02_04_PROGRAM_PREFETCH_SIZE MW(1009:1001)
#define NVC6C0_QMDV02_04_PROGRAM_PREFETCH_TYPE MW(1011:1010)
#define NVC6C0_QMDV02_04_PROGRAM_PREFETCH_TYPE_PREFETCH_LAUNCH 0x00000000
#define NVC6C0_QMDV02_04_PROGRAM_PREFETCH_TYPE_PREFTECH_POST 0x00000001
#define NVC6C0_QMDV02_04_QMD_RESERVED_A MW(1015:1012)
#define NVC6C0_QMDV02_04_SASS_VERSION MW(1023:1016)
#define NVC6C0_QMDV02_04_CONSTANT_BUFFER_ADDR_LOWER(i) MW((1055+(i)*64):(1024+(i)*64))
#define NVC6C0_QMDV02_04_CONSTANT_BUFFER_ADDR_UPPER(i) MW((1072+(i)*64):(1056+(i)*64))
#define NVC6C0_QMDV02_04_CONSTANT_BUFFER_PREFETCH_POST(i) MW((1073+(i)*64):(1073+(i)*64))
#define NVC6C0_QMDV02_04_CONSTANT_BUFFER_PREFETCH_POST_FALSE 0x00000000
#define NVC6C0_QMDV02_04_CONSTANT_BUFFER_PREFETCH_POST_TRUE 0x00000001
#define NVC6C0_QMDV02_04_CONSTANT_BUFFER_INVALIDATE(i) MW((1074+(i)*64):(1074+(i)*64))
#define NVC6C0_QMDV02_04_CONSTANT_BUFFER_INVALIDATE_FALSE 0x00000000
#define NVC6C0_QMDV02_04_CONSTANT_BUFFER_INVALIDATE_TRUE 0x00000001
#define NVC6C0_QMDV02_04_CONSTANT_BUFFER_SIZE_SHIFTED4(i) MW((1087+(i)*64):(1075+(i)*64))
#define NVC6C0_QMDV02_04_PROGRAM_ADDRESS_LOWER MW(1567:1536)
#define NVC6C0_QMDV02_04_PROGRAM_ADDRESS_UPPER MW(1584:1568)
#define NVC6C0_QMDV02_04_QMD_RESERVED_S MW(1599:1585)
#define NVC6C0_QMDV02_04_HW_ONLY_INNER_GET MW(1630:1600)
#define NVC6C0_QMDV02_04_HW_ONLY_REQUIRE_SCHEDULING_PCAS MW(1631:1631)
#define NVC6C0_QMDV02_04_HW_ONLY_INNER_PUT MW(1662:1632)
#define NVC6C0_QMDV02_04_HW_ONLY_SCG_TYPE MW(1663:1663)
#define NVC6C0_QMDV02_04_HW_ONLY_SPAN_LIST_HEAD_INDEX MW(1693:1664)
#define NVC6C0_QMDV02_04_QMD_RESERVED_Q MW(1694:1694)
#define NVC6C0_QMDV02_04_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID MW(1695:1695)
#define NVC6C0_QMDV02_04_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_FALSE 0x00000000
#define NVC6C0_QMDV02_04_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_TRUE 0x00000001
#define NVC6C0_QMDV02_04_HW_ONLY_SKED_NEXT_QMD_POINTER MW(1727:1696)
#define NVC6C0_QMDV02_04_HW_ONLY_DEPENDENCE_COUNTER MW(1734:1728)
#define NVC6C0_QMDV02_04_QMD_RESERVED_I MW(1759:1735)
#define NVC6C0_QMDV02_04_QMD_SPARE_H MW(1791:1760)
#define NVC6C0_QMDV02_04_QMD_SPARE_I MW(1823:1792)
#define NVC6C0_QMDV02_04_QMD_SPARE_J MW(1855:1824)
#define NVC6C0_QMDV02_04_QMD_SPARE_K MW(1887:1856)
#define NVC6C0_QMDV02_04_QMD_SPARE_L MW(1919:1888)
#define NVC6C0_QMDV02_04_QMD_SPARE_M MW(1951:1920)
#define NVC6C0_QMDV02_04_QMD_SPARE_N MW(1983:1952)
#define NVC6C0_QMDV02_04_DEBUG_ID_UPPER MW(2015:1984)
#define NVC6C0_QMDV02_04_DEBUG_ID_LOWER MW(2047:2016)
/*
** Queue Meta Data, Version 03_00
*/
#define NVC6C0_QMDV03_00_OUTER_PUT MW(30:0)
#define NVC6C0_QMDV03_00_OUTER_OVERFLOW MW(31:31)
#define NVC6C0_QMDV03_00_OUTER_GET MW(62:32)
#define NVC6C0_QMDV03_00_OUTER_STICKY_OVERFLOW MW(63:63)
#define NVC6C0_QMDV03_00_INNER_GET MW(94:64)
#define NVC6C0_QMDV03_00_INNER_OVERFLOW MW(95:95)
#define NVC6C0_QMDV03_00_INNER_PUT MW(126:96)
#define NVC6C0_QMDV03_00_INNER_STICKY_OVERFLOW MW(127:127)
#define NVC6C0_QMDV03_00_QMD_GROUP_ID MW(133:128)
#define NVC6C0_QMDV03_00_SM_GLOBAL_CACHING_ENABLE MW(134:134)
#define NVC6C0_QMDV03_00_RUN_CTA_IN_ONE_SM_PARTITION MW(135:135)
#define NVC6C0_QMDV03_00_RUN_CTA_IN_ONE_SM_PARTITION_FALSE 0x00000000
#define NVC6C0_QMDV03_00_RUN_CTA_IN_ONE_SM_PARTITION_TRUE 0x00000001
#define NVC6C0_QMDV03_00_IS_QUEUE MW(136:136)
#define NVC6C0_QMDV03_00_IS_QUEUE_FALSE 0x00000000
#define NVC6C0_QMDV03_00_IS_QUEUE_TRUE 0x00000001
#define NVC6C0_QMDV03_00_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST MW(137:137)
#define NVC6C0_QMDV03_00_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_FALSE 0x00000000
#define NVC6C0_QMDV03_00_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_TRUE 0x00000001
#define NVC6C0_QMDV03_00_QMD_RESERVED04A MW(139:138)
#define NVC6C0_QMDV03_00_REQUIRE_SCHEDULING_PCAS MW(140:140)
#define NVC6C0_QMDV03_00_REQUIRE_SCHEDULING_PCAS_FALSE 0x00000000
#define NVC6C0_QMDV03_00_REQUIRE_SCHEDULING_PCAS_TRUE 0x00000001
#define NVC6C0_QMDV03_00_QMD_RESERVED04B MW(141:141)
#define NVC6C0_QMDV03_00_DEPENDENCE_COUNTER MW(157:142)
#define NVC6C0_QMDV03_00_SELF_COPY_ON_COMPLETION MW(158:158)
#define NVC6C0_QMDV03_00_SELF_COPY_ON_COMPLETION_FALSE 0x00000000
#define NVC6C0_QMDV03_00_SELF_COPY_ON_COMPLETION_TRUE 0x00000001
#define NVC6C0_QMDV03_00_QMD_RESERVED04C MW(159:159)
#define NVC6C0_QMDV03_00_CIRCULAR_QUEUE_SIZE MW(184:160)
#define NVC6C0_QMDV03_00_DEMOTE_L2_EVICT_LAST MW(185:185)
#define NVC6C0_QMDV03_00_INVALIDATE_TEXTURE_HEADER_CACHE MW(186:186)
#define NVC6C0_QMDV03_00_INVALIDATE_TEXTURE_HEADER_CACHE_FALSE 0x00000000
#define NVC6C0_QMDV03_00_INVALIDATE_TEXTURE_HEADER_CACHE_TRUE 0x00000001
#define NVC6C0_QMDV03_00_INVALIDATE_TEXTURE_SAMPLER_CACHE MW(187:187)
#define NVC6C0_QMDV03_00_INVALIDATE_TEXTURE_SAMPLER_CACHE_FALSE 0x00000000
#define NVC6C0_QMDV03_00_INVALIDATE_TEXTURE_SAMPLER_CACHE_TRUE 0x00000001
#define NVC6C0_QMDV03_00_INVALIDATE_TEXTURE_DATA_CACHE MW(188:188)
#define NVC6C0_QMDV03_00_INVALIDATE_TEXTURE_DATA_CACHE_FALSE 0x00000000
#define NVC6C0_QMDV03_00_INVALIDATE_TEXTURE_DATA_CACHE_TRUE 0x00000001
#define NVC6C0_QMDV03_00_INVALIDATE_SHADER_DATA_CACHE MW(189:189)
#define NVC6C0_QMDV03_00_INVALIDATE_SHADER_DATA_CACHE_FALSE 0x00000000
#define NVC6C0_QMDV03_00_INVALIDATE_SHADER_DATA_CACHE_TRUE 0x00000001
#define NVC6C0_QMDV03_00_INVALIDATE_INSTRUCTION_CACHE MW(190:190)
#define NVC6C0_QMDV03_00_INVALIDATE_INSTRUCTION_CACHE_FALSE 0x00000000
#define NVC6C0_QMDV03_00_INVALIDATE_INSTRUCTION_CACHE_TRUE 0x00000001
#define NVC6C0_QMDV03_00_INVALIDATE_SHADER_CONSTANT_CACHE MW(191:191)
#define NVC6C0_QMDV03_00_INVALIDATE_SHADER_CONSTANT_CACHE_FALSE 0x00000000
#define NVC6C0_QMDV03_00_INVALIDATE_SHADER_CONSTANT_CACHE_TRUE 0x00000001
#define NVC6C0_QMDV03_00_CTA_RASTER_WIDTH_RESUME MW(223:192)
#define NVC6C0_QMDV03_00_CTA_RASTER_HEIGHT_RESUME MW(239:224)
#define NVC6C0_QMDV03_00_CTA_RASTER_DEPTH_RESUME MW(255:240)
#define NVC6C0_QMDV03_00_PROGRAM_PREFETCH_ADDR_LOWER_SHIFTED MW(287:256)
#define NVC6C0_QMDV03_00_CIRCULAR_QUEUE_ADDR_LOWER MW(319:288)
#define NVC6C0_QMDV03_00_CIRCULAR_QUEUE_ADDR_UPPER MW(327:320)
#define NVC6C0_QMDV03_00_QMD_RESERVED_D MW(335:328)
#define NVC6C0_QMDV03_00_CIRCULAR_QUEUE_ENTRY_SIZE MW(351:336)
#define NVC6C0_QMDV03_00_CWD_REFERENCE_COUNT_ID MW(357:352)
#define NVC6C0_QMDV03_00_CWD_REFERENCE_COUNT_DELTA_MINUS_ONE MW(365:358)
#define NVC6C0_QMDV03_00_QMD_RESERVED11A MW(366:366)
#define NVC6C0_QMDV03_00_CWD_REFERENCE_COUNT_INCR_ENABLE MW(367:367)
#define NVC6C0_QMDV03_00_CWD_REFERENCE_COUNT_INCR_ENABLE_FALSE 0x00000000
#define NVC6C0_QMDV03_00_CWD_REFERENCE_COUNT_INCR_ENABLE_TRUE 0x00000001
#define NVC6C0_QMDV03_00_CWD_MEMBAR_TYPE MW(369:368)
#define NVC6C0_QMDV03_00_CWD_MEMBAR_TYPE_L1_NONE 0x00000000
#define NVC6C0_QMDV03_00_CWD_MEMBAR_TYPE_L1_SYSMEMBAR 0x00000001
#define NVC6C0_QMDV03_00_CWD_MEMBAR_TYPE_L1_MEMBAR 0x00000003
#define NVC6C0_QMDV03_00_SEQUENTIALLY_RUN_CTAS MW(370:370)
#define NVC6C0_QMDV03_00_SEQUENTIALLY_RUN_CTAS_FALSE 0x00000000
#define NVC6C0_QMDV03_00_SEQUENTIALLY_RUN_CTAS_TRUE 0x00000001
#define NVC6C0_QMDV03_00_CWD_REFERENCE_COUNT_DECR_ENABLE MW(371:371)
#define NVC6C0_QMDV03_00_CWD_REFERENCE_COUNT_DECR_ENABLE_FALSE 0x00000000
#define NVC6C0_QMDV03_00_CWD_REFERENCE_COUNT_DECR_ENABLE_TRUE 0x00000001
#define NVC6C0_QMDV03_00_QMD_RESERVED11B MW(377:372)
#define NVC6C0_QMDV03_00_API_VISIBLE_CALL_LIMIT MW(378:378)
#define NVC6C0_QMDV03_00_API_VISIBLE_CALL_LIMIT__32 0x00000000
#define NVC6C0_QMDV03_00_API_VISIBLE_CALL_LIMIT_NO_CHECK 0x00000001
#define NVC6C0_QMDV03_00_QMD_RESERVED11C MW(381:379)
#define NVC6C0_QMDV03_00_SAMPLER_INDEX MW(382:382)
#define NVC6C0_QMDV03_00_SAMPLER_INDEX_INDEPENDENTLY 0x00000000
#define NVC6C0_QMDV03_00_SAMPLER_INDEX_VIA_HEADER_INDEX 0x00000001
#define NVC6C0_QMDV03_00_DISABLE_AUTO_INVALIDATE MW(383:383)
#define NVC6C0_QMDV03_00_DISABLE_AUTO_INVALIDATE_FALSE 0x00000000
#define NVC6C0_QMDV03_00_DISABLE_AUTO_INVALIDATE_TRUE 0x00000001
#define NVC6C0_QMDV03_00_CTA_RASTER_WIDTH MW(415:384)
#define NVC6C0_QMDV03_00_CTA_RASTER_HEIGHT MW(431:416)
#define NVC6C0_QMDV03_00_CTA_RASTER_DEPTH MW(463:448)
#define NVC6C0_QMDV03_00_DEPENDENT_QMD0_POINTER MW(511:480)
#define NVC6C0_QMDV03_00_DEPENDENT_QMD0_ENABLE MW(512:512)
#define NVC6C0_QMDV03_00_DEPENDENT_QMD0_ENABLE_FALSE 0x00000000
#define NVC6C0_QMDV03_00_DEPENDENT_QMD0_ENABLE_TRUE 0x00000001
#define NVC6C0_QMDV03_00_DEPENDENT_QMD0_ACTION MW(515:513)
#define NVC6C0_QMDV03_00_DEPENDENT_QMD0_ACTION_QMD_INCREMENT_PUT 0x00000000
#define NVC6C0_QMDV03_00_DEPENDENT_QMD0_ACTION_QMD_SCHEDULE 0x00000001
#define NVC6C0_QMDV03_00_DEPENDENT_QMD0_ACTION_QMD_INVALIDATE_COPY_SCHEDULE 0x00000003
#define NVC6C0_QMDV03_00_DEPENDENT_QMD0_ACTION_QMD_DECREMENT_DEPENDENCE 0x00000004
#define NVC6C0_QMDV03_00_DEPENDENT_QMD0_PREFETCH MW(516:516)
#define NVC6C0_QMDV03_00_DEPENDENT_QMD0_PREFETCH_FALSE 0x00000000
#define NVC6C0_QMDV03_00_DEPENDENT_QMD0_PREFETCH_TRUE 0x00000001
#define NVC6C0_QMDV03_00_DEPENDENT_QMD1_ENABLE MW(517:517)
#define NVC6C0_QMDV03_00_DEPENDENT_QMD1_ENABLE_FALSE 0x00000000
#define NVC6C0_QMDV03_00_DEPENDENT_QMD1_ENABLE_TRUE 0x00000001
#define NVC6C0_QMDV03_00_DEPENDENT_QMD1_ACTION MW(520:518)
#define NVC6C0_QMDV03_00_DEPENDENT_QMD1_ACTION_QMD_INCREMENT_PUT 0x00000000
#define NVC6C0_QMDV03_00_DEPENDENT_QMD1_ACTION_QMD_SCHEDULE 0x00000001
#define NVC6C0_QMDV03_00_DEPENDENT_QMD1_ACTION_QMD_INVALIDATE_COPY_SCHEDULE 0x00000003
#define NVC6C0_QMDV03_00_DEPENDENT_QMD1_ACTION_QMD_DECREMENT_DEPENDENCE 0x00000004
#define NVC6C0_QMDV03_00_DEPENDENT_QMD1_PREFETCH MW(521:521)
#define NVC6C0_QMDV03_00_DEPENDENT_QMD1_PREFETCH_FALSE 0x00000000
#define NVC6C0_QMDV03_00_DEPENDENT_QMD1_PREFETCH_TRUE 0x00000001
#define NVC6C0_QMDV03_00_COALESCE_WAITING_PERIOD MW(529:522)
#define NVC6C0_QMDV03_00_QUEUE_ENTRIES_PER_CTA_LOG2 MW(534:530)
#define NVC6C0_QMDV03_00_SHARED_MEMORY_SIZE MW(561:544)
#define NVC6C0_QMDV03_00_MIN_SM_CONFIG_SHARED_MEM_SIZE MW(567:562)
#define NVC6C0_QMDV03_00_QMD_RESERVED17A MW(568:568)
#define NVC6C0_QMDV03_00_MAX_SM_CONFIG_SHARED_MEM_SIZE MW(574:569)
#define NVC6C0_QMDV03_00_QMD_RESERVED17B MW(575:575)
#define NVC6C0_QMDV03_00_QMD_VERSION MW(579:576)
#define NVC6C0_QMDV03_00_QMD_MAJOR_VERSION MW(583:580)
#define NVC6C0_QMDV03_00_CTA_THREAD_DIMENSION0 MW(607:592)
#define NVC6C0_QMDV03_00_CTA_THREAD_DIMENSION1 MW(623:608)
#define NVC6C0_QMDV03_00_CTA_THREAD_DIMENSION2 MW(639:624)
#define NVC6C0_QMDV03_00_CONSTANT_BUFFER_VALID(i) MW((640+(i)*1):(640+(i)*1))
#define NVC6C0_QMDV03_00_CONSTANT_BUFFER_VALID_FALSE 0x00000000
#define NVC6C0_QMDV03_00_CONSTANT_BUFFER_VALID_TRUE 0x00000001
#define NVC6C0_QMDV03_00_REGISTER_COUNT_V MW(656:648)
#define NVC6C0_QMDV03_00_TARGET_SM_CONFIG_SHARED_MEM_SIZE MW(662:657)
#define NVC6C0_QMDV03_00_SHARED_ALLOCATION_ENABLE MW(663:663)
#define NVC6C0_QMDV03_00_SHARED_ALLOCATION_ENABLE_FALSE 0x00000000
#define NVC6C0_QMDV03_00_SHARED_ALLOCATION_ENABLE_TRUE 0x00000001
#define NVC6C0_QMDV03_00_FREE_CTA_SLOTS_EMPTY_SM MW(671:664)
#define NVC6C0_QMDV03_00_SM_DISABLE_MASK_LOWER MW(703:672)
#define NVC6C0_QMDV03_00_SM_DISABLE_MASK_UPPER MW(735:704)
#define NVC6C0_QMDV03_00_SHADER_LOCAL_MEMORY_LOW_SIZE MW(759:736)
#define NVC6C0_QMDV03_00_BARRIER_COUNT MW(767:763)
#define NVC6C0_QMDV03_00_RELEASE0_ADDRESS_LOWER MW(799:768)
#define NVC6C0_QMDV03_00_RELEASE0_ADDRESS_UPPER MW(807:800)
#define NVC6C0_QMDV03_00_SEMAPHORE_RESERVED25A MW(818:808)
#define NVC6C0_QMDV03_00_RELEASE0_MEMBAR_TYPE MW(819:819)
#define NVC6C0_QMDV03_00_RELEASE0_MEMBAR_TYPE_FE_NONE 0x00000000
#define NVC6C0_QMDV03_00_RELEASE0_MEMBAR_TYPE_FE_SYSMEMBAR 0x00000001
#define NVC6C0_QMDV03_00_RELEASE0_REDUCTION_OP MW(822:820)
#define NVC6C0_QMDV03_00_RELEASE0_REDUCTION_OP_RED_ADD 0x00000000
#define NVC6C0_QMDV03_00_RELEASE0_REDUCTION_OP_RED_MIN 0x00000001
#define NVC6C0_QMDV03_00_RELEASE0_REDUCTION_OP_RED_MAX 0x00000002
#define NVC6C0_QMDV03_00_RELEASE0_REDUCTION_OP_RED_INC 0x00000003
#define NVC6C0_QMDV03_00_RELEASE0_REDUCTION_OP_RED_DEC 0x00000004
#define NVC6C0_QMDV03_00_RELEASE0_REDUCTION_OP_RED_AND 0x00000005
#define NVC6C0_QMDV03_00_RELEASE0_REDUCTION_OP_RED_OR 0x00000006
#define NVC6C0_QMDV03_00_RELEASE0_REDUCTION_OP_RED_XOR 0x00000007
#define NVC6C0_QMDV03_00_RELEASE0_ENABLE MW(823:823)
#define NVC6C0_QMDV03_00_RELEASE0_ENABLE_FALSE 0x00000000
#define NVC6C0_QMDV03_00_RELEASE0_ENABLE_TRUE 0x00000001
#define NVC6C0_QMDV03_00_RELEASE0_REDUCTION_FORMAT MW(825:824)
#define NVC6C0_QMDV03_00_RELEASE0_REDUCTION_FORMAT_UNSIGNED_32 0x00000000
#define NVC6C0_QMDV03_00_RELEASE0_REDUCTION_FORMAT_SIGNED_32 0x00000001
#define NVC6C0_QMDV03_00_RELEASE0_REDUCTION_ENABLE MW(826:826)
#define NVC6C0_QMDV03_00_RELEASE0_REDUCTION_ENABLE_FALSE 0x00000000
#define NVC6C0_QMDV03_00_RELEASE0_REDUCTION_ENABLE_TRUE 0x00000001
#define NVC6C0_QMDV03_00_RELEASE0_NON_BLOCKING_INTR_TYPE MW(828:827)
#define NVC6C0_QMDV03_00_RELEASE0_NON_BLOCKING_INTR_TYPE_NONE 0x00000000
#define NVC6C0_QMDV03_00_RELEASE0_NON_BLOCKING_INTR_TYPE_TRAP 0x00000001
#define NVC6C0_QMDV03_00_RELEASE0_NON_BLOCKING_INTR_TYPE_CONDITIONAL_TRAP 0x00000002
#define NVC6C0_QMDV03_00_RELEASE0_PAYLOAD64B MW(829:829)
#define NVC6C0_QMDV03_00_RELEASE0_PAYLOAD64B_FALSE 0x00000000
#define NVC6C0_QMDV03_00_RELEASE0_PAYLOAD64B_TRUE 0x00000001
#define NVC6C0_QMDV03_00_RELEASE0_STRUCTURE_SIZE MW(831:830)
#define NVC6C0_QMDV03_00_RELEASE0_STRUCTURE_SIZE_SEMAPHORE_FOUR_WORDS 0x00000000
#define NVC6C0_QMDV03_00_RELEASE0_STRUCTURE_SIZE_SEMAPHORE_ONE_WORD 0x00000001
#define NVC6C0_QMDV03_00_RELEASE0_STRUCTURE_SIZE_SEMAPHORE_TWO_WORDS 0x00000002
#define NVC6C0_QMDV03_00_RELEASE0_PAYLOAD_LOWER MW(863:832)
#define NVC6C0_QMDV03_00_RELEASE0_PAYLOAD_UPPER MW(895:864)
#define NVC6C0_QMDV03_00_RELEASE1_ADDRESS_LOWER MW(927:896)
#define NVC6C0_QMDV03_00_RELEASE1_ADDRESS_UPPER MW(935:928)
#define NVC6C0_QMDV03_00_SEMAPHORE_RESERVED29A MW(946:936)
#define NVC6C0_QMDV03_00_RELEASE1_MEMBAR_TYPE MW(947:947)
#define NVC6C0_QMDV03_00_RELEASE1_MEMBAR_TYPE_FE_NONE 0x00000000
#define NVC6C0_QMDV03_00_RELEASE1_MEMBAR_TYPE_FE_SYSMEMBAR 0x00000001
#define NVC6C0_QMDV03_00_RELEASE1_REDUCTION_OP MW(950:948)
#define NVC6C0_QMDV03_00_RELEASE1_REDUCTION_OP_RED_ADD 0x00000000
#define NVC6C0_QMDV03_00_RELEASE1_REDUCTION_OP_RED_MIN 0x00000001
#define NVC6C0_QMDV03_00_RELEASE1_REDUCTION_OP_RED_MAX 0x00000002
#define NVC6C0_QMDV03_00_RELEASE1_REDUCTION_OP_RED_INC 0x00000003
#define NVC6C0_QMDV03_00_RELEASE1_REDUCTION_OP_RED_DEC 0x00000004
#define NVC6C0_QMDV03_00_RELEASE1_REDUCTION_OP_RED_AND 0x00000005
#define NVC6C0_QMDV03_00_RELEASE1_REDUCTION_OP_RED_OR 0x00000006
#define NVC6C0_QMDV03_00_RELEASE1_REDUCTION_OP_RED_XOR 0x00000007
#define NVC6C0_QMDV03_00_RELEASE1_ENABLE MW(951:951)
#define NVC6C0_QMDV03_00_RELEASE1_ENABLE_FALSE 0x00000000
#define NVC6C0_QMDV03_00_RELEASE1_ENABLE_TRUE 0x00000001
#define NVC6C0_QMDV03_00_RELEASE1_REDUCTION_FORMAT MW(953:952)
#define NVC6C0_QMDV03_00_RELEASE1_REDUCTION_FORMAT_UNSIGNED_32 0x00000000
#define NVC6C0_QMDV03_00_RELEASE1_REDUCTION_FORMAT_SIGNED_32 0x00000001
#define NVC6C0_QMDV03_00_RELEASE1_REDUCTION_ENABLE MW(954:954)
#define NVC6C0_QMDV03_00_RELEASE1_REDUCTION_ENABLE_FALSE 0x00000000
#define NVC6C0_QMDV03_00_RELEASE1_REDUCTION_ENABLE_TRUE 0x00000001
#define NVC6C0_QMDV03_00_RELEASE1_NON_BLOCKING_INTR_TYPE MW(956:955)
#define NVC6C0_QMDV03_00_RELEASE1_NON_BLOCKING_INTR_TYPE_NONE 0x00000000
#define NVC6C0_QMDV03_00_RELEASE1_NON_BLOCKING_INTR_TYPE_TRAP 0x00000001
#define NVC6C0_QMDV03_00_RELEASE1_NON_BLOCKING_INTR_TYPE_CONDITIONAL_TRAP 0x00000002
#define NVC6C0_QMDV03_00_RELEASE1_PAYLOAD64B MW(957:957)
#define NVC6C0_QMDV03_00_RELEASE1_PAYLOAD64B_FALSE 0x00000000
#define NVC6C0_QMDV03_00_RELEASE1_PAYLOAD64B_TRUE 0x00000001
#define NVC6C0_QMDV03_00_RELEASE1_STRUCTURE_SIZE MW(959:958)
#define NVC6C0_QMDV03_00_RELEASE1_STRUCTURE_SIZE_SEMAPHORE_FOUR_WORDS 0x00000000
#define NVC6C0_QMDV03_00_RELEASE1_STRUCTURE_SIZE_SEMAPHORE_ONE_WORD 0x00000001
#define NVC6C0_QMDV03_00_RELEASE1_STRUCTURE_SIZE_SEMAPHORE_TWO_WORDS 0x00000002
#define NVC6C0_QMDV03_00_RELEASE1_PAYLOAD_LOWER MW(991:960)
#define NVC6C0_QMDV03_00_RELEASE1_PAYLOAD_UPPER MW(1023:992)
#define NVC6C0_QMDV03_00_CONSTANT_BUFFER_ADDR_LOWER(i) MW((1055+(i)*64):(1024+(i)*64))
#define NVC6C0_QMDV03_00_CONSTANT_BUFFER_ADDR_UPPER(i) MW((1072+(i)*64):(1056+(i)*64))
#define NVC6C0_QMDV03_00_CONSTANT_BUFFER_PREFETCH_POST(i) MW((1073+(i)*64):(1073+(i)*64))
#define NVC6C0_QMDV03_00_CONSTANT_BUFFER_PREFETCH_POST_FALSE 0x00000000
#define NVC6C0_QMDV03_00_CONSTANT_BUFFER_PREFETCH_POST_TRUE 0x00000001
#define NVC6C0_QMDV03_00_CONSTANT_BUFFER_INVALIDATE(i) MW((1074+(i)*64):(1074+(i)*64))
#define NVC6C0_QMDV03_00_CONSTANT_BUFFER_INVALIDATE_FALSE 0x00000000
#define NVC6C0_QMDV03_00_CONSTANT_BUFFER_INVALIDATE_TRUE 0x00000001
#define NVC6C0_QMDV03_00_CONSTANT_BUFFER_SIZE_SHIFTED4(i) MW((1087+(i)*64):(1075+(i)*64))
#define NVC6C0_QMDV03_00_PROGRAM_ADDRESS_LOWER MW(1567:1536)
#define NVC6C0_QMDV03_00_PROGRAM_ADDRESS_UPPER MW(1584:1568)
#define NVC6C0_QMDV03_00_SHADER_LOCAL_MEMORY_HIGH_SIZE MW(1623:1600)
#define NVC6C0_QMDV03_00_PROGRAM_PREFETCH_ADDR_UPPER_SHIFTED MW(1640:1632)
#define NVC6C0_QMDV03_00_PROGRAM_PREFETCH_SIZE MW(1649:1641)
#define NVC6C0_QMDV03_00_PROGRAM_PREFETCH_TYPE MW(1651:1650)
#define NVC6C0_QMDV03_00_PROGRAM_PREFETCH_TYPE_PREFETCH_LAUNCH 0x00000000
#define NVC6C0_QMDV03_00_PROGRAM_PREFETCH_TYPE_PREFTECH_POST 0x00000001
#define NVC6C0_QMDV03_00_SASS_VERSION MW(1663:1656)
#define NVC6C0_QMDV03_00_RELEASE2_ADDRESS_LOWER MW(1695:1664)
#define NVC6C0_QMDV03_00_RELEASE2_ADDRESS_UPPER MW(1703:1696)
#define NVC6C0_QMDV03_00_SEMAPHORE_RESERVED53A MW(1714:1704)
#define NVC6C0_QMDV03_00_RELEASE2_MEMBAR_TYPE MW(1715:1715)
#define NVC6C0_QMDV03_00_RELEASE2_MEMBAR_TYPE_FE_NONE 0x00000000
#define NVC6C0_QMDV03_00_RELEASE2_MEMBAR_TYPE_FE_SYSMEMBAR 0x00000001
#define NVC6C0_QMDV03_00_RELEASE2_REDUCTION_OP MW(1718:1716)
#define NVC6C0_QMDV03_00_RELEASE2_REDUCTION_OP_RED_ADD 0x00000000
#define NVC6C0_QMDV03_00_RELEASE2_REDUCTION_OP_RED_MIN 0x00000001
#define NVC6C0_QMDV03_00_RELEASE2_REDUCTION_OP_RED_MAX 0x00000002
#define NVC6C0_QMDV03_00_RELEASE2_REDUCTION_OP_RED_INC 0x00000003
#define NVC6C0_QMDV03_00_RELEASE2_REDUCTION_OP_RED_DEC 0x00000004
#define NVC6C0_QMDV03_00_RELEASE2_REDUCTION_OP_RED_AND 0x00000005
#define NVC6C0_QMDV03_00_RELEASE2_REDUCTION_OP_RED_OR 0x00000006
#define NVC6C0_QMDV03_00_RELEASE2_REDUCTION_OP_RED_XOR 0x00000007
#define NVC6C0_QMDV03_00_RELEASE2_ENABLE MW(1719:1719)
#define NVC6C0_QMDV03_00_RELEASE2_ENABLE_FALSE 0x00000000
#define NVC6C0_QMDV03_00_RELEASE2_ENABLE_TRUE 0x00000001
#define NVC6C0_QMDV03_00_RELEASE2_REDUCTION_FORMAT MW(1721:1720)
#define NVC6C0_QMDV03_00_RELEASE2_REDUCTION_FORMAT_UNSIGNED_32 0x00000000
#define NVC6C0_QMDV03_00_RELEASE2_REDUCTION_FORMAT_SIGNED_32 0x00000001
#define NVC6C0_QMDV03_00_RELEASE2_REDUCTION_ENABLE MW(1722:1722)
#define NVC6C0_QMDV03_00_RELEASE2_REDUCTION_ENABLE_FALSE 0x00000000
#define NVC6C0_QMDV03_00_RELEASE2_REDUCTION_ENABLE_TRUE 0x00000001
#define NVC6C0_QMDV03_00_RELEASE2_NON_BLOCKING_INTR_TYPE MW(1724:1723)
#define NVC6C0_QMDV03_00_RELEASE2_NON_BLOCKING_INTR_TYPE_NONE 0x00000000
#define NVC6C0_QMDV03_00_RELEASE2_NON_BLOCKING_INTR_TYPE_TRAP 0x00000001
#define NVC6C0_QMDV03_00_RELEASE2_NON_BLOCKING_INTR_TYPE_CONDITIONAL_TRAP 0x00000002
#define NVC6C0_QMDV03_00_RELEASE2_PAYLOAD64B MW(1725:1725)
#define NVC6C0_QMDV03_00_RELEASE2_PAYLOAD64B_FALSE 0x00000000
#define NVC6C0_QMDV03_00_RELEASE2_PAYLOAD64B_TRUE 0x00000001
#define NVC6C0_QMDV03_00_RELEASE2_STRUCTURE_SIZE MW(1727:1726)
#define NVC6C0_QMDV03_00_RELEASE2_STRUCTURE_SIZE_SEMAPHORE_FOUR_WORDS 0x00000000
#define NVC6C0_QMDV03_00_RELEASE2_STRUCTURE_SIZE_SEMAPHORE_ONE_WORD 0x00000001
#define NVC6C0_QMDV03_00_RELEASE2_STRUCTURE_SIZE_SEMAPHORE_TWO_WORDS 0x00000002
#define NVC6C0_QMDV03_00_RELEASE2_PAYLOAD_LOWER MW(1759:1728)
#define NVC6C0_QMDV03_00_RELEASE2_PAYLOAD_UPPER MW(1791:1760)
#define NVC6C0_QMDV03_00_QMD_SPARE_I MW(1823:1792)
#define NVC6C0_QMDV03_00_HW_ONLY_INNER_GET MW(1854:1824)
#define NVC6C0_QMDV03_00_HW_ONLY_REQUIRE_SCHEDULING_PCAS MW(1855:1855)
#define NVC6C0_QMDV03_00_HW_ONLY_INNER_PUT MW(1886:1856)
#define NVC6C0_QMDV03_00_HW_ONLY_SPAN_LIST_HEAD_INDEX MW(1917:1888)
#define NVC6C0_QMDV03_00_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID MW(1919:1919)
#define NVC6C0_QMDV03_00_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_FALSE 0x00000000
#define NVC6C0_QMDV03_00_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_TRUE 0x00000001
#define NVC6C0_QMDV03_00_HW_ONLY_SKED_NEXT_QMD_POINTER MW(1951:1920)
#define NVC6C0_QMDV03_00_HW_ONLY_DEPENDENCE_COUNTER MW(1958:1952)
#define NVC6C0_QMDV03_00_DEBUG_ID_UPPER MW(2015:1984)
#define NVC6C0_QMDV03_00_DEBUG_ID_LOWER MW(2047:2016)
#endif // #ifndef __CLC6C0QMD_H__

603
artifacts/package_sources/tinygrad/extra/nv_gpu_driver/clc9b0.h Normal file
View File

@@ -0,0 +1,603 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef clc9b0_h_
#define clc9b0_h_
#include "nvtypes.h"
#ifdef __cplusplus
extern "C" {
#endif
#define NVC9B0_VIDEO_DECODER (0x0000C9B0)
#define NVC9B0_NOP (0x00000100)
#define NVC9B0_NOP_PARAMETER 31:0
#define NVC9B0_PM_TRIGGER (0x00000140)
#define NVC9B0_PM_TRIGGER_V 31:0
#define NVC9B0_SET_APPLICATION_ID (0x00000200)
#define NVC9B0_SET_APPLICATION_ID_ID 31:0
#define NVC9B0_SET_APPLICATION_ID_ID_MPEG12 (0x00000001)
#define NVC9B0_SET_APPLICATION_ID_ID_VC1 (0x00000002)
#define NVC9B0_SET_APPLICATION_ID_ID_H264 (0x00000003)
#define NVC9B0_SET_APPLICATION_ID_ID_MPEG4 (0x00000004)
#define NVC9B0_SET_APPLICATION_ID_ID_VP8 (0x00000005)
#define NVC9B0_SET_APPLICATION_ID_ID_CTR64 (0x00000006)
#define NVC9B0_SET_APPLICATION_ID_ID_HEVC (0x00000007)
#define NVC9B0_SET_APPLICATION_ID_ID_NEW_H264 (0x00000008)
#define NVC9B0_SET_APPLICATION_ID_ID_VP9 (0x00000009)
#define NVC9B0_SET_APPLICATION_ID_ID_PASS1 (0x0000000A)
#define NVC9B0_SET_APPLICATION_ID_ID_HEVC_PARSER (0x0000000C)
#define NVC9B0_SET_APPLICATION_ID_ID_UCODE_TEST (0x0000000D)
#define NVC9B0_SET_APPLICATION_ID_ID_HWDRM_PR_DECRYPTAUDIO (0x0000000E)
#define NVC9B0_SET_APPLICATION_ID_ID_HWDRM_PR_DECRYPTAUDIOMULTIPLE (0x0000000F)
#define NVC9B0_SET_APPLICATION_ID_ID_HWDRM_PR_PREPROCESSENCRYPTEDDATA (0x00000010)
#define NVC9B0_SET_APPLICATION_ID_ID_VP9_WITH_PARSER (0x00000011)
#define NVC9B0_SET_APPLICATION_ID_ID_AVD (0x00000012)
#define NVC9B0_SET_APPLICATION_ID_ID_HW_DRM_PR4_DECRYPTCONTENTMULTIPLE (0x00000013)
#define NVC9B0_SET_APPLICATION_ID_ID_DHKE (0x00000020)
#define NVC9B0_SET_WATCHDOG_TIMER (0x00000204)
#define NVC9B0_SET_WATCHDOG_TIMER_TIMER 31:0
#define NVC9B0_SEMAPHORE_A (0x00000240)
#define NVC9B0_SEMAPHORE_A_UPPER 7:0
#define NVC9B0_SEMAPHORE_B (0x00000244)
#define NVC9B0_SEMAPHORE_B_LOWER 31:0
#define NVC9B0_SEMAPHORE_C (0x00000248)
#define NVC9B0_SEMAPHORE_C_PAYLOAD 31:0
#define NVC9B0_CTX_SAVE_AREA (0x0000024C)
#define NVC9B0_CTX_SAVE_AREA_OFFSET 31:0
#define NVC9B0_CTX_SWITCH (0x00000250)
#define NVC9B0_CTX_SWITCH_OP 1:0
#define NVC9B0_CTX_SWITCH_OP_CTX_UPDATE (0x00000000)
#define NVC9B0_CTX_SWITCH_OP_CTX_SAVE (0x00000001)
#define NVC9B0_CTX_SWITCH_OP_CTX_RESTORE (0x00000002)
#define NVC9B0_CTX_SWITCH_OP_CTX_FORCERESTORE (0x00000003)
#define NVC9B0_CTX_SWITCH_CTXID_VALID 2:2
#define NVC9B0_CTX_SWITCH_CTXID_VALID_FALSE (0x00000000)
#define NVC9B0_CTX_SWITCH_CTXID_VALID_TRUE (0x00000001)
#define NVC9B0_CTX_SWITCH_RESERVED0 7:3
#define NVC9B0_CTX_SWITCH_CTX_ID 23:8
#define NVC9B0_CTX_SWITCH_RESERVED1 31:24
#define NVC9B0_SET_SEMAPHORE_PAYLOAD_LOWER (0x00000254)
#define NVC9B0_SET_SEMAPHORE_PAYLOAD_LOWER_PAYLOAD_LOWER 31:0
#define NVC9B0_SET_SEMAPHORE_PAYLOAD_UPPER (0x00000258)
#define NVC9B0_SET_SEMAPHORE_PAYLOAD_UPPER_PAYLOAD_UPPER 31:0
#define NVC9B0_SET_MONITORED_FENCE_SIGNAL_ADDRESS_BASE_A (0x0000025C)
#define NVC9B0_SET_MONITORED_FENCE_SIGNAL_ADDRESS_BASE_A_LOWER 31:0
#define NVC9B0_SET_MONITORED_FENCE_SIGNAL_ADDRESS_BASE_B (0x00000260)
#define NVC9B0_SET_MONITORED_FENCE_SIGNAL_ADDRESS_BASE_B_UPPER 31:0
#define NVC9B0_EXECUTE (0x00000300)
#define NVC9B0_EXECUTE_NOTIFY 0:0
#define NVC9B0_EXECUTE_NOTIFY_DISABLE (0x00000000)
#define NVC9B0_EXECUTE_NOTIFY_ENABLE (0x00000001)
#define NVC9B0_EXECUTE_NOTIFY_ON 1:1
#define NVC9B0_EXECUTE_NOTIFY_ON_END (0x00000000)
#define NVC9B0_EXECUTE_NOTIFY_ON_BEGIN (0x00000001)
#define NVC9B0_EXECUTE_PREDICATION 2:2
#define NVC9B0_EXECUTE_PREDICATION_DISABLE (0x00000000)
#define NVC9B0_EXECUTE_PREDICATION_ENABLE (0x00000001)
#define NVC9B0_EXECUTE_PREDICATION_OP 3:3
#define NVC9B0_EXECUTE_PREDICATION_OP_EQUAL_ZERO (0x00000000)
#define NVC9B0_EXECUTE_PREDICATION_OP_NOT_EQUAL_ZERO (0x00000001)
#define NVC9B0_EXECUTE_AWAKEN 8:8
#define NVC9B0_EXECUTE_AWAKEN_DISABLE (0x00000000)
#define NVC9B0_EXECUTE_AWAKEN_ENABLE (0x00000001)
#define NVC9B0_SEMAPHORE_D (0x00000304)
#define NVC9B0_SEMAPHORE_D_STRUCTURE_SIZE 1:0
#define NVC9B0_SEMAPHORE_D_STRUCTURE_SIZE_ONE (0x00000000)
#define NVC9B0_SEMAPHORE_D_STRUCTURE_SIZE_FOUR (0x00000001)
#define NVC9B0_SEMAPHORE_D_STRUCTURE_SIZE_TWO (0x00000002)
#define NVC9B0_SEMAPHORE_D_AWAKEN_ENABLE 8:8
#define NVC9B0_SEMAPHORE_D_AWAKEN_ENABLE_FALSE (0x00000000)
#define NVC9B0_SEMAPHORE_D_AWAKEN_ENABLE_TRUE (0x00000001)
#define NVC9B0_SEMAPHORE_D_OPERATION 17:16
#define NVC9B0_SEMAPHORE_D_OPERATION_RELEASE (0x00000000)
#define NVC9B0_SEMAPHORE_D_OPERATION_RESERVED_0 (0x00000001)
#define NVC9B0_SEMAPHORE_D_OPERATION_RESERVED_1 (0x00000002)
#define NVC9B0_SEMAPHORE_D_OPERATION_TRAP (0x00000003)
#define NVC9B0_SEMAPHORE_D_FLUSH_DISABLE 21:21
#define NVC9B0_SEMAPHORE_D_FLUSH_DISABLE_FALSE (0x00000000)
#define NVC9B0_SEMAPHORE_D_FLUSH_DISABLE_TRUE (0x00000001)
#define NVC9B0_SEMAPHORE_D_TRAP_TYPE 23:22
#define NVC9B0_SEMAPHORE_D_TRAP_TYPE_UNCONDITIONAL (0x00000000)
#define NVC9B0_SEMAPHORE_D_TRAP_TYPE_CONDITIONAL (0x00000001)
#define NVC9B0_SEMAPHORE_D_TRAP_TYPE_CONDITIONAL_EXT (0x00000002)
#define NVC9B0_SEMAPHORE_D_PAYLOAD_SIZE 24:24
#define NVC9B0_SEMAPHORE_D_PAYLOAD_SIZE_32BIT (0x00000000)
#define NVC9B0_SEMAPHORE_D_PAYLOAD_SIZE_64BIT (0x00000001)
#define NVC9B0_SET_PREDICATION_OFFSET_UPPER (0x00000308)
#define NVC9B0_SET_PREDICATION_OFFSET_UPPER_OFFSET 7:0
#define NVC9B0_SET_PREDICATION_OFFSET_LOWER (0x0000030C)
#define NVC9B0_SET_PREDICATION_OFFSET_LOWER_OFFSET 31:0
#define NVC9B0_SET_AUXILIARY_DATA_BUFFER (0x00000310)
#define NVC9B0_SET_AUXILIARY_DATA_BUFFER_OFFSET 31:0
#define NVC9B0_SET_CONTROL_PARAMS (0x00000400)
#define NVC9B0_SET_CONTROL_PARAMS_CODEC_TYPE 3:0
#define NVC9B0_SET_CONTROL_PARAMS_CODEC_TYPE_MPEG1 (0x00000000)
#define NVC9B0_SET_CONTROL_PARAMS_CODEC_TYPE_MPEG2 (0x00000001)
#define NVC9B0_SET_CONTROL_PARAMS_CODEC_TYPE_VC1 (0x00000002)
#define NVC9B0_SET_CONTROL_PARAMS_CODEC_TYPE_H264 (0x00000003)
#define NVC9B0_SET_CONTROL_PARAMS_CODEC_TYPE_MPEG4 (0x00000004)
#define NVC9B0_SET_CONTROL_PARAMS_CODEC_TYPE_DIVX3 (0x00000004)
#define NVC9B0_SET_CONTROL_PARAMS_CODEC_TYPE_VP8 (0x00000005)
#define NVC9B0_SET_CONTROL_PARAMS_CODEC_TYPE_HEVC (0x00000007)
#define NVC9B0_SET_CONTROL_PARAMS_CODEC_TYPE_VP9 (0x00000009)
#define NVC9B0_SET_CONTROL_PARAMS_CODEC_TYPE_AV1 (0x0000000A)
#define NVC9B0_SET_CONTROL_PARAMS_GPTIMER_ON 4:4
#define NVC9B0_SET_CONTROL_PARAMS_RET_ERROR 5:5
#define NVC9B0_SET_CONTROL_PARAMS_ERR_CONCEAL_ON 6:6
#define NVC9B0_SET_CONTROL_PARAMS_ERROR_FRM_IDX 12:7
#define NVC9B0_SET_CONTROL_PARAMS_MBTIMER_ON 13:13
#define NVC9B0_SET_CONTROL_PARAMS_EC_INTRA_FRAME_USING_PSLC 14:14
#define NVC9B0_SET_CONTROL_PARAMS_IGNORE_SOME_FIELDS_CRC_CHECK 15:15
#define NVC9B0_SET_CONTROL_PARAMS_EVENT_TRACE_LOGGING_ON 16:16
#define NVC9B0_SET_CONTROL_PARAMS_ALL_INTRA_FRAME 17:17
#define NVC9B0_SET_CONTROL_PARAMS_TESTRUN_ENV 19:18
#define NVC9B0_SET_CONTROL_PARAMS_TESTRUN_ENV_TRACE3D_RUN (0x00000000)
#define NVC9B0_SET_CONTROL_PARAMS_TESTRUN_ENV_PROD_RUN (0x00000001)
#define NVC9B0_SET_CONTROL_PARAMS_HINT_DUMP_EN 20:20
#define NVC9B0_SET_CONTROL_PARAMS_RESERVED 25:21
#define NVC9B0_SET_CONTROL_PARAMS_NVDECSIM_SKIP_SCP 26:26
#define NVC9B0_SET_CONTROL_PARAMS_ENABLE_ENCRYPT 27:27
#define NVC9B0_SET_CONTROL_PARAMS_ENCRYPTMODE 31:28
#define NVC9B0_SET_DRV_PIC_SETUP_OFFSET (0x00000404)
#define NVC9B0_SET_DRV_PIC_SETUP_OFFSET_OFFSET 31:0
#define NVC9B0_SET_IN_BUF_BASE_OFFSET (0x00000408)
#define NVC9B0_SET_IN_BUF_BASE_OFFSET_OFFSET 31:0
#define NVC9B0_SET_PICTURE_INDEX (0x0000040C)
#define NVC9B0_SET_PICTURE_INDEX_INDEX 31:0
#define NVC9B0_SET_SLICE_OFFSETS_BUF_OFFSET (0x00000410)
#define NVC9B0_SET_SLICE_OFFSETS_BUF_OFFSET_OFFSET 31:0
#define NVC9B0_SET_COLOC_DATA_OFFSET (0x00000414)
#define NVC9B0_SET_COLOC_DATA_OFFSET_OFFSET 31:0
#define NVC9B0_SET_HISTORY_OFFSET (0x00000418)
#define NVC9B0_SET_HISTORY_OFFSET_OFFSET 31:0
#define NVC9B0_SET_DISPLAY_BUF_SIZE (0x0000041C)
#define NVC9B0_SET_DISPLAY_BUF_SIZE_SIZE 31:0
#define NVC9B0_SET_HISTOGRAM_OFFSET (0x00000420)
#define NVC9B0_SET_HISTOGRAM_OFFSET_OFFSET 31:0
#define NVC9B0_SET_NVDEC_STATUS_OFFSET (0x00000424)
#define NVC9B0_SET_NVDEC_STATUS_OFFSET_OFFSET 31:0
#define NVC9B0_SET_DISPLAY_BUF_LUMA_OFFSET (0x00000428)
#define NVC9B0_SET_DISPLAY_BUF_LUMA_OFFSET_OFFSET 31:0
#define NVC9B0_SET_DISPLAY_BUF_CHROMA_OFFSET (0x0000042C)
#define NVC9B0_SET_DISPLAY_BUF_CHROMA_OFFSET_OFFSET 31:0
#define NVC9B0_SET_PICTURE_LUMA_OFFSET0 (0x00000430)
#define NVC9B0_SET_PICTURE_LUMA_OFFSET0_OFFSET 31:0
#define NVC9B0_SET_PICTURE_LUMA_OFFSET1 (0x00000434)
#define NVC9B0_SET_PICTURE_LUMA_OFFSET1_OFFSET 31:0
#define NVC9B0_SET_PICTURE_LUMA_OFFSET2 (0x00000438)
#define NVC9B0_SET_PICTURE_LUMA_OFFSET2_OFFSET 31:0
#define NVC9B0_SET_PICTURE_LUMA_OFFSET3 (0x0000043C)
#define NVC9B0_SET_PICTURE_LUMA_OFFSET3_OFFSET 31:0
#define NVC9B0_SET_PICTURE_LUMA_OFFSET4 (0x00000440)
#define NVC9B0_SET_PICTURE_LUMA_OFFSET4_OFFSET 31:0
#define NVC9B0_SET_PICTURE_LUMA_OFFSET5 (0x00000444)
#define NVC9B0_SET_PICTURE_LUMA_OFFSET5_OFFSET 31:0
#define NVC9B0_SET_PICTURE_LUMA_OFFSET6 (0x00000448)
#define NVC9B0_SET_PICTURE_LUMA_OFFSET6_OFFSET 31:0
#define NVC9B0_SET_PICTURE_LUMA_OFFSET7 (0x0000044C)
#define NVC9B0_SET_PICTURE_LUMA_OFFSET7_OFFSET 31:0
#define NVC9B0_SET_PICTURE_LUMA_OFFSET8 (0x00000450)
#define NVC9B0_SET_PICTURE_LUMA_OFFSET8_OFFSET 31:0
#define NVC9B0_SET_PICTURE_LUMA_OFFSET9 (0x00000454)
#define NVC9B0_SET_PICTURE_LUMA_OFFSET9_OFFSET 31:0
#define NVC9B0_SET_PICTURE_LUMA_OFFSET10 (0x00000458)
#define NVC9B0_SET_PICTURE_LUMA_OFFSET10_OFFSET 31:0
#define NVC9B0_SET_PICTURE_LUMA_OFFSET11 (0x0000045C)
#define NVC9B0_SET_PICTURE_LUMA_OFFSET11_OFFSET 31:0
#define NVC9B0_SET_PICTURE_LUMA_OFFSET12 (0x00000460)
#define NVC9B0_SET_PICTURE_LUMA_OFFSET12_OFFSET 31:0
#define NVC9B0_SET_PICTURE_LUMA_OFFSET13 (0x00000464)
#define NVC9B0_SET_PICTURE_LUMA_OFFSET13_OFFSET 31:0
#define NVC9B0_SET_PICTURE_LUMA_OFFSET14 (0x00000468)
#define NVC9B0_SET_PICTURE_LUMA_OFFSET14_OFFSET 31:0
#define NVC9B0_SET_PICTURE_LUMA_OFFSET15 (0x0000046C)
#define NVC9B0_SET_PICTURE_LUMA_OFFSET15_OFFSET 31:0
#define NVC9B0_SET_PICTURE_LUMA_OFFSET16 (0x00000470)
#define NVC9B0_SET_PICTURE_LUMA_OFFSET16_OFFSET 31:0
#define NVC9B0_SET_PICTURE_CHROMA_OFFSET0 (0x00000474)
#define NVC9B0_SET_PICTURE_CHROMA_OFFSET0_OFFSET 31:0
#define NVC9B0_SET_PICTURE_CHROMA_OFFSET1 (0x00000478)
#define NVC9B0_SET_PICTURE_CHROMA_OFFSET1_OFFSET 31:0
#define NVC9B0_SET_PICTURE_CHROMA_OFFSET2 (0x0000047C)
#define NVC9B0_SET_PICTURE_CHROMA_OFFSET2_OFFSET 31:0
#define NVC9B0_SET_PICTURE_CHROMA_OFFSET3 (0x00000480)
#define NVC9B0_SET_PICTURE_CHROMA_OFFSET3_OFFSET 31:0
#define NVC9B0_SET_PICTURE_CHROMA_OFFSET4 (0x00000484)
#define NVC9B0_SET_PICTURE_CHROMA_OFFSET4_OFFSET 31:0
#define NVC9B0_SET_PICTURE_CHROMA_OFFSET5 (0x00000488)
#define NVC9B0_SET_PICTURE_CHROMA_OFFSET5_OFFSET 31:0
#define NVC9B0_SET_PICTURE_CHROMA_OFFSET6 (0x0000048C)
#define NVC9B0_SET_PICTURE_CHROMA_OFFSET6_OFFSET 31:0
#define NVC9B0_SET_PICTURE_CHROMA_OFFSET7 (0x00000490)
#define NVC9B0_SET_PICTURE_CHROMA_OFFSET7_OFFSET 31:0
#define NVC9B0_SET_PICTURE_CHROMA_OFFSET8 (0x00000494)
#define NVC9B0_SET_PICTURE_CHROMA_OFFSET8_OFFSET 31:0
#define NVC9B0_SET_PICTURE_CHROMA_OFFSET9 (0x00000498)
#define NVC9B0_SET_PICTURE_CHROMA_OFFSET9_OFFSET 31:0
#define NVC9B0_SET_PICTURE_CHROMA_OFFSET10 (0x0000049C)
#define NVC9B0_SET_PICTURE_CHROMA_OFFSET10_OFFSET 31:0
#define NVC9B0_SET_PICTURE_CHROMA_OFFSET11 (0x000004A0)
#define NVC9B0_SET_PICTURE_CHROMA_OFFSET11_OFFSET 31:0
#define NVC9B0_SET_PICTURE_CHROMA_OFFSET12 (0x000004A4)
#define NVC9B0_SET_PICTURE_CHROMA_OFFSET12_OFFSET 31:0
#define NVC9B0_SET_PICTURE_CHROMA_OFFSET13 (0x000004A8)
#define NVC9B0_SET_PICTURE_CHROMA_OFFSET13_OFFSET 31:0
#define NVC9B0_SET_PICTURE_CHROMA_OFFSET14 (0x000004AC)
#define NVC9B0_SET_PICTURE_CHROMA_OFFSET14_OFFSET 31:0
#define NVC9B0_SET_PICTURE_CHROMA_OFFSET15 (0x000004B0)
#define NVC9B0_SET_PICTURE_CHROMA_OFFSET15_OFFSET 31:0
#define NVC9B0_SET_PICTURE_CHROMA_OFFSET16 (0x000004B4)
#define NVC9B0_SET_PICTURE_CHROMA_OFFSET16_OFFSET 31:0
#define NVC9B0_SET_PIC_SCRATCH_BUF_OFFSET (0x000004B8)
#define NVC9B0_SET_PIC_SCRATCH_BUF_OFFSET_OFFSET 31:0
#define NVC9B0_SET_EXTERNAL_MVBUFFER_OFFSET (0x000004BC)
#define NVC9B0_SET_EXTERNAL_MVBUFFER_OFFSET_OFFSET 31:0
#define NVC9B0_SET_SUB_SAMPLE_MAP_OFFSET (0x000004C0)
#define NVC9B0_SET_SUB_SAMPLE_MAP_OFFSET_OFFSET 31:0
#define NVC9B0_SET_SUB_SAMPLE_MAP_IV_OFFSET (0x000004C4)
#define NVC9B0_SET_SUB_SAMPLE_MAP_IV_OFFSET_OFFSET 31:0
#define NVC9B0_SET_INTRA_TOP_BUF_OFFSET (0x000004C8)
#define NVC9B0_SET_INTRA_TOP_BUF_OFFSET_OFFSET 31:0
#define NVC9B0_SET_TILE_SIZE_BUF_OFFSET (0x000004CC)
#define NVC9B0_SET_TILE_SIZE_BUF_OFFSET_OFFSET 31:0
#define NVC9B0_SET_FILTER_BUFFER_OFFSET (0x000004D0)
#define NVC9B0_SET_FILTER_BUFFER_OFFSET_OFFSET 31:0
#define NVC9B0_SET_CRC_STRUCT_OFFSET (0x000004D4)
#define NVC9B0_SET_CRC_STRUCT_OFFSET_OFFSET 31:0
#define NVC9B0_SET_PR_SSM_CONTENT_INFO_BUF_OFFSET (0x000004D8)
#define NVC9B0_SET_PR_SSM_CONTENT_INFO_BUF_OFFSET_OFFSET 31:0
#define NVC9B0_H264_SET_MBHIST_BUF_OFFSET (0x00000500)
#define NVC9B0_H264_SET_MBHIST_BUF_OFFSET_OFFSET 31:0
#define NVC9B0_VP8_SET_PROB_DATA_OFFSET (0x00000540)
#define NVC9B0_VP8_SET_PROB_DATA_OFFSET_OFFSET 31:0
#define NVC9B0_VP8_SET_HEADER_PARTITION_BUF_BASE_OFFSET (0x00000544)
#define NVC9B0_VP8_SET_HEADER_PARTITION_BUF_BASE_OFFSET_OFFSET 31:0
#define NVC9B0_HEVC_SET_SCALING_LIST_OFFSET (0x00000580)
#define NVC9B0_HEVC_SET_SCALING_LIST_OFFSET_OFFSET 31:0
#define NVC9B0_HEVC_SET_TILE_SIZES_OFFSET (0x00000584)
#define NVC9B0_HEVC_SET_TILE_SIZES_OFFSET_OFFSET 31:0
#define NVC9B0_HEVC_SET_FILTER_BUFFER_OFFSET (0x00000588)
#define NVC9B0_HEVC_SET_FILTER_BUFFER_OFFSET_OFFSET 31:0
#define NVC9B0_HEVC_SET_SAO_BUFFER_OFFSET (0x0000058C)
#define NVC9B0_HEVC_SET_SAO_BUFFER_OFFSET_OFFSET 31:0
#define NVC9B0_HEVC_SET_SLICE_INFO_BUFFER_OFFSET (0x00000590)
#define NVC9B0_HEVC_SET_SLICE_INFO_BUFFER_OFFSET_OFFSET 31:0
#define NVC9B0_HEVC_SET_SLICE_GROUP_INDEX (0x00000594)
#define NVC9B0_HEVC_SET_SLICE_GROUP_INDEX_OFFSET 31:0
#define NVC9B0_VP9_SET_PROB_TAB_BUF_OFFSET (0x000005C0)
#define NVC9B0_VP9_SET_PROB_TAB_BUF_OFFSET_OFFSET 31:0
#define NVC9B0_VP9_SET_CTX_COUNTER_BUF_OFFSET (0x000005C4)
#define NVC9B0_VP9_SET_CTX_COUNTER_BUF_OFFSET_OFFSET 31:0
#define NVC9B0_VP9_SET_SEGMENT_READ_BUF_OFFSET (0x000005C8)
#define NVC9B0_VP9_SET_SEGMENT_READ_BUF_OFFSET_OFFSET 31:0
#define NVC9B0_VP9_SET_SEGMENT_WRITE_BUF_OFFSET (0x000005CC)
#define NVC9B0_VP9_SET_SEGMENT_WRITE_BUF_OFFSET_OFFSET 31:0
#define NVC9B0_VP9_SET_TILE_SIZE_BUF_OFFSET (0x000005D0)
#define NVC9B0_VP9_SET_TILE_SIZE_BUF_OFFSET_OFFSET 31:0
#define NVC9B0_VP9_SET_COL_MVWRITE_BUF_OFFSET (0x000005D4)
#define NVC9B0_VP9_SET_COL_MVWRITE_BUF_OFFSET_OFFSET 31:0
#define NVC9B0_VP9_SET_COL_MVREAD_BUF_OFFSET (0x000005D8)
#define NVC9B0_VP9_SET_COL_MVREAD_BUF_OFFSET_OFFSET 31:0
#define NVC9B0_VP9_SET_FILTER_BUFFER_OFFSET (0x000005DC)
#define NVC9B0_VP9_SET_FILTER_BUFFER_OFFSET_OFFSET 31:0
#define NVC9B0_VP9_PARSER_SET_PIC_SETUP_OFFSET (0x000005E0)
#define NVC9B0_VP9_PARSER_SET_PIC_SETUP_OFFSET_OFFSET 31:0
#define NVC9B0_VP9_PARSER_SET_PREV_PIC_SETUP_OFFSET (0x000005E4)
#define NVC9B0_VP9_PARSER_SET_PREV_PIC_SETUP_OFFSET_OFFSET 31:0
#define NVC9B0_VP9_PARSER_SET_PROB_TAB_BUF_OFFSET (0x000005E8)
#define NVC9B0_VP9_PARSER_SET_PROB_TAB_BUF_OFFSET_OFFSET 31:0
#define NVC9B0_VP9_SET_HINT_DUMP_BUF_OFFSET (0x000005EC)
#define NVC9B0_VP9_SET_HINT_DUMP_BUF_OFFSET_OFFSET 31:0
#define NVC9B0_PASS1_SET_CLEAR_HEADER_OFFSET (0x00000600)
#define NVC9B0_PASS1_SET_CLEAR_HEADER_OFFSET_OFFSET 31:0
#define NVC9B0_PASS1_SET_RE_ENCRYPT_OFFSET (0x00000604)
#define NVC9B0_PASS1_SET_RE_ENCRYPT_OFFSET_OFFSET 31:0
#define NVC9B0_PASS1_SET_VP8_TOKEN_OFFSET (0x00000608)
#define NVC9B0_PASS1_SET_VP8_TOKEN_OFFSET_OFFSET 31:0
#define NVC9B0_PASS1_SET_INPUT_DATA_OFFSET (0x0000060C)
#define NVC9B0_PASS1_SET_INPUT_DATA_OFFSET_OFFSET 31:0
#define NVC9B0_PASS1_SET_OUTPUT_DATA_SIZE_OFFSET (0x00000610)
#define NVC9B0_PASS1_SET_OUTPUT_DATA_SIZE_OFFSET_OFFSET 31:0
#define NVC9B0_AV1_SET_PROB_TAB_READ_BUF_OFFSET (0x00000640)
#define NVC9B0_AV1_SET_PROB_TAB_READ_BUF_OFFSET_OFFSET 31:0
#define NVC9B0_AV1_SET_PROB_TAB_WRITE_BUF_OFFSET (0x00000644)
#define NVC9B0_AV1_SET_PROB_TAB_WRITE_BUF_OFFSET_OFFSET 31:0
#define NVC9B0_AV1_SET_SEGMENT_READ_BUF_OFFSET (0x00000648)
#define NVC9B0_AV1_SET_SEGMENT_READ_BUF_OFFSET_OFFSET 31:0
#define NVC9B0_AV1_SET_SEGMENT_WRITE_BUF_OFFSET (0x0000064C)
#define NVC9B0_AV1_SET_SEGMENT_WRITE_BUF_OFFSET_OFFSET 31:0
#define NVC9B0_AV1_SET_COL_MV0_READ_BUF_OFFSET (0x00000650)
#define NVC9B0_AV1_SET_COL_MV0_READ_BUF_OFFSET_OFFSET 31:0
#define NVC9B0_AV1_SET_COL_MV1_READ_BUF_OFFSET (0x00000654)
#define NVC9B0_AV1_SET_COL_MV1_READ_BUF_OFFSET_OFFSET 31:0
#define NVC9B0_AV1_SET_COL_MV2_READ_BUF_OFFSET (0x00000658)
#define NVC9B0_AV1_SET_COL_MV2_READ_BUF_OFFSET_OFFSET 31:0
#define NVC9B0_AV1_SET_COL_MVWRITE_BUF_OFFSET (0x0000065C)
#define NVC9B0_AV1_SET_COL_MVWRITE_BUF_OFFSET_OFFSET 31:0
#define NVC9B0_AV1_SET_GLOBAL_MODEL_BUF_OFFSET (0x00000660)
#define NVC9B0_AV1_SET_GLOBAL_MODEL_BUF_OFFSET_OFFSET 31:0
#define NVC9B0_AV1_SET_FILM_GRAIN_BUF_OFFSET (0x00000664)
#define NVC9B0_AV1_SET_FILM_GRAIN_BUF_OFFSET_OFFSET 31:0
#define NVC9B0_AV1_SET_TILE_STREAM_INFO_BUF_OFFSET (0x00000668)
#define NVC9B0_AV1_SET_TILE_STREAM_INFO_BUF_OFFSET_OFFSET 31:0
#define NVC9B0_AV1_SET_SUB_STREAM_ENTRY_BUF_OFFSET (0x0000066C)
#define NVC9B0_AV1_SET_SUB_STREAM_ENTRY_BUF_OFFSET_OFFSET 31:0
#define NVC9B0_AV1_SET_HINT_DUMP_BUF_OFFSET (0x00000670)
#define NVC9B0_AV1_SET_HINT_DUMP_BUF_OFFSET_OFFSET 31:0
#define NVC9B0_H264_SET_SCALING_LIST_OFFSET (0x00000680)
#define NVC9B0_H264_SET_SCALING_LIST_OFFSET_OFFSET 31:0
#define NVC9B0_H264_SET_VLDHIST_BUF_OFFSET (0x00000684)
#define NVC9B0_H264_SET_VLDHIST_BUF_OFFSET_OFFSET 31:0
#define NVC9B0_H264_SET_EDOBOFFSET0 (0x00000688)
#define NVC9B0_H264_SET_EDOBOFFSET0_OFFSET 31:0
#define NVC9B0_H264_SET_EDOBOFFSET1 (0x0000068C)
#define NVC9B0_H264_SET_EDOBOFFSET1_OFFSET 31:0
#define NVC9B0_H264_SET_EDOBOFFSET2 (0x00000690)
#define NVC9B0_H264_SET_EDOBOFFSET2_OFFSET 31:0
#define NVC9B0_H264_SET_EDOBOFFSET3 (0x00000694)
#define NVC9B0_H264_SET_EDOBOFFSET3_OFFSET 31:0
#define NVC9B0_SET_CONTENT_INITIAL_VECTOR(b) (0x00000C00 + (b)*0x00000004)
#define NVC9B0_SET_CONTENT_INITIAL_VECTOR_VALUE 31:0
#define NVC9B0_SET_CTL_COUNT (0x00000C10)
#define NVC9B0_SET_CTL_COUNT_VALUE 31:0
#define NVC9B0_SET_UPPER_SRC (0x00000C14)
#define NVC9B0_SET_UPPER_SRC_OFFSET 7:0
#define NVC9B0_SET_LOWER_SRC (0x00000C18)
#define NVC9B0_SET_LOWER_SRC_OFFSET 31:0
#define NVC9B0_SET_UPPER_DST (0x00000C1C)
#define NVC9B0_SET_UPPER_DST_OFFSET 7:0
#define NVC9B0_SET_LOWER_DST (0x00000C20)
#define NVC9B0_SET_LOWER_DST_OFFSET 31:0
#define NVC9B0_SET_BLOCK_COUNT (0x00000C24)
#define NVC9B0_SET_BLOCK_COUNT_VALUE 31:0
#define NVC9B0_PR_SET_REQUEST_BUF_OFFSET (0x00000D00)
#define NVC9B0_PR_SET_REQUEST_BUF_OFFSET_OFFSET 31:0
#define NVC9B0_PR_SET_REQUEST_BUF_SIZE (0x00000D04)
#define NVC9B0_PR_SET_REQUEST_BUF_SIZE_SIZE 31:0
#define NVC9B0_PR_SET_RESPONSE_BUF_OFFSET (0x00000D08)
#define NVC9B0_PR_SET_RESPONSE_BUF_OFFSET_OFFSET 31:0
#define NVC9B0_PR_SET_RESPONSE_BUF_SIZE (0x00000D0C)
#define NVC9B0_PR_SET_RESPONSE_BUF_SIZE_SIZE 31:0
#define NVC9B0_PR_SET_REQUEST_MESSAGE_BUF_OFFSET (0x00000D10)
#define NVC9B0_PR_SET_REQUEST_MESSAGE_BUF_OFFSET_OFFSET 31:0
#define NVC9B0_PR_SET_RESPONSE_MESSAGE_BUF_OFFSET (0x00000D14)
#define NVC9B0_PR_SET_RESPONSE_MESSAGE_BUF_OFFSET_OFFSET 31:0
#define NVC9B0_PR_SET_LOCAL_DECRYPT_BUF_OFFSET (0x00000D18)
#define NVC9B0_PR_SET_LOCAL_DECRYPT_BUF_OFFSET_OFFSET 31:0
#define NVC9B0_PR_SET_LOCAL_DECRYPT_BUF_SIZE (0x00000D1C)
#define NVC9B0_PR_SET_LOCAL_DECRYPT_BUF_SIZE_SIZE 31:0
#define NVC9B0_PR_SET_CONTENT_DECRYPT_INFO_BUF_OFFSET (0x00000D20)
#define NVC9B0_PR_SET_CONTENT_DECRYPT_INFO_BUF_OFFSET_OFFSET 31:0
#define NVC9B0_PR_SET_REENCRYPTED_BITSTREAM_BUF_OFFSET (0x00000D24)
#define NVC9B0_PR_SET_REENCRYPTED_BITSTREAM_BUF_OFFSET_OFFSET 31:0
#define NVC9B0_DH_KE_SET_CHALLENGE_BUF_OFFSET (0x00000E00)
#define NVC9B0_DH_KE_SET_CHALLENGE_BUF_OFFSET_OFFSET 31:0
#define NVC9B0_DH_KE_SET_RESPONSE_BUF_OFFSET (0x00000E04)
#define NVC9B0_DH_KE_SET_RESPONSE_BUF_OFFSET_OFFSET 31:0
#define NVC9B0_SET_SESSION_KEY(b) (0x00000F00 + (b)*0x00000004)
#define NVC9B0_SET_SESSION_KEY_VALUE 31:0
#define NVC9B0_SET_CONTENT_KEY(b) (0x00000F10 + (b)*0x00000004)
#define NVC9B0_SET_CONTENT_KEY_VALUE 31:0
#define NVC9B0_PM_TRIGGER_END (0x00001114)
#define NVC9B0_PM_TRIGGER_END_V 31:0
#define NVC9B0_ERROR_NONE (0x00000000)
#define NVC9B0_OS_ERROR_EXECUTE_INSUFFICIENT_DATA (0x00000001)
#define NVC9B0_OS_ERROR_SEMAPHORE_INSUFFICIENT_DATA (0x00000002)
#define NVC9B0_OS_ERROR_INVALID_METHOD (0x00000003)
#define NVC9B0_OS_ERROR_INVALID_DMA_PAGE (0x00000004)
#define NVC9B0_OS_ERROR_UNHANDLED_INTERRUPT (0x00000005)
#define NVC9B0_OS_ERROR_EXCEPTION (0x00000006)
#define NVC9B0_OS_ERROR_INVALID_CTXSW_REQUEST (0x00000007)
#define NVC9B0_OS_ERROR_APPLICATION (0x00000008)
#define NVC9B0_OS_ERROR_SW_BREAKPT (0x00000009)
#define NVC9B0_OS_INTERRUPT_EXECUTE_AWAKEN (0x00000100)
#define NVC9B0_OS_INTERRUPT_BACKEND_SEMAPHORE_AWAKEN (0x00000200)
#define NVC9B0_OS_INTERRUPT_CTX_ERROR_FBIF (0x00000300)
#define NVC9B0_OS_INTERRUPT_LIMIT_VIOLATION (0x00000400)
#define NVC9B0_OS_INTERRUPT_LIMIT_AND_FBIF_CTX_ERROR (0x00000500)
#define NVC9B0_OS_INTERRUPT_HALT_ENGINE (0x00000600)
#define NVC9B0_OS_INTERRUPT_TRAP_NONSTALL (0x00000700)
#define NVC9B0_H264_VLD_ERR_SEQ_DATA_INCONSISTENT (0x00004001)
#define NVC9B0_H264_VLD_ERR_PIC_DATA_INCONSISTENT (0x00004002)
#define NVC9B0_H264_VLD_ERR_SLC_DATA_BUF_ADDR_OUT_OF_BOUNDS (0x00004100)
#define NVC9B0_H264_VLD_ERR_BITSTREAM_ERROR (0x00004101)
#define NVC9B0_H264_VLD_ERR_CTX_DMA_ID_CTRL_IN_INVALID (0x000041F8)
#define NVC9B0_H264_VLD_ERR_SLC_HDR_OUT_SIZE_NOT_MULT256 (0x00004200)
#define NVC9B0_H264_VLD_ERR_SLC_DATA_OUT_SIZE_NOT_MULT256 (0x00004201)
#define NVC9B0_H264_VLD_ERR_CTX_DMA_ID_FLOW_CTRL_INVALID (0x00004203)
#define NVC9B0_H264_VLD_ERR_CTX_DMA_ID_SLC_HDR_OUT_INVALID (0x00004204)
#define NVC9B0_H264_VLD_ERR_SLC_HDR_OUT_BUF_TOO_SMALL (0x00004205)
#define NVC9B0_H264_VLD_ERR_SLC_HDR_OUT_BUF_ALREADY_VALID (0x00004206)
#define NVC9B0_H264_VLD_ERR_SLC_DATA_OUT_BUF_TOO_SMALL (0x00004207)
#define NVC9B0_H264_VLD_ERR_DATA_BUF_CNT_TOO_SMALL (0x00004208)
#define NVC9B0_H264_VLD_ERR_BITSTREAM_EMPTY (0x00004209)
#define NVC9B0_H264_VLD_ERR_FRAME_WIDTH_TOO_LARGE (0x0000420A)
#define NVC9B0_H264_VLD_ERR_FRAME_HEIGHT_TOO_LARGE (0x0000420B)
#define NVC9B0_H264_VLD_ERR_HIST_BUF_TOO_SMALL (0x00004300)
#define NVC9B0_VC1_VLD_ERR_PIC_DATA_BUF_ADDR_OUT_OF_BOUND (0x00005100)
#define NVC9B0_VC1_VLD_ERR_BITSTREAM_ERROR (0x00005101)
#define NVC9B0_VC1_VLD_ERR_PIC_HDR_OUT_SIZE_NOT_MULT256 (0x00005200)
#define NVC9B0_VC1_VLD_ERR_PIC_DATA_OUT_SIZE_NOT_MULT256 (0x00005201)
#define NVC9B0_VC1_VLD_ERR_CTX_DMA_ID_CTRL_IN_INVALID (0x00005202)
#define NVC9B0_VC1_VLD_ERR_CTX_DMA_ID_FLOW_CTRL_INVALID (0x00005203)
#define NVC9B0_VC1_VLD_ERR_CTX_DMA_ID_PIC_HDR_OUT_INVALID (0x00005204)
#define NVC9B0_VC1_VLD_ERR_SLC_HDR_OUT_BUF_TOO_SMALL (0x00005205)
#define NVC9B0_VC1_VLD_ERR_PIC_HDR_OUT_BUF_ALREADY_VALID (0x00005206)
#define NVC9B0_VC1_VLD_ERR_PIC_DATA_OUT_BUF_TOO_SMALL (0x00005207)
#define NVC9B0_VC1_VLD_ERR_DATA_INFO_IN_BUF_TOO_SMALL (0x00005208)
#define NVC9B0_VC1_VLD_ERR_BITSTREAM_EMPTY (0x00005209)
#define NVC9B0_VC1_VLD_ERR_FRAME_WIDTH_TOO_LARGE (0x0000520A)
#define NVC9B0_VC1_VLD_ERR_FRAME_HEIGHT_TOO_LARGE (0x0000520B)
#define NVC9B0_VC1_VLD_ERR_PIC_DATA_OUT_BUF_FULL_TIME_OUT (0x00005300)
#define NVC9B0_MPEG12_VLD_ERR_SLC_DATA_BUF_ADDR_OUT_OF_BOUNDS (0x00006100)
#define NVC9B0_MPEG12_VLD_ERR_BITSTREAM_ERROR (0x00006101)
#define NVC9B0_MPEG12_VLD_ERR_SLC_DATA_OUT_SIZE_NOT_MULT256 (0x00006200)
#define NVC9B0_MPEG12_VLD_ERR_CTX_DMA_ID_CTRL_IN_INVALID (0x00006201)
#define NVC9B0_MPEG12_VLD_ERR_CTX_DMA_ID_FLOW_CTRL_INVALID (0x00006202)
#define NVC9B0_MPEG12_VLD_ERR_SLC_DATA_OUT_BUF_TOO_SMALL (0x00006203)
#define NVC9B0_MPEG12_VLD_ERR_DATA_INFO_IN_BUF_TOO_SMALL (0x00006204)
#define NVC9B0_MPEG12_VLD_ERR_BITSTREAM_EMPTY (0x00006205)
#define NVC9B0_MPEG12_VLD_ERR_INVALID_PIC_STRUCTURE (0x00006206)
#define NVC9B0_MPEG12_VLD_ERR_INVALID_PIC_CODING_TYPE (0x00006207)
#define NVC9B0_MPEG12_VLD_ERR_FRAME_WIDTH_TOO_LARGE (0x00006208)
#define NVC9B0_MPEG12_VLD_ERR_FRAME_HEIGHT_TOO_LARGE (0x00006209)
#define NVC9B0_MPEG12_VLD_ERR_SLC_DATA_OUT_BUF_FULL_TIME_OUT (0x00006300)
#define NVC9B0_CMN_VLD_ERR_PDEC_RETURNED_ERROR (0x00007101)
#define NVC9B0_CMN_VLD_ERR_EDOB_FLUSH_TIME_OUT (0x00007102)
#define NVC9B0_CMN_VLD_ERR_EDOB_REWIND_TIME_OUT (0x00007103)
#define NVC9B0_CMN_VLD_ERR_VLD_WD_TIME_OUT (0x00007104)
#define NVC9B0_CMN_VLD_ERR_NUM_SLICES_ZERO (0x00007105)
#define NVC9B0_MPEG4_VLD_ERR_PIC_DATA_BUF_ADDR_OUT_OF_BOUND (0x00008100)
#define NVC9B0_MPEG4_VLD_ERR_BITSTREAM_ERROR (0x00008101)
#define NVC9B0_MPEG4_VLD_ERR_PIC_HDR_OUT_SIZE_NOT_MULT256 (0x00008200)
#define NVC9B0_MPEG4_VLD_ERR_PIC_DATA_OUT_SIZE_NOT_MULT256 (0x00008201)
#define NVC9B0_MPEG4_VLD_ERR_CTX_DMA_ID_CTRL_IN_INVALID (0x00008202)
#define NVC9B0_MPEG4_VLD_ERR_CTX_DMA_ID_FLOW_CTRL_INVALID (0x00008203)
#define NVC9B0_MPEG4_VLD_ERR_CTX_DMA_ID_PIC_HDR_OUT_INVALID (0x00008204)
#define NVC9B0_MPEG4_VLD_ERR_SLC_HDR_OUT_BUF_TOO_SMALL (0x00008205)
#define NVC9B0_MPEG4_VLD_ERR_PIC_HDR_OUT_BUF_ALREADY_VALID (0x00008206)
#define NVC9B0_MPEG4_VLD_ERR_PIC_DATA_OUT_BUF_TOO_SMALL (0x00008207)
#define NVC9B0_MPEG4_VLD_ERR_DATA_INFO_IN_BUF_TOO_SMALL (0x00008208)
#define NVC9B0_MPEG4_VLD_ERR_BITSTREAM_EMPTY (0x00008209)
#define NVC9B0_MPEG4_VLD_ERR_FRAME_WIDTH_TOO_LARGE (0x0000820A)
#define NVC9B0_MPEG4_VLD_ERR_FRAME_HEIGHT_TOO_LARGE (0x0000820B)
#define NVC9B0_MPEG4_VLD_ERR_PIC_DATA_OUT_BUF_FULL_TIME_OUT (0x00051E01)
#define NVC9B0_DEC_ERROR_MPEG12_APPTIMER_EXPIRED (0xDEC10001)
#define NVC9B0_DEC_ERROR_MPEG12_MVTIMER_EXPIRED (0xDEC10002)
#define NVC9B0_DEC_ERROR_MPEG12_INVALID_TOKEN (0xDEC10003)
#define NVC9B0_DEC_ERROR_MPEG12_SLICEDATA_MISSING (0xDEC10004)
#define NVC9B0_DEC_ERROR_MPEG12_HWERR_INTERRUPT (0xDEC10005)
#define NVC9B0_DEC_ERROR_MPEG12_DETECTED_VLD_FAILURE (0xDEC10006)
#define NVC9B0_DEC_ERROR_MPEG12_PICTURE_INIT (0xDEC10100)
#define NVC9B0_DEC_ERROR_MPEG12_STATEMACHINE_FAILURE (0xDEC10101)
#define NVC9B0_DEC_ERROR_MPEG12_INVALID_CTXID_PIC (0xDEC10901)
#define NVC9B0_DEC_ERROR_MPEG12_INVALID_CTXID_UCODE (0xDEC10902)
#define NVC9B0_DEC_ERROR_MPEG12_INVALID_CTXID_FC (0xDEC10903)
#define NVC9B0_DEC_ERROR_MPEG12_INVALID_CTXID_SLH (0xDEC10904)
#define NVC9B0_DEC_ERROR_MPEG12_INVALID_UCODE_SIZE (0xDEC10905)
#define NVC9B0_DEC_ERROR_MPEG12_INVALID_SLICE_COUNT (0xDEC10906)
#define NVC9B0_DEC_ERROR_VC1_APPTIMER_EXPIRED (0xDEC20001)
#define NVC9B0_DEC_ERROR_VC1_MVTIMER_EXPIRED (0xDEC20002)
#define NVC9B0_DEC_ERROR_VC1_INVALID_TOKEN (0xDEC20003)
#define NVC9B0_DEC_ERROR_VC1_SLICEDATA_MISSING (0xDEC20004)
#define NVC9B0_DEC_ERROR_VC1_HWERR_INTERRUPT (0xDEC20005)
#define NVC9B0_DEC_ERROR_VC1_DETECTED_VLD_FAILURE (0xDEC20006)
#define NVC9B0_DEC_ERROR_VC1_TIMEOUT_POLLING_FOR_DATA (0xDEC20007)
#define NVC9B0_DEC_ERROR_VC1_PDEC_PIC_END_UNALIGNED (0xDEC20008)
#define NVC9B0_DEC_ERROR_VC1_WDTIMER_EXPIRED (0xDEC20009)
#define NVC9B0_DEC_ERROR_VC1_ERRINTSTART (0xDEC20010)
#define NVC9B0_DEC_ERROR_VC1_IQT_ERRINT (0xDEC20011)
#define NVC9B0_DEC_ERROR_VC1_MC_ERRINT (0xDEC20012)
#define NVC9B0_DEC_ERROR_VC1_MC_IQT_ERRINT (0xDEC20013)
#define NVC9B0_DEC_ERROR_VC1_REC_ERRINT (0xDEC20014)
#define NVC9B0_DEC_ERROR_VC1_REC_IQT_ERRINT (0xDEC20015)
#define NVC9B0_DEC_ERROR_VC1_REC_MC_ERRINT (0xDEC20016)
#define NVC9B0_DEC_ERROR_VC1_REC_MC_IQT_ERRINT (0xDEC20017)
#define NVC9B0_DEC_ERROR_VC1_DBF_ERRINT (0xDEC20018)
#define NVC9B0_DEC_ERROR_VC1_DBF_IQT_ERRINT (0xDEC20019)
#define NVC9B0_DEC_ERROR_VC1_DBF_MC_ERRINT (0xDEC2001A)
#define NVC9B0_DEC_ERROR_VC1_DBF_MC_IQT_ERRINT (0xDEC2001B)
#define NVC9B0_DEC_ERROR_VC1_DBF_REC_ERRINT (0xDEC2001C)
#define NVC9B0_DEC_ERROR_VC1_DBF_REC_IQT_ERRINT (0xDEC2001D)
#define NVC9B0_DEC_ERROR_VC1_DBF_REC_MC_ERRINT (0xDEC2001E)
#define NVC9B0_DEC_ERROR_VC1_DBF_REC_MC_IQT_ERRINT (0xDEC2001F)
#define NVC9B0_DEC_ERROR_VC1_PICTURE_INIT (0xDEC20100)
#define NVC9B0_DEC_ERROR_VC1_STATEMACHINE_FAILURE (0xDEC20101)
#define NVC9B0_DEC_ERROR_VC1_INVALID_CTXID_PIC (0xDEC20901)
#define NVC9B0_DEC_ERROR_VC1_INVALID_CTXID_UCODE (0xDEC20902)
#define NVC9B0_DEC_ERROR_VC1_INVALID_CTXID_FC (0xDEC20903)
#define NVC9B0_DEC_ERROR_VC1_INVAILD_CTXID_SLH (0xDEC20904)
#define NVC9B0_DEC_ERROR_VC1_INVALID_UCODE_SIZE (0xDEC20905)
#define NVC9B0_DEC_ERROR_VC1_INVALID_SLICE_COUNT (0xDEC20906)
#define NVC9B0_DEC_ERROR_H264_APPTIMER_EXPIRED (0xDEC30001)
#define NVC9B0_DEC_ERROR_H264_MVTIMER_EXPIRED (0xDEC30002)
#define NVC9B0_DEC_ERROR_H264_INVALID_TOKEN (0xDEC30003)
#define NVC9B0_DEC_ERROR_H264_SLICEDATA_MISSING (0xDEC30004)
#define NVC9B0_DEC_ERROR_H264_HWERR_INTERRUPT (0xDEC30005)
#define NVC9B0_DEC_ERROR_H264_DETECTED_VLD_FAILURE (0xDEC30006)
#define NVC9B0_DEC_ERROR_H264_ERRINTSTART (0xDEC30010)
#define NVC9B0_DEC_ERROR_H264_IQT_ERRINT (0xDEC30011)
#define NVC9B0_DEC_ERROR_H264_MC_ERRINT (0xDEC30012)
#define NVC9B0_DEC_ERROR_H264_MC_IQT_ERRINT (0xDEC30013)
#define NVC9B0_DEC_ERROR_H264_REC_ERRINT (0xDEC30014)
#define NVC9B0_DEC_ERROR_H264_REC_IQT_ERRINT (0xDEC30015)
#define NVC9B0_DEC_ERROR_H264_REC_MC_ERRINT (0xDEC30016)
#define NVC9B0_DEC_ERROR_H264_REC_MC_IQT_ERRINT (0xDEC30017)
#define NVC9B0_DEC_ERROR_H264_DBF_ERRINT (0xDEC30018)
#define NVC9B0_DEC_ERROR_H264_DBF_IQT_ERRINT (0xDEC30019)
#define NVC9B0_DEC_ERROR_H264_DBF_MC_ERRINT (0xDEC3001A)
#define NVC9B0_DEC_ERROR_H264_DBF_MC_IQT_ERRINT (0xDEC3001B)
#define NVC9B0_DEC_ERROR_H264_DBF_REC_ERRINT (0xDEC3001C)
#define NVC9B0_DEC_ERROR_H264_DBF_REC_IQT_ERRINT (0xDEC3001D)
#define NVC9B0_DEC_ERROR_H264_DBF_REC_MC_ERRINT (0xDEC3001E)
#define NVC9B0_DEC_ERROR_H264_DBF_REC_MC_IQT_ERRINT (0xDEC3001F)
#define NVC9B0_DEC_ERROR_H264_PICTURE_INIT (0xDEC30100)
#define NVC9B0_DEC_ERROR_H264_STATEMACHINE_FAILURE (0xDEC30101)
#define NVC9B0_DEC_ERROR_H264_INVALID_CTXID_PIC (0xDEC30901)
#define NVC9B0_DEC_ERROR_H264_INVALID_CTXID_UCODE (0xDEC30902)
#define NVC9B0_DEC_ERROR_H264_INVALID_CTXID_FC (0xDEC30903)
#define NVC9B0_DEC_ERROR_H264_INVALID_CTXID_SLH (0xDEC30904)
#define NVC9B0_DEC_ERROR_H264_INVALID_UCODE_SIZE (0xDEC30905)
#define NVC9B0_DEC_ERROR_H264_INVALID_SLICE_COUNT (0xDEC30906)
#define NVC9B0_DEC_ERROR_MPEG4_APPTIMER_EXPIRED (0xDEC40001)
#define NVC9B0_DEC_ERROR_MPEG4_MVTIMER_EXPIRED (0xDEC40002)
#define NVC9B0_DEC_ERROR_MPEG4_INVALID_TOKEN (0xDEC40003)
#define NVC9B0_DEC_ERROR_MPEG4_SLICEDATA_MISSING (0xDEC40004)
#define NVC9B0_DEC_ERROR_MPEG4_HWERR_INTERRUPT (0xDEC40005)
#define NVC9B0_DEC_ERROR_MPEG4_DETECTED_VLD_FAILURE (0xDEC40006)
#define NVC9B0_DEC_ERROR_MPEG4_TIMEOUT_POLLING_FOR_DATA (0xDEC40007)
#define NVC9B0_DEC_ERROR_MPEG4_PDEC_PIC_END_UNALIGNED (0xDEC40008)
#define NVC9B0_DEC_ERROR_MPEG4_WDTIMER_EXPIRED (0xDEC40009)
#define NVC9B0_DEC_ERROR_MPEG4_ERRINTSTART (0xDEC40010)
#define NVC9B0_DEC_ERROR_MPEG4_IQT_ERRINT (0xDEC40011)
#define NVC9B0_DEC_ERROR_MPEG4_MC_ERRINT (0xDEC40012)
#define NVC9B0_DEC_ERROR_MPEG4_MC_IQT_ERRINT (0xDEC40013)
#define NVC9B0_DEC_ERROR_MPEG4_REC_ERRINT (0xDEC40014)
#define NVC9B0_DEC_ERROR_MPEG4_REC_IQT_ERRINT (0xDEC40015)
#define NVC9B0_DEC_ERROR_MPEG4_REC_MC_ERRINT (0xDEC40016)
#define NVC9B0_DEC_ERROR_MPEG4_REC_MC_IQT_ERRINT (0xDEC40017)
#define NVC9B0_DEC_ERROR_MPEG4_DBF_ERRINT (0xDEC40018)
#define NVC9B0_DEC_ERROR_MPEG4_DBF_IQT_ERRINT (0xDEC40019)
#define NVC9B0_DEC_ERROR_MPEG4_DBF_MC_ERRINT (0xDEC4001A)
#define NVC9B0_DEC_ERROR_MPEG4_DBF_MC_IQT_ERRINT (0xDEC4001B)
#define NVC9B0_DEC_ERROR_MPEG4_DBF_REC_ERRINT (0xDEC4001C)
#define NVC9B0_DEC_ERROR_MPEG4_DBF_REC_IQT_ERRINT (0xDEC4001D)
#define NVC9B0_DEC_ERROR_MPEG4_DBF_REC_MC_ERRINT (0xDEC4001E)
#define NVC9B0_DEC_ERROR_MPEG4_DBF_REC_MC_IQT_ERRINT (0xDEC4001F)
#define NVC9B0_DEC_ERROR_MPEG4_PICTURE_INIT (0xDEC40100)
#define NVC9B0_DEC_ERROR_MPEG4_STATEMACHINE_FAILURE (0xDEC40101)
#define NVC9B0_DEC_ERROR_MPEG4_INVALID_CTXID_PIC (0xDEC40901)
#define NVC9B0_DEC_ERROR_MPEG4_INVALID_CTXID_UCODE (0xDEC40902)
#define NVC9B0_DEC_ERROR_MPEG4_INVALID_CTXID_FC (0xDEC40903)
#define NVC9B0_DEC_ERROR_MPEG4_INVALID_CTXID_SLH (0xDEC40904)
#define NVC9B0_DEC_ERROR_MPEG4_INVALID_UCODE_SIZE (0xDEC40905)
#define NVC9B0_DEC_ERROR_MPEG4_INVALID_SLICE_COUNT (0xDEC40906)
#ifdef __cplusplus
}; /* extern "C" */
#endif
#endif // clc9b0_h

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artifacts/package_sources/tinygrad/extra/nv_gpu_driver/clcec0qmd.h Normal file
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@@ -0,0 +1,865 @@
/*******************************************************************************
Copyright (c) 2025, NVIDIA CORPORATION. All rights reserved.
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
to deal in the Software without restriction, including without limitation
the rights to use, copy, modify, merge, publish, distribute, sublicense,
and/or sell copies of the Software, and to permit persons to whom the
Software is furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
DEALINGS IN THE SOFTWARE.
*******************************************************************************/
#ifndef __CLCEC0QMD_H__
#define __CLCEC0QMD_H__
/*
** Queue Meta Data, Version 05_00
*/
#define NVCEC0_QMDV05_00_HW_ONLY_SPAN_LIST_HEAD_INDEX MW(29:0)
#define NVCEC0_QMDV05_00_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID MW(30:30)
#define NVCEC0_QMDV05_00_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_FALSE 0x00000000
#define NVCEC0_QMDV05_00_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_TRUE 0x00000001
#define NVCEC0_QMDV05_00_HW_ONLY_REQUIRE_SCHEDULING_PCAS MW(31:31)
#define NVCEC0_QMDV05_00_HW_ONLY_SKED_NEXT_QMD_POINTER MW(63:32)
#define NVCEC0_QMDV05_00_INNER_GET MW(94:64)
#define NVCEC0_QMDV05_00_INNER_OVERFLOW MW(95:95)
#define NVCEC0_QMDV05_00_INNER_PUT MW(126:96)
#define NVCEC0_QMDV05_00_INNER_STICKY_OVERFLOW MW(127:127)
#define NVCEC0_QMDV05_00_DEPENDENCE_COUNTER MW(143:128)
#define NVCEC0_QMDV05_00_QMD_GROUP_ID MW(149:144)
#define NVCEC0_QMDV05_00_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST MW(150:150)
#define NVCEC0_QMDV05_00_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_FALSE 0x00000000
#define NVCEC0_QMDV05_00_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_TRUE 0x00000001
#define NVCEC0_QMDV05_00_QMD_TYPE MW(153:151)
#define NVCEC0_QMDV05_00_QMD_TYPE_QUEUE 0x00000000
#define NVCEC0_QMDV05_00_QMD_TYPE_GRID_NULL 0x00000001
#define NVCEC0_QMDV05_00_QMD_TYPE_GRID_CTA 0x00000002
#define NVCEC0_QMDV05_00_QMD_TYPE_GRID_GPC_CGA 0x00000003
#define NVCEC0_QMDV05_00_QMD_TYPE_GRID_GPU_CGA 0x00000004
#define NVCEC0_QMDV05_00_QMD_TYPE_GRID_GPU_GPC_CGA 0x00000005
#define NVCEC0_QMDV05_00_NUM_SUB_TASKS_PER_TASK MW(157:154)
#define NVCEC0_QMDV05_00_REQUIRE_SCHEDULING_PCAS MW(158:158)
#define NVCEC0_QMDV05_00_REQUIRE_SCHEDULING_PCAS_FALSE 0x00000000
#define NVCEC0_QMDV05_00_REQUIRE_SCHEDULING_PCAS_TRUE 0x00000001
#define NVCEC0_QMDV05_00_TPC_DISABLE_MASK_VALID MW(159:159)
#define NVCEC0_QMDV05_00_TPC_DISABLE_MASK_VALID_FALSE 0x00000000
#define NVCEC0_QMDV05_00_TPC_DISABLE_MASK_VALID_TRUE 0x00000001
#define NVCEC0_QMDV05_00_CIRCULAR_QUEUE_SIZE MW(184:160)
#define NVCEC0_QMDV05_00_HW_ONLY_DEPENDENCE_COUNTER MW(207:192)
#define NVCEC0_QMDV05_00_RESUME_SUB_TASK_ID MW(210:208)
#define NVCEC0_QMDV05_00_COMPLETED_SUB_TASK_MASK MW(218:211)
#define NVCEC0_QMDV05_00_GRID_WIDTH_RESUME MW(255:224)
#define NVCEC0_QMDV05_00_GRID_HEIGHT_RESUME MW(271:256)
#define NVCEC0_QMDV05_00_GRID_DEPTH_RESUME MW(287:272)
#define NVCEC0_QMDV05_00_RELEASE_ENABLE(i) MW((288+(i)*16):(288+(i)*16))
#define NVCEC0_QMDV05_00_RELEASE0_ENABLE NVCEC0_QMDV05_00_RELEASE_ENABLE(0)
#define NVCEC0_QMDV05_00_RELEASE1_ENABLE NVCEC0_QMDV05_00_RELEASE_ENABLE(1)
#define NVCEC0_QMDV05_00_RELEASE_ENABLE_FALSE 0x00000000
#define NVCEC0_QMDV05_00_RELEASE_ENABLE_TRUE 0x00000001
#define NVCEC0_QMDV05_00_RELEASE_STRUCTURE_SIZE(i) MW((290+(i)*16):(289+(i)*16))
#define NVCEC0_QMDV05_00_RELEASE_STRUCTURE_SIZE_SEMAPHORE_FOUR_WORDS 0x00000000
#define NVCEC0_QMDV05_00_RELEASE_STRUCTURE_SIZE_SEMAPHORE_ONE_WORD 0x00000001
#define NVCEC0_QMDV05_00_RELEASE_STRUCTURE_SIZE_SEMAPHORE_TWO_WORDS 0x00000002
#define NVCEC0_QMDV05_00_RELEASE_MEMBAR_TYPE(i) MW((291+(i)*16):(291+(i)*16))
#define NVCEC0_QMDV05_00_RELEASE_MEMBAR_TYPE_FE_NONE 0x00000000
#define NVCEC0_QMDV05_00_RELEASE_MEMBAR_TYPE_FE_SYSMEMBAR 0x00000001
#define NVCEC0_QMDV05_00_RELEASE_REDUCTION_ENABLE(i) MW((292+(i)*16):(292+(i)*16))
#define NVCEC0_QMDV05_00_RELEASE_REDUCTION_ENABLE_FALSE 0x00000000
#define NVCEC0_QMDV05_00_RELEASE_REDUCTION_ENABLE_TRUE 0x00000001
#define NVCEC0_QMDV05_00_RELEASE_REDUCTION_OP(i) MW((295+(i)*16):(293+(i)*16))
#define NVCEC0_QMDV05_00_RELEASE_REDUCTION_OP_RED_ADD 0x00000000
#define NVCEC0_QMDV05_00_RELEASE_REDUCTION_OP_RED_MIN 0x00000001
#define NVCEC0_QMDV05_00_RELEASE_REDUCTION_OP_RED_MAX 0x00000002
#define NVCEC0_QMDV05_00_RELEASE_REDUCTION_OP_RED_INC 0x00000003
#define NVCEC0_QMDV05_00_RELEASE_REDUCTION_OP_RED_DEC 0x00000004
#define NVCEC0_QMDV05_00_RELEASE_REDUCTION_OP_RED_AND 0x00000005
#define NVCEC0_QMDV05_00_RELEASE_REDUCTION_OP_RED_OR 0x00000006
#define NVCEC0_QMDV05_00_RELEASE_REDUCTION_OP_RED_XOR 0x00000007
#define NVCEC0_QMDV05_00_RELEASE_REDUCTION_FORMAT(i) MW((297+(i)*16):(296+(i)*16))
#define NVCEC0_QMDV05_00_RELEASE_REDUCTION_FORMAT_UNSIGNED 0x00000000
#define NVCEC0_QMDV05_00_RELEASE_REDUCTION_FORMAT_SIGNED 0x00000001
#define NVCEC0_QMDV05_00_RELEASE_TRAP_TYPE(i) MW((299+(i)*16):(298+(i)*16))
#define NVCEC0_QMDV05_00_RELEASE_TRAP_TYPE_TRAP_NONE 0x00000000
#define NVCEC0_QMDV05_00_RELEASE_TRAP_TYPE_TRAP_UNCONDITIONAL 0x00000001
#define NVCEC0_QMDV05_00_RELEASE_TRAP_TYPE_TRAP_CONDITIONAL 0x00000002
#define NVCEC0_QMDV05_00_RELEASE_TRAP_TYPE_TRAP_CONDITIONAL_EXT 0x00000003
#define NVCEC0_QMDV05_00_RELEASE_PAYLOAD64B(i) MW((300+(i)*16):(300+(i)*16))
#define NVCEC0_QMDV05_00_RELEASE_PAYLOAD64B_FALSE 0x00000000
#define NVCEC0_QMDV05_00_RELEASE_PAYLOAD64B_TRUE 0x00000001
#define NVCEC0_QMDV05_00_RELEASE_RESERVED_INFO(i) MW((303+(i)*16):(301+(i)*16))
#define NVCEC0_QMDV05_00_DEPENDENT_QMD0_ENABLE MW(336:336)
#define NVCEC0_QMDV05_00_DEPENDENT_QMD0_ENABLE_FALSE 0x00000000
#define NVCEC0_QMDV05_00_DEPENDENT_QMD0_ENABLE_TRUE 0x00000001
#define NVCEC0_QMDV05_00_DEPENDENT_QMD0_ACTION MW(339:337)
#define NVCEC0_QMDV05_00_DEPENDENT_QMD0_ACTION_QMD_INCREMENT_PUT 0x00000000
#define NVCEC0_QMDV05_00_DEPENDENT_QMD0_ACTION_QMD_SCHEDULE 0x00000001
#define NVCEC0_QMDV05_00_DEPENDENT_QMD0_ACTION_QMD_INVALIDATE_COPY_SCHEDULE 0x00000003
#define NVCEC0_QMDV05_00_DEPENDENT_QMD0_ACTION_QMD_DECREMENT_DEPENDENCE 0x00000004
#define NVCEC0_QMDV05_00_DEPENDENT_QMD0_PREFETCH MW(340:340)
#define NVCEC0_QMDV05_00_DEPENDENT_QMD0_PREFETCH_FALSE 0x00000000
#define NVCEC0_QMDV05_00_DEPENDENT_QMD0_PREFETCH_TRUE 0x00000001
#define NVCEC0_QMDV05_00_SELF_COPY_ON_COMPLETION MW(341:341)
#define NVCEC0_QMDV05_00_SELF_COPY_ON_COMPLETION_FALSE 0x00000000
#define NVCEC0_QMDV05_00_SELF_COPY_ON_COMPLETION_TRUE 0x00000001
#define NVCEC0_QMDV05_00_DEMOTE_L2_EVICT_LAST MW(342:342)
#define NVCEC0_QMDV05_00_DEMOTE_L2_EVICT_LAST_FALSE 0x00000000
#define NVCEC0_QMDV05_00_DEMOTE_L2_EVICT_LAST_TRUE 0x00000001
#define NVCEC0_QMDV05_00_DISABLE_AUTO_INVALIDATE MW(343:343)
#define NVCEC0_QMDV05_00_DISABLE_AUTO_INVALIDATE_FALSE 0x00000000
#define NVCEC0_QMDV05_00_DISABLE_AUTO_INVALIDATE_TRUE 0x00000001
#define NVCEC0_QMDV05_00_DEPENDENT_QMD1_ENABLE MW(344:344)
#define NVCEC0_QMDV05_00_DEPENDENT_QMD1_ENABLE_FALSE 0x00000000
#define NVCEC0_QMDV05_00_DEPENDENT_QMD1_ENABLE_TRUE 0x00000001
#define NVCEC0_QMDV05_00_DEPENDENT_QMD1_ACTION MW(347:345)
#define NVCEC0_QMDV05_00_DEPENDENT_QMD1_ACTION_QMD_INCREMENT_PUT 0x00000000
#define NVCEC0_QMDV05_00_DEPENDENT_QMD1_ACTION_QMD_SCHEDULE 0x00000001
#define NVCEC0_QMDV05_00_DEPENDENT_QMD1_ACTION_QMD_INVALIDATE_COPY_SCHEDULE 0x00000003
#define NVCEC0_QMDV05_00_DEPENDENT_QMD1_ACTION_QMD_DECREMENT_DEPENDENCE 0x00000004
#define NVCEC0_QMDV05_00_DEPENDENT_QMD1_PREFETCH MW(348:348)
#define NVCEC0_QMDV05_00_DEPENDENT_QMD1_PREFETCH_FALSE 0x00000000
#define NVCEC0_QMDV05_00_DEPENDENT_QMD1_PREFETCH_TRUE 0x00000001
#define NVCEC0_QMDV05_00_CORRELATION_ID_INTERNAL MW(349:349)
#define NVCEC0_QMDV05_00_CORRELATION_ID_INTERNAL_FALSE 0x00000000
#define NVCEC0_QMDV05_00_CORRELATION_ID_INTERNAL_TRUE 0x00000001
#define NVCEC0_QMDV05_00_CWD_MEMBAR_TASK_CHASING_ENABLE MW(350:350)
#define NVCEC0_QMDV05_00_CWD_MEMBAR_TASK_CHASING_ENABLE_FALSE 0x00000000
#define NVCEC0_QMDV05_00_CWD_MEMBAR_TASK_CHASING_ENABLE_TRUE 0x00000001
#define NVCEC0_QMDV05_00_SHARED_ALLOCATION_ENABLE MW(351:351)
#define NVCEC0_QMDV05_00_SHARED_ALLOCATION_ENABLE_FALSE 0x00000000
#define NVCEC0_QMDV05_00_SHARED_ALLOCATION_ENABLE_TRUE 0x00000001
#define NVCEC0_QMDV05_00_CORRELATION_ID MW(383:352)
#define NVCEC0_QMDV05_00_DEPENDENT_QMD0_POINTER MW(415:384)
#define NVCEC0_QMDV05_00_DEPENDENT_QMD1_POINTER MW(447:416)
#define NVCEC0_QMDV05_00_SASS_VERSION MW(455:448)
#define NVCEC0_QMDV05_00_API_VISIBLE_CALL_LIMIT MW(456:456)
#define NVCEC0_QMDV05_00_API_VISIBLE_CALL_LIMIT__32 0x00000000
#define NVCEC0_QMDV05_00_API_VISIBLE_CALL_LIMIT_NO_CHECK 0x00000001
#define NVCEC0_QMDV05_00_SAMPLER_INDEX MW(457:457)
#define NVCEC0_QMDV05_00_SAMPLER_INDEX_INDEPENDENTLY 0x00000000
#define NVCEC0_QMDV05_00_SAMPLER_INDEX_VIA_HEADER_INDEX 0x00000001
#define NVCEC0_QMDV05_00_CONSTANT_BANK_PREFETCH_PRE_MAX_SIZE_SHIFTED8 MW(463:458)
#define NVCEC0_QMDV05_00_QMD_MINOR_VERSION MW(467:464)
#define NVCEC0_QMDV05_00_QMD_MAJOR_VERSION MW(471:468)
#define NVCEC0_QMDV05_00_INVALIDATE_TEXTURE_HEADER_CACHE MW(472:472)
#define NVCEC0_QMDV05_00_INVALIDATE_TEXTURE_HEADER_CACHE_FALSE 0x00000000
#define NVCEC0_QMDV05_00_INVALIDATE_TEXTURE_HEADER_CACHE_TRUE 0x00000001
#define NVCEC0_QMDV05_00_INVALIDATE_TEXTURE_SAMPLER_CACHE MW(473:473)
#define NVCEC0_QMDV05_00_INVALIDATE_TEXTURE_SAMPLER_CACHE_FALSE 0x00000000
#define NVCEC0_QMDV05_00_INVALIDATE_TEXTURE_SAMPLER_CACHE_TRUE 0x00000001
#define NVCEC0_QMDV05_00_INVALIDATE_TEXTURE_DATA_CACHE MW(474:474)
#define NVCEC0_QMDV05_00_INVALIDATE_TEXTURE_DATA_CACHE_FALSE 0x00000000
#define NVCEC0_QMDV05_00_INVALIDATE_TEXTURE_DATA_CACHE_TRUE 0x00000001
#define NVCEC0_QMDV05_00_INVALIDATE_SHADER_DATA_CACHE MW(475:475)
#define NVCEC0_QMDV05_00_INVALIDATE_SHADER_DATA_CACHE_FALSE 0x00000000
#define NVCEC0_QMDV05_00_INVALIDATE_SHADER_DATA_CACHE_TRUE 0x00000001
#define NVCEC0_QMDV05_00_INVALIDATE_INSTRUCTION_CACHE MW(476:476)
#define NVCEC0_QMDV05_00_INVALIDATE_INSTRUCTION_CACHE_FALSE 0x00000000
#define NVCEC0_QMDV05_00_INVALIDATE_INSTRUCTION_CACHE_TRUE 0x00000001
#define NVCEC0_QMDV05_00_INVALIDATE_SHADER_CONSTANT_CACHE MW(477:477)
#define NVCEC0_QMDV05_00_INVALIDATE_SHADER_CONSTANT_CACHE_FALSE 0x00000000
#define NVCEC0_QMDV05_00_INVALIDATE_SHADER_CONSTANT_CACHE_TRUE 0x00000001
#define NVCEC0_QMDV05_00_LATCH_ACQUIRE_INVALIDATE_SHADER_DATA_CACHE MW(478:478)
#define NVCEC0_QMDV05_00_LATCH_ACQUIRE_INVALIDATE_SHADER_DATA_CACHE_FALSE 0x00000000
#define NVCEC0_QMDV05_00_LATCH_ACQUIRE_INVALIDATE_SHADER_DATA_CACHE_TRUE 0x00000001
#define NVCEC0_QMDV05_00_LATCH_ACQUIRE_INVALIDATE_TEXTURE_DATA_CACHE MW(479:479)
#define NVCEC0_QMDV05_00_LATCH_ACQUIRE_INVALIDATE_TEXTURE_DATA_CACHE_FALSE 0x00000000
#define NVCEC0_QMDV05_00_LATCH_ACQUIRE_INVALIDATE_TEXTURE_DATA_CACHE_TRUE 0x00000001
#define NVCEC0_QMDV05_00_RELEASE_SEMAPHORE0_ADDR_LOWER MW(511:480)
#define NVCEC0_QMDV05_00_RELEASE_SEMAPHORE0_ADDR_UPPER MW(536:512)
#define NVCEC0_QMDV05_00_RELEASE_SEMAPHORE0_PAYLOAD_LOWER MW(575:544)
#define NVCEC0_QMDV05_00_RELEASE_SEMAPHORE0_PAYLOAD_UPPER MW(607:576)
#define NVCEC0_QMDV05_00_CWD_REFERENCE_COUNT_DELTA_MINUS_ONE MW(615:608)
#define NVCEC0_QMDV05_00_CWD_REFERENCE_COUNT_ID MW(621:616)
#define NVCEC0_QMDV05_00_CWD_REFERENCE_COUNT_INCR_ENABLE MW(622:622)
#define NVCEC0_QMDV05_00_CWD_REFERENCE_COUNT_INCR_ENABLE_FALSE 0x00000000
#define NVCEC0_QMDV05_00_CWD_REFERENCE_COUNT_INCR_ENABLE_TRUE 0x00000001
#define NVCEC0_QMDV05_00_CWD_REFERENCE_COUNT_DECR_ENABLE MW(623:623)
#define NVCEC0_QMDV05_00_CWD_REFERENCE_COUNT_DECR_ENABLE_FALSE 0x00000000
#define NVCEC0_QMDV05_00_CWD_REFERENCE_COUNT_DECR_ENABLE_TRUE 0x00000001
#define NVCEC0_QMDV05_00_CWD_MEMBAR_TYPE MW(625:624)
#define NVCEC0_QMDV05_00_CWD_MEMBAR_TYPE_L1_NONE 0x00000000
#define NVCEC0_QMDV05_00_CWD_MEMBAR_TYPE_L1_SYSMEMBAR 0x00000001
#define NVCEC0_QMDV05_00_CWD_MEMBAR_TYPE_L1_MEMBAR 0x00000003
#define NVCEC0_QMDV05_00_LATCH_ACQUIRE_INVALIDATE_CONSTANT_CACHE MW(626:626)
#define NVCEC0_QMDV05_00_LATCH_ACQUIRE_INVALIDATE_CONSTANT_CACHE_FALSE 0x00000000
#define NVCEC0_QMDV05_00_LATCH_ACQUIRE_INVALIDATE_CONSTANT_CACHE_TRUE 0x00000001
#define NVCEC0_QMDV05_00_CTA_LAUNCH_QUEUE MW(627:627)
#define NVCEC0_QMDV05_00_FREE_CTA_SLOTS_EMPTY_SM MW(635:628)
#define NVCEC0_QMDV05_00_SYNC_DOMAIN_ID MW(637:636)
#define NVCEC0_QMDV05_00_PRE_EXIT_AT_LAST_CTA_LAUNCH MW(638:638)
#define NVCEC0_QMDV05_00_PRE_EXIT_AT_LAST_CTA_LAUNCH_FALSE 0x00000000
#define NVCEC0_QMDV05_00_PRE_EXIT_AT_LAST_CTA_LAUNCH_TRUE 0x00000001
#define NVCEC0_QMDV05_00_ENABLE_PROGRAM_PRE_EXIT MW(639:639)
#define NVCEC0_QMDV05_00_ENABLE_PROGRAM_PRE_EXIT_FALSE 0x00000000
#define NVCEC0_QMDV05_00_ENABLE_PROGRAM_PRE_EXIT_TRUE 0x00000001
#define NVCEC0_QMDV05_00_ARRIVE_AT_LATCH_ID MW(671:640)
#define NVCEC0_QMDV05_00_WAIT_ON_LATCH_ID MW(703:672)
#define NVCEC0_QMDV05_00_OCCUPANCY_THRESHOLD_SHARED_MEM MW(721:714)
#define NVCEC0_QMDV05_00_OCCUPANCY_MAX_SHARED_MEM MW(729:722)
#define NVCEC0_QMDV05_00_ARRIVE_AT_LATCH_VALID MW(730:730)
#define NVCEC0_QMDV05_00_ARRIVE_AT_LATCH_VALID_FALSE 0x00000000
#define NVCEC0_QMDV05_00_ARRIVE_AT_LATCH_VALID_TRUE 0x00000001
#define NVCEC0_QMDV05_00_WAIT_ON_LATCH_VALID MW(731:731)
#define NVCEC0_QMDV05_00_WAIT_ON_LATCH_VALID_FALSE 0x00000000
#define NVCEC0_QMDV05_00_WAIT_ON_LATCH_VALID_TRUE 0x00000001
#define NVCEC0_QMDV05_00_LATCH_RELEASE_INVALIDATE_ENABLE MW(732:732)
#define NVCEC0_QMDV05_00_LATCH_RELEASE_INVALIDATE_ENABLE_FALSE 0x00000000
#define NVCEC0_QMDV05_00_LATCH_RELEASE_INVALIDATE_ENABLE_TRUE 0x00000001
#define NVCEC0_QMDV05_00_HOLD_CTA_LAUNCH_UNTIL_PARENT_LATCH_ACQUIRE_AND_CTA_COMPLETE MW(733:733)
#define NVCEC0_QMDV05_00_HOLD_CTA_LAUNCH_UNTIL_PARENT_LATCH_ACQUIRE_AND_CTA_COMPLETE_FALSE 0x00000000
#define NVCEC0_QMDV05_00_HOLD_CTA_LAUNCH_UNTIL_PARENT_LATCH_ACQUIRE_AND_CTA_COMPLETE_TRUE 0x00000001
#define NVCEC0_QMDV05_00_HOLD_MEMBAR_UNTIL_LATCH_ACQUIRE MW(734:734)
#define NVCEC0_QMDV05_00_HOLD_MEMBAR_UNTIL_LATCH_ACQUIRE_FALSE 0x00000000
#define NVCEC0_QMDV05_00_HOLD_MEMBAR_UNTIL_LATCH_ACQUIRE_TRUE 0x00000001
#define NVCEC0_QMDV05_00_PRIORITY_DEMOTE_UNTIL_LATCH_ACQUIRE MW(735:735)
#define NVCEC0_QMDV05_00_PRIORITY_DEMOTE_UNTIL_LATCH_ACQUIRE_FALSE 0x00000000
#define NVCEC0_QMDV05_00_PRIORITY_DEMOTE_UNTIL_LATCH_ACQUIRE_TRUE 0x00000001
#define NVCEC0_QMDV05_00_OCCUPANCY_THRESHOLD_WARP MW(743:736)
#define NVCEC0_QMDV05_00_OCCUPANCY_MAX_WARP MW(751:744)
#define NVCEC0_QMDV05_00_OCCUPANCY_THRESHOLD_REGISTER MW(759:752)
#define NVCEC0_QMDV05_00_OCCUPANCY_MAX_REGISTER MW(767:760)
#define NVCEC0_QMDV05_00_RELEASE_SEMAPHORE1_ADDR_LOWER MW(799:768)
#define NVCEC0_QMDV05_00_RELEASE_SEMAPHORE1_ADDR_UPPER MW(824:800)
#define NVCEC0_QMDV05_00_RELEASE_SEMAPHORE1_PAYLOAD_LOWER MW(863:832)
#define NVCEC0_QMDV05_00_RELEASE_SEMAPHORE1_PAYLOAD_UPPER MW(895:864)
#define NVCEC0_QMDV05_00_RELEASE_SEMAPHORE2_ADDR_LOWER MW(927:896)
#define NVCEC0_QMDV05_00_RELEASE_SEMAPHORE2_ADDR_UPPER MW(952:928)
#define NVCEC0_QMDV05_00_RELEASE_SEMAPHORE2_PAYLOAD_LOWER MW(991:960)
#define NVCEC0_QMDV05_00_RELEASE_SEMAPHORE2_PAYLOAD_UPPER MW(1023:992)
#define NVCEC0_QMDV05_00_PROGRAM_ADDRESS_LOWER_SHIFTED4 MW(1055:1024)
#define NVCEC0_QMDV05_00_PROGRAM_ADDRESS_UPPER_SHIFTED4 MW(1076:1056)
#define NVCEC0_QMDV05_00_PROGRAM_PREFETCH_SIZE MW(1085:1077)
#define NVCEC0_QMDV05_00_PROGRAM_PREFETCH_TYPE MW(1087:1086)
#define NVCEC0_QMDV05_00_PROGRAM_PREFETCH_TYPE_PREFETCH_LAUNCH 0x00000000
#define NVCEC0_QMDV05_00_PROGRAM_PREFETCH_TYPE_PREFTECH_POST 0x00000001
#define NVCEC0_QMDV05_00_CTA_THREAD_DIMENSION0 MW(1103:1088)
#define NVCEC0_QMDV05_00_CTA_THREAD_DIMENSION1 MW(1119:1104)
#define NVCEC0_QMDV05_00_CTA_THREAD_DIMENSION2 MW(1127:1120)
#define NVCEC0_QMDV05_00_REGISTER_COUNT MW(1136:1128)
#define NVCEC0_QMDV05_00_BARRIER_COUNT MW(1141:1137)
#define NVCEC0_QMDV05_00_ICC_PREFETCH_SIZE MW(1147:1142)
#define NVCEC0_QMDV05_00_SHARED_MEMORY_SIZE_SHIFTED7 MW(1162:1152)
#define NVCEC0_QMDV05_00_MIN_SM_CONFIG_SHARED_MEM_SIZE MW(1168:1163)
#define NVCEC0_QMDV05_00_MAX_SM_CONFIG_SHARED_MEM_SIZE MW(1174:1169)
#define NVCEC0_QMDV05_00_TARGET_SM_CONFIG_SHARED_MEM_SIZE MW(1180:1175)
#define NVCEC0_QMDV05_00_SHARED_MEM_BARRIER_INIT_ENABLE MW(1181:1181)
#define NVCEC0_QMDV05_00_SHADER_LOCAL_MEMORY_LOW_SIZE_SHIFTED4 MW(1199:1184)
#define NVCEC0_QMDV05_00_SHADER_LOCAL_MEMORY_HIGH_SIZE_SHIFTED4 MW(1215:1200)
#define NVCEC0_QMDV05_00_VIRTUAL_RESOURCE_COUNT MW(1223:1216)
#define NVCEC0_QMDV05_00_GRID_WIDTH MW(1279:1248)
#define NVCEC0_QMDV05_00_GRID_HEIGHT MW(1295:1280)
#define NVCEC0_QMDV05_00_GRID_DEPTH MW(1327:1312)
#define NVCEC0_QMDV05_00_CONSTANT_BUFFER_ADDR_LOWER_SHIFTED6(i) MW((1375+(i)*64):(1344+(i)*64))
#define NVCEC0_QMDV05_00_CONSTANT_BUFFER_ADDR_UPPER_SHIFTED6(i) MW((1394+(i)*64):(1376+(i)*64))
#define NVCEC0_QMDV05_00_CONSTANT_BUFFER_SIZE_SHIFTED4(i) MW((1407+(i)*64):(1395+(i)*64))
#define NVCEC0_QMDV05_00_CONSTANT_BUFFER_VALID(i) MW((1856+(i)*4):(1856+(i)*4))
#define NVCEC0_QMDV05_00_CONSTANT_BUFFER_VALID_FALSE 0x00000000
#define NVCEC0_QMDV05_00_CONSTANT_BUFFER_VALID_TRUE 0x00000001
#define NVCEC0_QMDV05_00_CONSTANT_BUFFER_PREFETCH(i) MW((1858+(i)*4):(1857+(i)*4))
#define NVCEC0_QMDV05_00_CONSTANT_BUFFER_PREFETCH_PREFETCH_NONE 0x00000000
#define NVCEC0_QMDV05_00_CONSTANT_BUFFER_PREFETCH_PREFETCH_PRE 0x00000001
#define NVCEC0_QMDV05_00_CONSTANT_BUFFER_PREFETCH_PREFETCH_POST 0x00000002
#define NVCEC0_QMDV05_00_CONSTANT_BUFFER_INVALIDATE(i) MW((1859+(i)*4):(1859+(i)*4))
#define NVCEC0_QMDV05_00_CONSTANT_BUFFER_INVALIDATE_FALSE 0x00000000
#define NVCEC0_QMDV05_00_CONSTANT_BUFFER_INVALIDATE_TRUE 0x00000001
#define NVCEC0_QMDV05_00_PROGRAM_PREFETCH_ADDR_LOWER_SHIFTED MW(1919:1888)
#define NVCEC0_QMDV05_00_PROGRAM_PREFETCH_ADDR_UPPER_SHIFTED MW(1936:1920)
#define NVCEC0_QMDV05_00_GPC_CGA_WIDTH MW(2053:2048)
#define NVCEC0_QMDV05_00_GPC_CGA_HEIGHT MW(2061:2056)
#define NVCEC0_QMDV05_00_GPC_CGA_DEPTH MW(2069:2064)
#define NVCEC0_QMDV05_00_LARGE_GPC_CGA_WIDTH_MINUS_ONE MW(2075:2072)
#define NVCEC0_QMDV05_00_LARGE_GPC_CGA_HEIGHT_MINUS_ONE MW(2079:2076)
#define NVCEC0_QMDV05_00_CGA_CTA_DISTRIBUTION_MODE MW(2111:2111)
#define NVCEC0_QMDV05_00_CGA_CTA_DISTRIBUTION_MODE_LOAD_BALANCING 0x00000000
#define NVCEC0_QMDV05_00_CGA_CTA_DISTRIBUTION_MODE_MULTI_CAST 0x00000001
#define NVCEC0_QMDV05_00_GPU_CGA_WIDTH MW(2127:2112)
#define NVCEC0_QMDV05_00_GPU_CGA_HEIGHT MW(2143:2128)
#define NVCEC0_QMDV05_00_GPU_CGA_DEPTH MW(2159:2144)
#define NVCEC0_QMDV05_00_DEBUG_ID_LOWER MW(2207:2176)
#define NVCEC0_QMDV05_00_DEBUG_ID_UPPER MW(2239:2208)
#define NVCEC0_QMDV05_00_TPC_DISABLE_MASK(i) MW((2271+(i)*32):(2240+(i)*32))
#define NVCEC0_QMDV05_00_INCOMPLETE_BOX_BASE_WIDTH_RESUME MW(2527:2496)
#define NVCEC0_QMDV05_00_INCOMPLETE_BOX_BASE_HEIGHT_RESUME MW(2543:2528)
#define NVCEC0_QMDV05_00_INCOMPLETE_BOX_BASE_DEPTH_RESUME MW(2559:2544)
#define NVCEC0_QMDV05_00_INCOMPLETE_BOX_OFFSET_WIDTH_RESUME MW(2563:2560)
#define NVCEC0_QMDV05_00_INCOMPLETE_BOX_OFFSET_HEIGHT_RESUME MW(2567:2564)
#define NVCEC0_QMDV05_00_QUEUE_ENTRIES_PER_CTA_LOG2 MW(2596:2592)
#define NVCEC0_QMDV05_00_HW_ONLY_INNER_GET MW(2654:2624)
#define NVCEC0_QMDV05_00_HW_ONLY_INNER_PUT MW(2686:2656)
#define NVCEC0_QMDV05_00_OUTER_PUT MW(3038:3008)
#define NVCEC0_QMDV05_00_OUTER_OVERFLOW MW(3039:3039)
#define NVCEC0_QMDV05_00_OUTER_GET MW(3070:3040)
#define NVCEC0_QMDV05_00_OUTER_STICKY_OVERFLOW MW(3071:3071)
/*
** Queue Meta Data, Version 05_00 (inferred arrays)
*/
#define NVCEC0_QMDV05_00_DEPENDENT_QMD_ENABLE(i) MW((336+(i)*8):(336+(i)*8))
#define NVCEC0_QMDV05_00_DEPENDENT_QMD_ENABLE_FALSE 0x00000000
#define NVCEC0_QMDV05_00_DEPENDENT_QMD_ENABLE_TRUE 0x00000001
#define NVCEC0_QMDV05_00_DEPENDENT_QMD_ACTION(i) MW((339+(i)*8):(337+(i)*8))
#define NVCEC0_QMDV05_00_DEPENDENT_QMD_ACTION_QMD_INCREMENT_PUT 0x00000000
#define NVCEC0_QMDV05_00_DEPENDENT_QMD_ACTION_QMD_SCHEDULE 0x00000001
#define NVCEC0_QMDV05_00_DEPENDENT_QMD_ACTION_QMD_INVALIDATE_COPY_SCHEDULE 0x00000003
#define NVCEC0_QMDV05_00_DEPENDENT_QMD_ACTION_QMD_DECREMENT_DEPENDENCE 0x00000004
#define NVCEC0_QMDV05_00_DEPENDENT_QMD_PREFETCH(i) MW((340+(i)*8):(340+(i)*8))
#define NVCEC0_QMDV05_00_DEPENDENT_QMD_PREFETCH_FALSE 0x00000000
#define NVCEC0_QMDV05_00_DEPENDENT_QMD_PREFETCH_TRUE 0x00000001
#define NVCEC0_QMDV05_00_DEPENDENT_QMD_POINTER(i) MW((415+(i)*32):(384+(i)*32))
/*
** Queue Meta Data, Version 05_01
*/
#define NVCEC0_QMDV05_01_HW_ONLY_SPAN_LIST_HEAD_INDEX MW(29:0)
#define NVCEC0_QMDV05_01_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID MW(30:30)
#define NVCEC0_QMDV05_01_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_FALSE 0x00000000
#define NVCEC0_QMDV05_01_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_TRUE 0x00000001
#define NVCEC0_QMDV05_01_HW_ONLY_REQUIRE_SCHEDULING_PCAS MW(31:31)
#define NVCEC0_QMDV05_01_HW_ONLY_SKED_NEXT_QMD_POINTER MW(63:32)
#define NVCEC0_QMDV05_01_INNER_GET MW(94:64)
#define NVCEC0_QMDV05_01_INNER_OVERFLOW MW(95:95)
#define NVCEC0_QMDV05_01_INNER_PUT MW(126:96)
#define NVCEC0_QMDV05_01_INNER_STICKY_OVERFLOW MW(127:127)
#define NVCEC0_QMDV05_01_DEPENDENCE_COUNTER MW(143:128)
#define NVCEC0_QMDV05_01_QMD_GROUP_ID MW(149:144)
#define NVCEC0_QMDV05_01_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST MW(150:150)
#define NVCEC0_QMDV05_01_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_FALSE 0x00000000
#define NVCEC0_QMDV05_01_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_TRUE 0x00000001
#define NVCEC0_QMDV05_01_QMD_TYPE MW(153:151)
#define NVCEC0_QMDV05_01_QMD_TYPE_QUEUE 0x00000000
#define NVCEC0_QMDV05_01_QMD_TYPE_GRID_NULL 0x00000001
#define NVCEC0_QMDV05_01_QMD_TYPE_GRID_CTA 0x00000002
#define NVCEC0_QMDV05_01_QMD_TYPE_GRID_GPC_CGA 0x00000003
#define NVCEC0_QMDV05_01_QMD_TYPE_GRID_GPU_CGA 0x00000004
#define NVCEC0_QMDV05_01_QMD_TYPE_GRID_GPU_GPC_CGA 0x00000005
#define NVCEC0_QMDV05_01_NUM_SUB_TASKS_PER_TASK MW(157:154)
#define NVCEC0_QMDV05_01_REQUIRE_SCHEDULING_PCAS MW(158:158)
#define NVCEC0_QMDV05_01_REQUIRE_SCHEDULING_PCAS_FALSE 0x00000000
#define NVCEC0_QMDV05_01_REQUIRE_SCHEDULING_PCAS_TRUE 0x00000001
#define NVCEC0_QMDV05_01_TPC_DISABLE_MASK_VALID MW(159:159)
#define NVCEC0_QMDV05_01_TPC_DISABLE_MASK_VALID_FALSE 0x00000000
#define NVCEC0_QMDV05_01_TPC_DISABLE_MASK_VALID_TRUE 0x00000001
#define NVCEC0_QMDV05_01_CIRCULAR_QUEUE_SIZE MW(184:160)
#define NVCEC0_QMDV05_01_HW_ONLY_DEPENDENCE_COUNTER MW(207:192)
#define NVCEC0_QMDV05_01_RESUME_SUB_TASK_ID MW(210:208)
#define NVCEC0_QMDV05_01_COMPLETED_SUB_TASK_MASK MW(218:211)
#define NVCEC0_QMDV05_01_GRID_WIDTH_RESUME MW(255:224)
#define NVCEC0_QMDV05_01_GRID_HEIGHT_RESUME MW(271:256)
#define NVCEC0_QMDV05_01_GRID_DEPTH_RESUME MW(287:272)
#define NVCEC0_QMDV05_01_RELEASE_ENABLE(i) MW((288+(i)*16):(288+(i)*16))
#define NVCEC0_QMDV05_01_RELEASE_ENABLE_FALSE 0x00000000
#define NVCEC0_QMDV05_01_RELEASE_ENABLE_TRUE 0x00000001
#define NVCEC0_QMDV05_01_RELEASE_STRUCTURE_SIZE(i) MW((290+(i)*16):(289+(i)*16))
#define NVCEC0_QMDV05_01_RELEASE_STRUCTURE_SIZE_SEMAPHORE_FOUR_WORDS 0x00000000
#define NVCEC0_QMDV05_01_RELEASE_STRUCTURE_SIZE_SEMAPHORE_ONE_WORD 0x00000001
#define NVCEC0_QMDV05_01_RELEASE_STRUCTURE_SIZE_SEMAPHORE_TWO_WORDS 0x00000002
#define NVCEC0_QMDV05_01_RELEASE_MEMBAR_TYPE(i) MW((291+(i)*16):(291+(i)*16))
#define NVCEC0_QMDV05_01_RELEASE_MEMBAR_TYPE_FE_NONE 0x00000000
#define NVCEC0_QMDV05_01_RELEASE_MEMBAR_TYPE_FE_SYSMEMBAR 0x00000001
#define NVCEC0_QMDV05_01_RELEASE_REDUCTION_ENABLE(i) MW((292+(i)*16):(292+(i)*16))
#define NVCEC0_QMDV05_01_RELEASE_REDUCTION_ENABLE_FALSE 0x00000000
#define NVCEC0_QMDV05_01_RELEASE_REDUCTION_ENABLE_TRUE 0x00000001
#define NVCEC0_QMDV05_01_RELEASE_REDUCTION_OP(i) MW((295+(i)*16):(293+(i)*16))
#define NVCEC0_QMDV05_01_RELEASE_REDUCTION_OP_RED_ADD 0x00000000
#define NVCEC0_QMDV05_01_RELEASE_REDUCTION_OP_RED_MIN 0x00000001
#define NVCEC0_QMDV05_01_RELEASE_REDUCTION_OP_RED_MAX 0x00000002
#define NVCEC0_QMDV05_01_RELEASE_REDUCTION_OP_RED_INC 0x00000003
#define NVCEC0_QMDV05_01_RELEASE_REDUCTION_OP_RED_DEC 0x00000004
#define NVCEC0_QMDV05_01_RELEASE_REDUCTION_OP_RED_AND 0x00000005
#define NVCEC0_QMDV05_01_RELEASE_REDUCTION_OP_RED_OR 0x00000006
#define NVCEC0_QMDV05_01_RELEASE_REDUCTION_OP_RED_XOR 0x00000007
#define NVCEC0_QMDV05_01_RELEASE_REDUCTION_FORMAT(i) MW((297+(i)*16):(296+(i)*16))
#define NVCEC0_QMDV05_01_RELEASE_REDUCTION_FORMAT_UNSIGNED 0x00000000
#define NVCEC0_QMDV05_01_RELEASE_REDUCTION_FORMAT_SIGNED 0x00000001
#define NVCEC0_QMDV05_01_RELEASE_TRAP_TYPE(i) MW((299+(i)*16):(298+(i)*16))
#define NVCEC0_QMDV05_01_RELEASE_TRAP_TYPE_TRAP_NONE 0x00000000
#define NVCEC0_QMDV05_01_RELEASE_TRAP_TYPE_TRAP_UNCONDITIONAL 0x00000001
#define NVCEC0_QMDV05_01_RELEASE_TRAP_TYPE_TRAP_CONDITIONAL 0x00000002
#define NVCEC0_QMDV05_01_RELEASE_TRAP_TYPE_TRAP_CONDITIONAL_EXT 0x00000003
#define NVCEC0_QMDV05_01_RELEASE_PAYLOAD64B(i) MW((300+(i)*16):(300+(i)*16))
#define NVCEC0_QMDV05_01_RELEASE_PAYLOAD64B_FALSE 0x00000000
#define NVCEC0_QMDV05_01_RELEASE_PAYLOAD64B_TRUE 0x00000001
#define NVCEC0_QMDV05_01_RELEASE_RESERVED_INFO(i) MW((303+(i)*16):(301+(i)*16))
#define NVCEC0_QMDV05_01_DEPENDENT_QMD0_ENABLE MW(336:336)
#define NVCEC0_QMDV05_01_DEPENDENT_QMD0_ENABLE_FALSE 0x00000000
#define NVCEC0_QMDV05_01_DEPENDENT_QMD0_ENABLE_TRUE 0x00000001
#define NVCEC0_QMDV05_01_DEPENDENT_QMD0_ACTION MW(339:337)
#define NVCEC0_QMDV05_01_DEPENDENT_QMD0_ACTION_QMD_INCREMENT_PUT 0x00000000
#define NVCEC0_QMDV05_01_DEPENDENT_QMD0_ACTION_QMD_SCHEDULE 0x00000001
#define NVCEC0_QMDV05_01_DEPENDENT_QMD0_ACTION_QMD_INVALIDATE_COPY_SCHEDULE 0x00000003
#define NVCEC0_QMDV05_01_DEPENDENT_QMD0_ACTION_QMD_DECREMENT_DEPENDENCE 0x00000004
#define NVCEC0_QMDV05_01_DEPENDENT_QMD0_PREFETCH MW(340:340)
#define NVCEC0_QMDV05_01_DEPENDENT_QMD0_PREFETCH_FALSE 0x00000000
#define NVCEC0_QMDV05_01_DEPENDENT_QMD0_PREFETCH_TRUE 0x00000001
#define NVCEC0_QMDV05_01_SELF_COPY_ON_COMPLETION MW(341:341)
#define NVCEC0_QMDV05_01_SELF_COPY_ON_COMPLETION_FALSE 0x00000000
#define NVCEC0_QMDV05_01_SELF_COPY_ON_COMPLETION_TRUE 0x00000001
#define NVCEC0_QMDV05_01_DEMOTE_L2_EVICT_LAST MW(342:342)
#define NVCEC0_QMDV05_01_DEMOTE_L2_EVICT_LAST_FALSE 0x00000000
#define NVCEC0_QMDV05_01_DEMOTE_L2_EVICT_LAST_TRUE 0x00000001
#define NVCEC0_QMDV05_01_DISABLE_AUTO_INVALIDATE MW(343:343)
#define NVCEC0_QMDV05_01_DISABLE_AUTO_INVALIDATE_FALSE 0x00000000
#define NVCEC0_QMDV05_01_DISABLE_AUTO_INVALIDATE_TRUE 0x00000001
#define NVCEC0_QMDV05_01_DEPENDENT_QMD1_ENABLE MW(344:344)
#define NVCEC0_QMDV05_01_DEPENDENT_QMD1_ENABLE_FALSE 0x00000000
#define NVCEC0_QMDV05_01_DEPENDENT_QMD1_ENABLE_TRUE 0x00000001
#define NVCEC0_QMDV05_01_DEPENDENT_QMD1_ACTION MW(347:345)
#define NVCEC0_QMDV05_01_DEPENDENT_QMD1_ACTION_QMD_INCREMENT_PUT 0x00000000
#define NVCEC0_QMDV05_01_DEPENDENT_QMD1_ACTION_QMD_SCHEDULE 0x00000001
#define NVCEC0_QMDV05_01_DEPENDENT_QMD1_ACTION_QMD_INVALIDATE_COPY_SCHEDULE 0x00000003
#define NVCEC0_QMDV05_01_DEPENDENT_QMD1_ACTION_QMD_DECREMENT_DEPENDENCE 0x00000004
#define NVCEC0_QMDV05_01_DEPENDENT_QMD1_PREFETCH MW(348:348)
#define NVCEC0_QMDV05_01_DEPENDENT_QMD1_PREFETCH_FALSE 0x00000000
#define NVCEC0_QMDV05_01_DEPENDENT_QMD1_PREFETCH_TRUE 0x00000001
#define NVCEC0_QMDV05_01_CORRELATION_ID_INTERNAL MW(349:349)
#define NVCEC0_QMDV05_01_CORRELATION_ID_INTERNAL_FALSE 0x00000000
#define NVCEC0_QMDV05_01_CORRELATION_ID_INTERNAL_TRUE 0x00000001
#define NVCEC0_QMDV05_01_CWD_MEMBAR_TASK_CHASING_ENABLE MW(350:350)
#define NVCEC0_QMDV05_01_CWD_MEMBAR_TASK_CHASING_ENABLE_FALSE 0x00000000
#define NVCEC0_QMDV05_01_CWD_MEMBAR_TASK_CHASING_ENABLE_TRUE 0x00000001
#define NVCEC0_QMDV05_01_SHARED_ALLOCATION_ENABLE MW(351:351)
#define NVCEC0_QMDV05_01_SHARED_ALLOCATION_ENABLE_FALSE 0x00000000
#define NVCEC0_QMDV05_01_SHARED_ALLOCATION_ENABLE_TRUE 0x00000001
#define NVCEC0_QMDV05_01_CORRELATION_ID MW(383:352)
#define NVCEC0_QMDV05_01_DEPENDENT_QMD0_POINTER MW(415:384)
#define NVCEC0_QMDV05_01_DEPENDENT_QMD1_POINTER MW(447:416)
#define NVCEC0_QMDV05_01_SASS_VERSION MW(455:448)
#define NVCEC0_QMDV05_01_API_VISIBLE_CALL_LIMIT MW(456:456)
#define NVCEC0_QMDV05_01_API_VISIBLE_CALL_LIMIT__32 0x00000000
#define NVCEC0_QMDV05_01_API_VISIBLE_CALL_LIMIT_NO_CHECK 0x00000001
#define NVCEC0_QMDV05_01_SAMPLER_INDEX MW(457:457)
#define NVCEC0_QMDV05_01_SAMPLER_INDEX_INDEPENDENTLY 0x00000000
#define NVCEC0_QMDV05_01_SAMPLER_INDEX_VIA_HEADER_INDEX 0x00000001
#define NVCEC0_QMDV05_01_CONSTANT_BANK_PREFETCH_PRE_MAX_SIZE_SHIFTED8 MW(463:458)
#define NVCEC0_QMDV05_01_QMD_MINOR_VERSION MW(467:464)
#define NVCEC0_QMDV05_01_QMD_MAJOR_VERSION MW(471:468)
#define NVCEC0_QMDV05_01_INVALIDATE_TEXTURE_HEADER_CACHE MW(472:472)
#define NVCEC0_QMDV05_01_INVALIDATE_TEXTURE_HEADER_CACHE_FALSE 0x00000000
#define NVCEC0_QMDV05_01_INVALIDATE_TEXTURE_HEADER_CACHE_TRUE 0x00000001
#define NVCEC0_QMDV05_01_INVALIDATE_TEXTURE_SAMPLER_CACHE MW(473:473)
#define NVCEC0_QMDV05_01_INVALIDATE_TEXTURE_SAMPLER_CACHE_FALSE 0x00000000
#define NVCEC0_QMDV05_01_INVALIDATE_TEXTURE_SAMPLER_CACHE_TRUE 0x00000001
#define NVCEC0_QMDV05_01_INVALIDATE_TEXTURE_DATA_CACHE MW(474:474)
#define NVCEC0_QMDV05_01_INVALIDATE_TEXTURE_DATA_CACHE_FALSE 0x00000000
#define NVCEC0_QMDV05_01_INVALIDATE_TEXTURE_DATA_CACHE_TRUE 0x00000001
#define NVCEC0_QMDV05_01_INVALIDATE_SHADER_DATA_CACHE MW(475:475)
#define NVCEC0_QMDV05_01_INVALIDATE_SHADER_DATA_CACHE_FALSE 0x00000000
#define NVCEC0_QMDV05_01_INVALIDATE_SHADER_DATA_CACHE_TRUE 0x00000001
#define NVCEC0_QMDV05_01_INVALIDATE_INSTRUCTION_CACHE MW(476:476)
#define NVCEC0_QMDV05_01_INVALIDATE_INSTRUCTION_CACHE_FALSE 0x00000000
#define NVCEC0_QMDV05_01_INVALIDATE_INSTRUCTION_CACHE_TRUE 0x00000001
#define NVCEC0_QMDV05_01_INVALIDATE_SHADER_CONSTANT_CACHE MW(477:477)
#define NVCEC0_QMDV05_01_INVALIDATE_SHADER_CONSTANT_CACHE_FALSE 0x00000000
#define NVCEC0_QMDV05_01_INVALIDATE_SHADER_CONSTANT_CACHE_TRUE 0x00000001
#define NVCEC0_QMDV05_01_LATCH_ACQUIRE_INVALIDATE_SHADER_DATA_CACHE MW(478:478)
#define NVCEC0_QMDV05_01_LATCH_ACQUIRE_INVALIDATE_SHADER_DATA_CACHE_FALSE 0x00000000
#define NVCEC0_QMDV05_01_LATCH_ACQUIRE_INVALIDATE_SHADER_DATA_CACHE_TRUE 0x00000001
#define NVCEC0_QMDV05_01_LATCH_ACQUIRE_INVALIDATE_TEXTURE_DATA_CACHE MW(479:479)
#define NVCEC0_QMDV05_01_LATCH_ACQUIRE_INVALIDATE_TEXTURE_DATA_CACHE_FALSE 0x00000000
#define NVCEC0_QMDV05_01_LATCH_ACQUIRE_INVALIDATE_TEXTURE_DATA_CACHE_TRUE 0x00000001
#define NVCEC0_QMDV05_01_RELEASE_SEMAPHORE0_ADDR_LOWER MW(511:480)
#define NVCEC0_QMDV05_01_RELEASE_SEMAPHORE0_ADDR_UPPER MW(536:512)
#define NVCEC0_QMDV05_01_RELEASE_SEMAPHORE0_PAYLOAD_LOWER MW(575:544)
#define NVCEC0_QMDV05_01_RELEASE_SEMAPHORE0_PAYLOAD_UPPER MW(607:576)
#define NVCEC0_QMDV05_01_CWD_REFERENCE_COUNT_DELTA_MINUS_ONE MW(615:608)
#define NVCEC0_QMDV05_01_CWD_REFERENCE_COUNT_ID MW(621:616)
#define NVCEC0_QMDV05_01_CWD_REFERENCE_COUNT_INCR_ENABLE MW(622:622)
#define NVCEC0_QMDV05_01_CWD_REFERENCE_COUNT_INCR_ENABLE_FALSE 0x00000000
#define NVCEC0_QMDV05_01_CWD_REFERENCE_COUNT_INCR_ENABLE_TRUE 0x00000001
#define NVCEC0_QMDV05_01_CWD_REFERENCE_COUNT_DECR_ENABLE MW(623:623)
#define NVCEC0_QMDV05_01_CWD_REFERENCE_COUNT_DECR_ENABLE_FALSE 0x00000000
#define NVCEC0_QMDV05_01_CWD_REFERENCE_COUNT_DECR_ENABLE_TRUE 0x00000001
#define NVCEC0_QMDV05_01_CWD_MEMBAR_TYPE MW(625:624)
#define NVCEC0_QMDV05_01_CWD_MEMBAR_TYPE_L1_NONE 0x00000000
#define NVCEC0_QMDV05_01_CWD_MEMBAR_TYPE_L1_SYSMEMBAR 0x00000001
#define NVCEC0_QMDV05_01_CWD_MEMBAR_TYPE_L1_MEMBAR 0x00000003
#define NVCEC0_QMDV05_01_LATCH_ACQUIRE_INVALIDATE_CONSTANT_CACHE MW(626:626)
#define NVCEC0_QMDV05_01_LATCH_ACQUIRE_INVALIDATE_CONSTANT_CACHE_FALSE 0x00000000
#define NVCEC0_QMDV05_01_LATCH_ACQUIRE_INVALIDATE_CONSTANT_CACHE_TRUE 0x00000001
#define NVCEC0_QMDV05_01_CTA_LAUNCH_QUEUE MW(627:627)
#define NVCEC0_QMDV05_01_FREE_CTA_SLOTS_EMPTY_SM MW(635:628)
#define NVCEC0_QMDV05_01_SYNC_DOMAIN_ID MW(637:636)
#define NVCEC0_QMDV05_01_PRE_EXIT_AT_LAST_CTA_LAUNCH MW(638:638)
#define NVCEC0_QMDV05_01_PRE_EXIT_AT_LAST_CTA_LAUNCH_FALSE 0x00000000
#define NVCEC0_QMDV05_01_PRE_EXIT_AT_LAST_CTA_LAUNCH_TRUE 0x00000001
#define NVCEC0_QMDV05_01_ENABLE_PROGRAM_PRE_EXIT MW(639:639)
#define NVCEC0_QMDV05_01_ENABLE_PROGRAM_PRE_EXIT_FALSE 0x00000000
#define NVCEC0_QMDV05_01_ENABLE_PROGRAM_PRE_EXIT_TRUE 0x00000001
#define NVCEC0_QMDV05_01_ARRIVE_AT_LATCH_ID MW(671:640)
#define NVCEC0_QMDV05_01_WAIT_ON_LATCH_ID MW(703:672)
#define NVCEC0_QMDV05_01_OCCUPANCY_THRESHOLD_SHARED_MEM MW(721:714)
#define NVCEC0_QMDV05_01_OCCUPANCY_MAX_SHARED_MEM MW(729:722)
#define NVCEC0_QMDV05_01_ARRIVE_AT_LATCH_VALID MW(730:730)
#define NVCEC0_QMDV05_01_ARRIVE_AT_LATCH_VALID_FALSE 0x00000000
#define NVCEC0_QMDV05_01_ARRIVE_AT_LATCH_VALID_TRUE 0x00000001
#define NVCEC0_QMDV05_01_WAIT_ON_LATCH_VALID MW(731:731)
#define NVCEC0_QMDV05_01_WAIT_ON_LATCH_VALID_FALSE 0x00000000
#define NVCEC0_QMDV05_01_WAIT_ON_LATCH_VALID_TRUE 0x00000001
#define NVCEC0_QMDV05_01_LATCH_RELEASE_INVALIDATE_ENABLE MW(732:732)
#define NVCEC0_QMDV05_01_LATCH_RELEASE_INVALIDATE_ENABLE_FALSE 0x00000000
#define NVCEC0_QMDV05_01_LATCH_RELEASE_INVALIDATE_ENABLE_TRUE 0x00000001
#define NVCEC0_QMDV05_01_HOLD_CTA_LAUNCH_UNTIL_PARENT_LATCH_ACQUIRE_AND_CTA_COMPLETE MW(733:733)
#define NVCEC0_QMDV05_01_HOLD_CTA_LAUNCH_UNTIL_PARENT_LATCH_ACQUIRE_AND_CTA_COMPLETE_FALSE 0x00000000
#define NVCEC0_QMDV05_01_HOLD_CTA_LAUNCH_UNTIL_PARENT_LATCH_ACQUIRE_AND_CTA_COMPLETE_TRUE 0x00000001
#define NVCEC0_QMDV05_01_HOLD_MEMBAR_UNTIL_LATCH_ACQUIRE MW(734:734)
#define NVCEC0_QMDV05_01_HOLD_MEMBAR_UNTIL_LATCH_ACQUIRE_FALSE 0x00000000
#define NVCEC0_QMDV05_01_HOLD_MEMBAR_UNTIL_LATCH_ACQUIRE_TRUE 0x00000001
#define NVCEC0_QMDV05_01_PRIORITY_DEMOTE_UNTIL_LATCH_ACQUIRE MW(735:735)
#define NVCEC0_QMDV05_01_PRIORITY_DEMOTE_UNTIL_LATCH_ACQUIRE_FALSE 0x00000000
#define NVCEC0_QMDV05_01_PRIORITY_DEMOTE_UNTIL_LATCH_ACQUIRE_TRUE 0x00000001
#define NVCEC0_QMDV05_01_OCCUPANCY_THRESHOLD_WARP MW(743:736)
#define NVCEC0_QMDV05_01_OCCUPANCY_MAX_WARP MW(751:744)
#define NVCEC0_QMDV05_01_OCCUPANCY_THRESHOLD_REGISTER MW(759:752)
#define NVCEC0_QMDV05_01_OCCUPANCY_MAX_REGISTER MW(767:760)
#define NVCEC0_QMDV05_01_SUB_TASK_PROGRAM_ADDRESS_LOWER_SHIFTED4(i) MW((799+(i)*416):(768+(i)*416))
#define NVCEC0_QMDV05_01_SUB_TASK_PROGRAM_ADDRESS_UPPER_SHIFTED4(i) MW((820+(i)*416):(800+(i)*416))
#define NVCEC0_QMDV05_01_SUB_TASK_PROGRAM_PREFETCH_SIZE(i) MW((829+(i)*416):(821+(i)*416))
#define NVCEC0_QMDV05_01_SUB_TASK_PROGRAM_PREFETCH_TYPE(i) MW((831+(i)*416):(830+(i)*416))
#define NVCEC0_QMDV05_01_SUB_TASK_PROGRAM_PREFETCH_TYPE_PREFETCH_LAUNCH 0x00000000
#define NVCEC0_QMDV05_01_SUB_TASK_PROGRAM_PREFETCH_TYPE_PREFTECH_POST 0x00000001
#define NVCEC0_QMDV05_01_SUB_TASK_CTA_THREAD_DIMENSION0(i) MW((847+(i)*416):(832+(i)*416))
#define NVCEC0_QMDV05_01_SUB_TASK_CTA_THREAD_DIMENSION1(i) MW((863+(i)*416):(848+(i)*416))
#define NVCEC0_QMDV05_01_SUB_TASK_CTA_THREAD_DIMENSION2(i) MW((871+(i)*416):(864+(i)*416))
#define NVCEC0_QMDV05_01_SUB_TASK_REGISTER_COUNT(i) MW((880+(i)*416):(872+(i)*416))
#define NVCEC0_QMDV05_01_SUB_TASK_BARRIER_COUNT(i) MW((885+(i)*416):(881+(i)*416))
#define NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK0_VALID(i) MW((886+(i)*416):(886+(i)*416))
#define NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK0_VALID_FALSE 0x00000000
#define NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK0_VALID_TRUE 0x00000001
#define NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK0_PREFETCH(i) MW((888+(i)*416):(887+(i)*416))
#define NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK0_PREFETCH_PREFETCH_NONE 0x00000000
#define NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK0_PREFETCH_PREFETCH_PRE 0x00000001
#define NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK0_PREFETCH_PREFETCH_POST 0x00000002
#define NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK0_INVALIDATE(i) MW((889+(i)*416):(889+(i)*416))
#define NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK0_INVALIDATE_FALSE 0x00000000
#define NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK0_INVALIDATE_TRUE 0x00000001
#define NVCEC0_QMDV05_01_SUB_TASK_ICC_PREFETCH_SIZE(i) MW((895+(i)*416):(890+(i)*416))
#define NVCEC0_QMDV05_01_SUB_TASK_SHARED_MEMORY_SIZE_SHIFTED7(i) MW((906+(i)*416):(896+(i)*416))
#define NVCEC0_QMDV05_01_SUB_TASK_MIN_SM_CONFIG_SHARED_MEM_SIZE(i) MW((912+(i)*416):(907+(i)*416))
#define NVCEC0_QMDV05_01_SUB_TASK_MAX_SM_CONFIG_SHARED_MEM_SIZE(i) MW((918+(i)*416):(913+(i)*416))
#define NVCEC0_QMDV05_01_SUB_TASK_TARGET_SM_CONFIG_SHARED_MEM_SIZE(i) MW((924+(i)*416):(919+(i)*416))
#define NVCEC0_QMDV05_01_SUB_TASK_SHARED_MEM_BARRIER_INIT_ENABLE(i) MW((925+(i)*416):(925+(i)*416))
#define NVCEC0_QMDV05_01_SUB_TASK_SHADER_LOCAL_MEMORY_LOW_SIZE_SHIFTED4(i) MW((943+(i)*416):(928+(i)*416))
#define NVCEC0_QMDV05_01_SUB_TASK_SHADER_LOCAL_MEMORY_HIGH_SIZE_SHIFTED4(i) MW((959+(i)*416):(944+(i)*416))
#define NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK0_ADDR_LOWER_SHIFTED6(i) MW((991+(i)*416):(960+(i)*416))
#define NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK0_ADDR_UPPER_SHIFTED6(i) MW((1010+(i)*416):(992+(i)*416))
#define NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK0_SIZE_SHIFTED4(i) MW((1023+(i)*416):(1011+(i)*416))
#define NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK1_ADDR_LOWER_SHIFTED6(i) MW((1055+(i)*416):(1024+(i)*416))
#define NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK1_ADDR_UPPER_SHIFTED6(i) MW((1074+(i)*416):(1056+(i)*416))
#define NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK1_SIZE_SHIFTED4(i) MW((1087+(i)*416):(1075+(i)*416))
#define NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK1_VALID(i) MW((1088+(i)*416):(1088+(i)*416))
#define NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK1_VALID_FALSE 0x00000000
#define NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK1_VALID_TRUE 0x00000001
#define NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK1_PREFETCH(i) MW((1090+(i)*416):(1089+(i)*416))
#define NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK1_PREFETCH_PREFETCH_NONE 0x00000000
#define NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK1_PREFETCH_PREFETCH_PRE 0x00000001
#define NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK1_PREFETCH_PREFETCH_POST 0x00000002
#define NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK1_INVALIDATE(i) MW((1091+(i)*416):(1091+(i)*416))
#define NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK1_INVALIDATE_FALSE 0x00000000
#define NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK1_INVALIDATE_TRUE 0x00000001
#define NVCEC0_QMDV05_01_SUB_TASK_VIRTUAL_RESOURCE_COUNT(i) MW((1099+(i)*416):(1092+(i)*416))
#define NVCEC0_QMDV05_01_SUB_TASK_GRID_WIDTH(i) MW((1151+(i)*416):(1120+(i)*416))
#define NVCEC0_QMDV05_01_SUB_TASK_GRID_HEIGHT(i) MW((1167+(i)*416):(1152+(i)*416))
#define NVCEC0_QMDV05_01_SUB_TASK_GRID_DEPTH(i) MW((1183+(i)*416):(1168+(i)*416))
/*
** Queue Meta Data, Version 05_01 (inferred arrays)
*/
#define NVCEC0_QMDV05_01_DEPENDENT_QMD_ENABLE(i) MW((336+(i)*8):(336+(i)*8))
#define NVCEC0_QMDV05_01_DEPENDENT_QMD_ENABLE_FALSE 0x00000000
#define NVCEC0_QMDV05_01_DEPENDENT_QMD_ENABLE_TRUE 0x00000001
#define NVCEC0_QMDV05_01_DEPENDENT_QMD_ACTION(i) MW((339+(i)*8):(337+(i)*8))
#define NVCEC0_QMDV05_01_DEPENDENT_QMD_ACTION_QMD_INCREMENT_PUT 0x00000000
#define NVCEC0_QMDV05_01_DEPENDENT_QMD_ACTION_QMD_SCHEDULE 0x00000001
#define NVCEC0_QMDV05_01_DEPENDENT_QMD_ACTION_QMD_INVALIDATE_COPY_SCHEDULE 0x00000003
#define NVCEC0_QMDV05_01_DEPENDENT_QMD_ACTION_QMD_DECREMENT_DEPENDENCE 0x00000004
#define NVCEC0_QMDV05_01_DEPENDENT_QMD_PREFETCH(i) MW((340+(i)*8):(340+(i)*8))
#define NVCEC0_QMDV05_01_DEPENDENT_QMD_PREFETCH_FALSE 0x00000000
#define NVCEC0_QMDV05_01_DEPENDENT_QMD_PREFETCH_TRUE 0x00000001
#define NVCEC0_QMDV05_01_DEPENDENT_QMD_POINTER(i) MW((415+(i)*32):(384+(i)*32))
#define NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK_VALID(i,j) MW((886+(i)*416+(j)*202):(886+(i)*416+(j)*202))
#define NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK_VALID_FALSE 0x00000000
#define NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK_VALID_TRUE 0x00000001
#define NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK_PREFETCH(i,j) MW((888+(i)*416+(j)*202):(887+(i)*416+(j)*202))
#define NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK_PREFETCH_PREFETCH_NONE 0x00000000
#define NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK_PREFETCH_PREFETCH_PRE 0x00000001
#define NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK_PREFETCH_PREFETCH_POST 0x00000002
#define NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK_INVALIDATE(i,j) MW((889+(i)*416+(j)*202):(889+(i)*416+(j)*202))
#define NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK_INVALIDATE_FALSE 0x00000000
#define NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK_INVALIDATE_TRUE 0x00000001
#define NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK_ADDR_LOWER_SHIFTED6(i,j) MW((991+(i)*416+(j)*64):(960+(i)*416+(j)*64))
#define NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK_ADDR_UPPER_SHIFTED6(i,j) MW((1010+(i)*416+(j)*64):(992+(i)*416+(j)*64))
#define NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK_SIZE_SHIFTED4(i,j) MW((1023+(i)*416+(j)*64):(1011+(i)*416+(j)*64))
/*
** Queue Meta Data, Version 04_01
*/
#define NVCEC0_QMDV04_01_DEPENDENCE_COUNTER MW(15:0)
#define NVCEC0_QMDV04_01_QMD_GROUP_ID MW(21:16)
#define NVCEC0_QMDV04_01_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST MW(22:22)
#define NVCEC0_QMDV04_01_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_FALSE 0x00000000
#define NVCEC0_QMDV04_01_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_TRUE 0x00000001
#define NVCEC0_QMDV04_01_QMD_TYPE MW(25:23)
#define NVCEC0_QMDV04_01_QMD_TYPE_QUEUE 0x00000000
#define NVCEC0_QMDV04_01_QMD_TYPE_GRID_NULL 0x00000001
#define NVCEC0_QMDV04_01_QMD_TYPE_GRID_CTA 0x00000002
#define NVCEC0_QMDV04_01_QMD_TYPE_GRID_GPC_CGA 0x00000003
#define NVCEC0_QMDV04_01_QMD_TYPE_GRID_GPU_CGA 0x00000004
#define NVCEC0_QMDV04_01_QMD_TYPE_GRID_GPU_GPC_CGA 0x00000005
#define NVCEC0_QMDV04_01_ARRIVE_AT_LATCH_VALID MW(28:28)
#define NVCEC0_QMDV04_01_WAIT_ON_LATCH_VALID MW(29:29)
#define NVCEC0_QMDV04_01_REQUIRE_SCHEDULING_PCAS MW(30:30)
#define NVCEC0_QMDV04_01_REQUIRE_SCHEDULING_PCAS_FALSE 0x00000000
#define NVCEC0_QMDV04_01_REQUIRE_SCHEDULING_PCAS_TRUE 0x00000001
#define NVCEC0_QMDV04_01_TPC_DISABLE_MASK_VALID MW(31:31)
#define NVCEC0_QMDV04_01_TPC_DISABLE_MASK_VALID_FALSE 0x00000000
#define NVCEC0_QMDV04_01_TPC_DISABLE_MASK_VALID_TRUE 0x00000001
#define NVCEC0_QMDV04_01_CIRCULAR_QUEUE_SIZE MW(56:32)
#define NVCEC0_QMDV04_01_INNER_GET MW(94:64)
#define NVCEC0_QMDV04_01_INNER_OVERFLOW MW(95:95)
#define NVCEC0_QMDV04_01_INNER_PUT MW(126:96)
#define NVCEC0_QMDV04_01_INNER_STICKY_OVERFLOW MW(127:127)
#define NVCEC0_QMDV04_01_HW_ONLY_INNER_GET MW(190:160)
#define NVCEC0_QMDV04_01_HW_ONLY_INNER_PUT MW(222:192)
#define NVCEC0_QMDV04_01_HW_ONLY_SPAN_LIST_HEAD_INDEX MW(253:224)
#define NVCEC0_QMDV04_01_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID MW(254:254)
#define NVCEC0_QMDV04_01_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_FALSE 0x00000000
#define NVCEC0_QMDV04_01_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_TRUE 0x00000001
#define NVCEC0_QMDV04_01_HW_ONLY_SKED_NEXT_QMD_POINTER MW(287:256)
#define NVCEC0_QMDV04_01_HW_ONLY_DEPENDENCE_COUNTER MW(303:288)
#define NVCEC0_QMDV04_01_HW_ONLY_REQUIRE_SCHEDULING_PCAS MW(304:304)
#define NVCEC0_QMDV04_01_RELEASE_ENABLE(i) MW((320+(i)*16):(320+(i)*16))
#define NVCEC0_QMDV04_01_RELEASE_ENABLE_FALSE 0x00000000
#define NVCEC0_QMDV04_01_RELEASE_ENABLE_TRUE 0x00000001
#define NVCEC0_QMDV04_01_RELEASE_STRUCTURE_SIZE(i) MW((322+(i)*16):(321+(i)*16))
#define NVCEC0_QMDV04_01_RELEASE_STRUCTURE_SIZE_SEMAPHORE_FOUR_WORDS 0x00000000
#define NVCEC0_QMDV04_01_RELEASE_STRUCTURE_SIZE_SEMAPHORE_ONE_WORD 0x00000001
#define NVCEC0_QMDV04_01_RELEASE_STRUCTURE_SIZE_SEMAPHORE_TWO_WORDS 0x00000002
#define NVCEC0_QMDV04_01_RELEASE_MEMBAR_TYPE(i) MW((323+(i)*16):(323+(i)*16))
#define NVCEC0_QMDV04_01_RELEASE_MEMBAR_TYPE_FE_NONE 0x00000000
#define NVCEC0_QMDV04_01_RELEASE_MEMBAR_TYPE_FE_SYSMEMBAR 0x00000001
#define NVCEC0_QMDV04_01_RELEASE_REDUCTION_ENABLE(i) MW((324+(i)*16):(324+(i)*16))
#define NVCEC0_QMDV04_01_RELEASE_REDUCTION_ENABLE_FALSE 0x00000000
#define NVCEC0_QMDV04_01_RELEASE_REDUCTION_ENABLE_TRUE 0x00000001
#define NVCEC0_QMDV04_01_RELEASE_REDUCTION_OP(i) MW((327+(i)*16):(325+(i)*16))
#define NVCEC0_QMDV04_01_RELEASE_REDUCTION_OP_RED_ADD 0x00000000
#define NVCEC0_QMDV04_01_RELEASE_REDUCTION_OP_RED_MIN 0x00000001
#define NVCEC0_QMDV04_01_RELEASE_REDUCTION_OP_RED_MAX 0x00000002
#define NVCEC0_QMDV04_01_RELEASE_REDUCTION_OP_RED_INC 0x00000003
#define NVCEC0_QMDV04_01_RELEASE_REDUCTION_OP_RED_DEC 0x00000004
#define NVCEC0_QMDV04_01_RELEASE_REDUCTION_OP_RED_AND 0x00000005
#define NVCEC0_QMDV04_01_RELEASE_REDUCTION_OP_RED_OR 0x00000006
#define NVCEC0_QMDV04_01_RELEASE_REDUCTION_OP_RED_XOR 0x00000007
#define NVCEC0_QMDV04_01_RELEASE_REDUCTION_FORMAT(i) MW((329+(i)*16):(328+(i)*16))
#define NVCEC0_QMDV04_01_RELEASE_REDUCTION_FORMAT_UNSIGNED 0x00000000
#define NVCEC0_QMDV04_01_RELEASE_REDUCTION_FORMAT_SIGNED 0x00000001
#define NVCEC0_QMDV04_01_RELEASE_TRAP_TYPE(i) MW((331+(i)*16):(330+(i)*16))
#define NVCEC0_QMDV04_01_RELEASE_TRAP_TYPE_TRAP_NONE 0x00000000
#define NVCEC0_QMDV04_01_RELEASE_TRAP_TYPE_TRAP_UNCONDITIONAL 0x00000001
#define NVCEC0_QMDV04_01_RELEASE_TRAP_TYPE_TRAP_CONDITIONAL 0x00000002
#define NVCEC0_QMDV04_01_RELEASE_TRAP_TYPE_TRAP_CONDITIONAL_EXT 0x00000003
#define NVCEC0_QMDV04_01_RELEASE_PAYLOAD64B(i) MW((332+(i)*16):(332+(i)*16))
#define NVCEC0_QMDV04_01_RELEASE_PAYLOAD64B_FALSE 0x00000000
#define NVCEC0_QMDV04_01_RELEASE_PAYLOAD64B_TRUE 0x00000001
#define NVCEC0_QMDV04_01_RELEASE_RESERVED_INFO(i) MW((335+(i)*16):(333+(i)*16))
#define NVCEC0_QMDV04_01_DEPENDENT_QMD_ENABLE(i) MW((368+(i)*5):(368+(i)*5))
#define NVCEC0_QMDV04_01_DEPENDENT_QMD_ENABLE_FALSE 0x00000000
#define NVCEC0_QMDV04_01_DEPENDENT_QMD_ENABLE_TRUE 0x00000001
#define NVCEC0_QMDV04_01_DEPENDENT_QMD_ACTION(i) MW((371+(i)*5):(369+(i)*5))
#define NVCEC0_QMDV04_01_DEPENDENT_QMD_ACTION_QMD_INCREMENT_PUT 0x00000000
#define NVCEC0_QMDV04_01_DEPENDENT_QMD_ACTION_QMD_SCHEDULE 0x00000001
#define NVCEC0_QMDV04_01_DEPENDENT_QMD_ACTION_QMD_INVALIDATE_COPY_SCHEDULE 0x00000003
#define NVCEC0_QMDV04_01_DEPENDENT_QMD_ACTION_QMD_DECREMENT_DEPENDENCE 0x00000004
#define NVCEC0_QMDV04_01_DEPENDENT_QMD_PREFETCH(i) MW((372+(i)*5):(372+(i)*5))
#define NVCEC0_QMDV04_01_DEPENDENT_QMD_PREFETCH_FALSE 0x00000000
#define NVCEC0_QMDV04_01_DEPENDENT_QMD_PREFETCH_TRUE 0x00000001
#define NVCEC0_QMDV04_01_SELF_COPY_ON_COMPLETION MW(378:378)
#define NVCEC0_QMDV04_01_SELF_COPY_ON_COMPLETION_FALSE 0x00000000
#define NVCEC0_QMDV04_01_SELF_COPY_ON_COMPLETION_TRUE 0x00000001
#define NVCEC0_QMDV04_01_DEMOTE_L2_EVICT_LAST MW(379:379)
#define NVCEC0_QMDV04_01_DEMOTE_L2_EVICT_LAST_FALSE 0x00000000
#define NVCEC0_QMDV04_01_DEMOTE_L2_EVICT_LAST_TRUE 0x00000001
#define NVCEC0_QMDV04_01_DISABLE_AUTO_INVALIDATE MW(380:380)
#define NVCEC0_QMDV04_01_DISABLE_AUTO_INVALIDATE_FALSE 0x00000000
#define NVCEC0_QMDV04_01_DISABLE_AUTO_INVALIDATE_TRUE 0x00000001
#define NVCEC0_QMDV04_01_CORRELATION_ID_INTERNAL MW(381:381)
#define NVCEC0_QMDV04_01_CORRELATION_ID_INTERNAL_FALSE 0x00000000
#define NVCEC0_QMDV04_01_CORRELATION_ID_INTERNAL_TRUE 0x00000001
#define NVCEC0_QMDV04_01_CWD_MEMBAR_TASK_CHASING_ENABLE MW(382:382)
#define NVCEC0_QMDV04_01_CWD_MEMBAR_TASK_CHASING_ENABLE_FALSE 0x00000000
#define NVCEC0_QMDV04_01_CWD_MEMBAR_TASK_CHASING_ENABLE_TRUE 0x00000001
#define NVCEC0_QMDV04_01_CORRELATION_ID MW(415:384)
#define NVCEC0_QMDV04_01_CONSTANT_BUFFER_VALID(i) MW((416+(i)*4):(416+(i)*4))
#define NVCEC0_QMDV04_01_CONSTANT_BUFFER_VALID_FALSE 0x00000000
#define NVCEC0_QMDV04_01_CONSTANT_BUFFER_VALID_TRUE 0x00000001
#define NVCEC0_QMDV04_01_CONSTANT_BUFFER_PREFETCH(i) MW((418+(i)*4):(417+(i)*4))
#define NVCEC0_QMDV04_01_CONSTANT_BUFFER_PREFETCH_PREFETCH_NONE 0x00000000
#define NVCEC0_QMDV04_01_CONSTANT_BUFFER_PREFETCH_PREFETCH_PRE 0x00000001
#define NVCEC0_QMDV04_01_CONSTANT_BUFFER_PREFETCH_PREFETCH_POST 0x00000002
#define NVCEC0_QMDV04_01_CONSTANT_BUFFER_INVALIDATE(i) MW((419+(i)*4):(419+(i)*4))
#define NVCEC0_QMDV04_01_CONSTANT_BUFFER_INVALIDATE_FALSE 0x00000000
#define NVCEC0_QMDV04_01_CONSTANT_BUFFER_INVALIDATE_TRUE 0x00000001
#define NVCEC0_QMDV04_01_DEPENDENT_QMD0_POINTER MW(479:448)
#define NVCEC0_QMDV04_01_DEPENDENT_QMD1_POINTER MW(511:480)
#define NVCEC0_QMDV04_01_SHADER_LOCAL_MEMORY_LOW_SIZE MW(535:512)
#define NVCEC0_QMDV04_01_SASS_VERSION MW(543:536)
#define NVCEC0_QMDV04_01_SHADER_LOCAL_MEMORY_HIGH_SIZE MW(567:544)
#define NVCEC0_QMDV04_01_API_VISIBLE_CALL_LIMIT MW(568:568)
#define NVCEC0_QMDV04_01_API_VISIBLE_CALL_LIMIT__32 0x00000000
#define NVCEC0_QMDV04_01_API_VISIBLE_CALL_LIMIT_NO_CHECK 0x00000001
#define NVCEC0_QMDV04_01_SAMPLER_INDEX MW(569:569)
#define NVCEC0_QMDV04_01_SAMPLER_INDEX_INDEPENDENTLY 0x00000000
#define NVCEC0_QMDV04_01_SAMPLER_INDEX_VIA_HEADER_INDEX 0x00000001
#define NVCEC0_QMDV04_01_CONSTANT_BUFFER_PREFETCH_PRE_MAX_SIZE_SHIFTED8 MW(575:570)
#define NVCEC0_QMDV04_01_QMD_MINOR_VERSION MW(579:576)
#define NVCEC0_QMDV04_01_QMD_MAJOR_VERSION MW(583:580)
#define NVCEC0_QMDV04_01_SHARED_MEMORY_SIZE MW(601:584)
#define NVCEC0_QMDV04_01_INVALIDATE_TEXTURE_HEADER_CACHE MW(602:602)
#define NVCEC0_QMDV04_01_INVALIDATE_TEXTURE_HEADER_CACHE_FALSE 0x00000000
#define NVCEC0_QMDV04_01_INVALIDATE_TEXTURE_HEADER_CACHE_TRUE 0x00000001
#define NVCEC0_QMDV04_01_INVALIDATE_TEXTURE_SAMPLER_CACHE MW(603:603)
#define NVCEC0_QMDV04_01_INVALIDATE_TEXTURE_SAMPLER_CACHE_FALSE 0x00000000
#define NVCEC0_QMDV04_01_INVALIDATE_TEXTURE_SAMPLER_CACHE_TRUE 0x00000001
#define NVCEC0_QMDV04_01_INVALIDATE_TEXTURE_DATA_CACHE MW(604:604)
#define NVCEC0_QMDV04_01_INVALIDATE_TEXTURE_DATA_CACHE_FALSE 0x00000000
#define NVCEC0_QMDV04_01_INVALIDATE_TEXTURE_DATA_CACHE_TRUE 0x00000001
#define NVCEC0_QMDV04_01_INVALIDATE_SHADER_DATA_CACHE MW(605:605)
#define NVCEC0_QMDV04_01_INVALIDATE_SHADER_DATA_CACHE_FALSE 0x00000000
#define NVCEC0_QMDV04_01_INVALIDATE_SHADER_DATA_CACHE_TRUE 0x00000001
#define NVCEC0_QMDV04_01_INVALIDATE_INSTRUCTION_CACHE MW(606:606)
#define NVCEC0_QMDV04_01_INVALIDATE_INSTRUCTION_CACHE_FALSE 0x00000000
#define NVCEC0_QMDV04_01_INVALIDATE_INSTRUCTION_CACHE_TRUE 0x00000001
#define NVCEC0_QMDV04_01_INVALIDATE_SHADER_CONSTANT_CACHE MW(607:607)
#define NVCEC0_QMDV04_01_INVALIDATE_SHADER_CONSTANT_CACHE_FALSE 0x00000000
#define NVCEC0_QMDV04_01_INVALIDATE_SHADER_CONSTANT_CACHE_TRUE 0x00000001
#define NVCEC0_QMDV04_01_MIN_SM_CONFIG_SHARED_MEM_SIZE MW(613:608)
#define NVCEC0_QMDV04_01_MAX_SM_CONFIG_SHARED_MEM_SIZE MW(619:614)
#define NVCEC0_QMDV04_01_TARGET_SM_CONFIG_SHARED_MEM_SIZE MW(625:620)
#define NVCEC0_QMDV04_01_SHARED_ALLOCATION_ENABLE MW(626:626)
#define NVCEC0_QMDV04_01_SHARED_ALLOCATION_ENABLE_FALSE 0x00000000
#define NVCEC0_QMDV04_01_SHARED_ALLOCATION_ENABLE_TRUE 0x00000001
#define NVCEC0_QMDV04_01_RELEASE_SEMAPHORE0_ADDR_LOWER MW(671:640)
#define NVCEC0_QMDV04_01_RELEASE_SEMAPHORE0_ADDR_UPPER MW(696:672)
#define NVCEC0_QMDV04_01_RELEASE_SEMAPHORE0_PAYLOAD_LOWER MW(735:704)
#define NVCEC0_QMDV04_01_RELEASE_SEMAPHORE0_PAYLOAD_UPPER MW(767:736)
#define NVCEC0_QMDV04_01_RELEASE_SEMAPHORE1_ADDR_LOWER MW(799:768)
#define NVCEC0_QMDV04_01_RELEASE_SEMAPHORE1_ADDR_UPPER MW(824:800)
#define NVCEC0_QMDV04_01_RELEASE_SEMAPHORE1_PAYLOAD_LOWER MW(863:832)
#define NVCEC0_QMDV04_01_RELEASE_SEMAPHORE1_PAYLOAD_UPPER MW(895:864)
#define NVCEC0_QMDV04_01_RELEASE_SEMAPHORE2_ADDR_LOWER MW(927:896)
#define NVCEC0_QMDV04_01_RELEASE_SEMAPHORE2_ADDR_UPPER MW(952:928)
#define NVCEC0_QMDV04_01_RELEASE_SEMAPHORE2_PAYLOAD_LOWER MW(991:960)
#define NVCEC0_QMDV04_01_RELEASE_SEMAPHORE2_PAYLOAD_UPPER MW(1023:992)
#define NVCEC0_QMDV04_01_GRID_WIDTH MW(1055:1024)
#define NVCEC0_QMDV04_01_GRID_HEIGHT MW(1071:1056)
#define NVCEC0_QMDV04_01_GRID_DEPTH MW(1103:1088)
#define NVCEC0_QMDV04_01_CWD_REFERENCE_COUNT_DELTA_MINUS_ONE MW(1127:1120)
#define NVCEC0_QMDV04_01_CWD_REFERENCE_COUNT_ID MW(1133:1128)
#define NVCEC0_QMDV04_01_CWD_REFERENCE_COUNT_INCR_ENABLE MW(1134:1134)
#define NVCEC0_QMDV04_01_CWD_REFERENCE_COUNT_INCR_ENABLE_FALSE 0x00000000
#define NVCEC0_QMDV04_01_CWD_REFERENCE_COUNT_INCR_ENABLE_TRUE 0x00000001
#define NVCEC0_QMDV04_01_CWD_REFERENCE_COUNT_DECR_ENABLE MW(1135:1135)
#define NVCEC0_QMDV04_01_CWD_REFERENCE_COUNT_DECR_ENABLE_FALSE 0x00000000
#define NVCEC0_QMDV04_01_CWD_REFERENCE_COUNT_DECR_ENABLE_TRUE 0x00000001
#define NVCEC0_QMDV04_01_CWD_MEMBAR_TYPE MW(1137:1136)
#define NVCEC0_QMDV04_01_CWD_MEMBAR_TYPE_L1_NONE 0x00000000
#define NVCEC0_QMDV04_01_CWD_MEMBAR_TYPE_L1_SYSMEMBAR 0x00000001
#define NVCEC0_QMDV04_01_CWD_MEMBAR_TYPE_L1_MEMBAR 0x00000003
#define NVCEC0_QMDV04_01_SEQUENTIALLY_RUN_CTAS MW(1138:1138)
#define NVCEC0_QMDV04_01_SEQUENTIALLY_RUN_CTAS_FALSE 0x00000000
#define NVCEC0_QMDV04_01_SEQUENTIALLY_RUN_CTAS_TRUE 0x00000001
#define NVCEC0_QMDV04_01_CTA_LAUNCH_QUEUE MW(1139:1139)
#define NVCEC0_QMDV04_01_FREE_CTA_SLOTS_EMPTY_SM MW(1147:1140)
#define NVCEC0_QMDV04_01_SYNC_DOMAIN_ID MW(1149:1148)
#define NVCEC0_QMDV04_01_PRE_EXIT_AT_LAST_CTA_LAUNCH MW(1150:1150)
#define NVCEC0_QMDV04_01_PRE_EXIT_AT_LAST_CTA_LAUNCH_FALSE 0x00000000
#define NVCEC0_QMDV04_01_PRE_EXIT_AT_LAST_CTA_LAUNCH_TRUE 0x00000001
#define NVCEC0_QMDV04_01_ENABLE_PROGRAM_PRE_EXIT MW(1151:1151)
#define NVCEC0_QMDV04_01_ENABLE_PROGRAM_PRE_EXIT_FALSE 0x00000000
#define NVCEC0_QMDV04_01_ENABLE_PROGRAM_PRE_EXIT_TRUE 0x00000001
#define NVCEC0_QMDV04_01_CTA_THREAD_DIMENSION0 MW(1167:1152)
#define NVCEC0_QMDV04_01_CTA_THREAD_DIMENSION1 MW(1183:1168)
#define NVCEC0_QMDV04_01_CTA_THREAD_DIMENSION2 MW(1191:1184)
#define NVCEC0_QMDV04_01_VIRTUAL_RESOURCE_COUNT MW(1199:1192)
#define NVCEC0_QMDV04_01_REGISTER_COUNT MW(1208:1200)
#define NVCEC0_QMDV04_01_SHARED_MEM_BARRIER_INIT_ENABLE MW(1210:1210)
#define NVCEC0_QMDV04_01_BARRIER_COUNT MW(1215:1211)
#define NVCEC0_QMDV04_01_PROGRAM_ADDRESS_LOWER MW(1247:1216)
#define NVCEC0_QMDV04_01_PROGRAM_ADDRESS_UPPER MW(1272:1248)
#define NVCEC0_QMDV04_01_OCCUPANCY_THRESHOLD_WARP MW(1287:1280)
#define NVCEC0_QMDV04_01_OCCUPANCY_MAX_WARP MW(1295:1288)
#define NVCEC0_QMDV04_01_OCCUPANCY_THRESHOLD_REGISTER MW(1303:1296)
#define NVCEC0_QMDV04_01_OCCUPANCY_MAX_REGISTER MW(1311:1304)
#define NVCEC0_QMDV04_01_OCCUPANCY_THRESHOLD_SHARED_MEM MW(1319:1312)
#define NVCEC0_QMDV04_01_OCCUPANCY_MAX_SHARED_MEM MW(1327:1320)
#define NVCEC0_QMDV04_01_ICC_PREFETCH_SIZE MW(1333:1328)
#define NVCEC0_QMDV04_01_PROGRAM_PREFETCH_ADDR_LOWER_SHIFTED MW(1375:1344)
#define NVCEC0_QMDV04_01_PROGRAM_PREFETCH_ADDR_UPPER_SHIFTED MW(1392:1376)
#define NVCEC0_QMDV04_01_PROGRAM_PREFETCH_SIZE MW(1401:1393)
#define NVCEC0_QMDV04_01_PROGRAM_PREFETCH_TYPE MW(1403:1402)
#define NVCEC0_QMDV04_01_PROGRAM_PREFETCH_TYPE_PREFETCH_LAUNCH 0x00000000
#define NVCEC0_QMDV04_01_PROGRAM_PREFETCH_TYPE_PREFTECH_POST 0x00000001
#define NVCEC0_QMDV04_01_LATCH_ACQUIRE_INVALIDATE_SHADER_DATA_CACHE MW(1406:1406)
#define NVCEC0_QMDV04_01_LATCH_ACQUIRE_INVALIDATE_SHADER_DATA_CACHE_FALSE 0x00000000
#define NVCEC0_QMDV04_01_LATCH_ACQUIRE_INVALIDATE_SHADER_DATA_CACHE_TRUE 0x00000001
#define NVCEC0_QMDV04_01_LATCH_ACQUIRE_INVALIDATE_TEXTURE_DATA_CACHE MW(1407:1407)
#define NVCEC0_QMDV04_01_LATCH_ACQUIRE_INVALIDATE_TEXTURE_DATA_CACHE_FALSE 0x00000000
#define NVCEC0_QMDV04_01_LATCH_ACQUIRE_INVALIDATE_TEXTURE_DATA_CACHE_TRUE 0x00000001
#define NVCEC0_QMDV04_01_GRID_WIDTH_RESUME MW(1439:1408)
#define NVCEC0_QMDV04_01_GRID_HEIGHT_RESUME MW(1455:1440)
#define NVCEC0_QMDV04_01_GRID_DEPTH_RESUME MW(1471:1456)
#define NVCEC0_QMDV04_01_ARRIVE_AT_LATCH_ID MW(1503:1472)
#define NVCEC0_QMDV04_01_WAIT_ON_LATCH_ID MW(1535:1504)
#define NVCEC0_QMDV04_01_CONSTANT_BUFFER_ADDR_LOWER_SHIFTED6(i) MW((1567+(i)*64):(1536+(i)*64))
#define NVCEC0_QMDV04_01_CONSTANT_BUFFER_ADDR_UPPER_SHIFTED6(i) MW((1586+(i)*64):(1568+(i)*64))
#define NVCEC0_QMDV04_01_CONSTANT_BUFFER_SIZE_SHIFTED4(i) MW((1599+(i)*64):(1587+(i)*64))
#define NVCEC0_QMDV04_01_COALESCE_WAITING_PERIOD MW(2135:2128)
#define NVCEC0_QMDV04_01_QUEUE_ENTRIES_PER_CTA_LOG2 MW(2140:2136)
#define NVCEC0_QMDV04_01_GPC_CGA_WIDTH MW(2149:2144)
#define NVCEC0_QMDV04_01_GPC_CGA_HEIGHT MW(2157:2152)
#define NVCEC0_QMDV04_01_GPC_CGA_DEPTH MW(2165:2160)
#define NVCEC0_QMDV04_01_LARGE_GPC_CGA_WIDTH_MINUS_ONE MW(2171:2168)
#define NVCEC0_QMDV04_01_LARGE_GPC_CGA_HEIGHT_MINUS_ONE MW(2175:2172)
#define NVCEC0_QMDV04_01_CGA_CTA_DISTRIBUTION_MODE MW(2207:2207)
#define NVCEC0_QMDV04_01_CGA_CTA_DISTRIBUTION_MODE_LOAD_BALANCING 0x00000000
#define NVCEC0_QMDV04_01_CGA_CTA_DISTRIBUTION_MODE_MULTI_CAST 0x00000001
#define NVCEC0_QMDV04_01_GPU_CGA_WIDTH MW(2223:2208)
#define NVCEC0_QMDV04_01_GPU_CGA_HEIGHT MW(2239:2224)
#define NVCEC0_QMDV04_01_GPU_CGA_DEPTH MW(2255:2240)
#define NVCEC0_QMDV04_01_DEBUG_ID_LOWER MW(2399:2368)
#define NVCEC0_QMDV04_01_DEBUG_ID_UPPER MW(2431:2400)
#define NVCEC0_QMDV04_01_TPC_DISABLE_MASK(i) MW((2463+(i)*32):(2432+(i)*32))
#define NVCEC0_QMDV04_01_INCOMPLETE_BOX_BASE_WIDTH_RESUME MW(2591:2560)
#define NVCEC0_QMDV04_01_INCOMPLETE_BOX_BASE_HEIGHT_RESUME MW(2607:2592)
#define NVCEC0_QMDV04_01_INCOMPLETE_BOX_BASE_DEPTH_RESUME MW(2623:2608)
#define NVCEC0_QMDV04_01_INCOMPLETE_BOX_OFFSET_WIDTH_RESUME MW(2627:2624)
#define NVCEC0_QMDV04_01_INCOMPLETE_BOX_OFFSET_HEIGHT_RESUME MW(2631:2628)
#define NVCEC0_QMDV04_01_TPC_DISABLE_MASK_UPPER(i) MW((2719+(i)*32):(2688+(i)*32))
#define NVCEC0_QMDV04_01_OUTER_PUT MW(3038:3008)
#define NVCEC0_QMDV04_01_OUTER_OVERFLOW MW(3039:3039)
#define NVCEC0_QMDV04_01_OUTER_GET MW(3070:3040)
#define NVCEC0_QMDV04_01_OUTER_STICKY_OVERFLOW MW(3071:3071)
#endif // #ifndef __CLCEC0QMD_H__

25
artifacts/package_sources/tinygrad/extra/nv_gpu_driver/fw.h Normal file
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/* adapted from linux/drivers/gpu/drm/nouveau/include/nvfw/fw.h */
/* SPDX-License-Identifier: MIT */
#ifndef __NVFW_FW_H__
#define __NVFW_FW_H__
typedef unsigned int u32;
struct nvfw_bin_hdr {
u32 bin_magic;
u32 bin_ver;
u32 bin_size;
u32 header_offset;
u32 data_offset;
u32 data_size;
};
struct nvfw_bl_desc {
u32 start_tag;
u32 dmem_load_off;
u32 code_off;
u32 code_size;
u32 data_off;
u32 data_size;
};
#endif

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/*
* SPDX-FileCopyrightText: Copyright (c) 2008-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
/*
* WARNING: This is an autogenerated file. DO NOT EDIT.
* This file is generated using below files:
* template file: inc/kernel/vgpu/gt_rpc-message.h
* definition file: inc/kernel/vgpu/rpc-message-header.def
*/
typedef struct GSP_MSG_QUEUE_ELEMENT
{
NvU8 authTagBuffer[16]; // Authentication tag buffer.
NvU8 aadBuffer[16]; // AAD buffer.
NvU32 checkSum; // Set to value needed to make checksum always zero.
NvU32 seqNum; // Sequence number maintained by the message queue.
NvU32 elemCount; // Number of message queue elements this message has.
NvU32 padding; // Reserved for future use.
} GSP_MSG_QUEUE_ELEMENT;
#ifdef RPC_MESSAGE_STRUCTURES
typedef union rpc_message_rpc_union_field_v03_00
{
NvU32 spare;
NvU32 cpuRmGfid;
} rpc_message_rpc_union_field_v03_00;
typedef rpc_message_rpc_union_field_v03_00 rpc_message_rpc_union_field_v;
typedef struct rpc_message_header_v03_00
{
NvU32 header_version;
NvU32 signature;
NvU32 length;
NvU32 function;
NvU32 rpc_result;
NvU32 rpc_result_private;
NvU32 sequence;
rpc_message_rpc_union_field_v u;
// rpc_generic_union rpc_message_data[];
} rpc_message_header_v03_00;
typedef rpc_message_header_v03_00 rpc_message_header_v;
#endif
#ifdef RPC_MESSAGE_GENERIC_UNION
// This is a generic union, that will be used for the communication between the vmioplugin & guest RM.
typedef union rpc_message_generic_union {
rpc_message_rpc_union_field_v03_00 rpc_union_field_v03_00;
rpc_message_rpc_union_field_v rpc_union_field_v;
rpc_message_header_v03_00 header_v03_00;
rpc_message_header_v header_v;
} rpc_message_generic_union;
#endif

455
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/*
* SPDX-FileCopyrightText: Copyright (c) 2019-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef GSP_STATIC_CONFIG_H
#define GSP_STATIC_CONFIG_H
//
// This header describes the set of static GPU configuration information
// that is collected during GSP RM init and made available to the
// CPU RM (aka GSP client) via NV_RM_RPC_GET_GSP_STATIC_INFO() call.
#include "ctrl/ctrl0080/ctrl0080gpu.h"
#include "ctrl/ctrl2080/ctrl2080bios.h"
#include "ctrl/ctrl2080/ctrl2080fb.h"
#include "ctrl/ctrl2080/ctrl2080gpu.h"
#include "vgpu/rpc_headers.h"
#include "nvacpitypes.h"
#include "ctrl/ctrl0073/ctrl0073system.h"
#define MAX_DSM_SUPPORTED_FUNCS_RTN_LEN 8 // # bytes to store supported functions
#define NV_ACPI_GENERIC_FUNC_COUNT 8
#define REGISTRY_TABLE_ENTRY_TYPE_UNKNOWN 0
#define REGISTRY_TABLE_ENTRY_TYPE_DWORD 1
#define REGISTRY_TABLE_ENTRY_TYPE_BINARY 2
#define REGISTRY_TABLE_ENTRY_TYPE_STRING 3
typedef struct PACKED_REGISTRY_ENTRY
{
NvU32 nameOffset;
NvU8 type;
NvU32 data;
NvU32 length;
} PACKED_REGISTRY_ENTRY;
typedef struct PACKED_REGISTRY_TABLE
{
NvU32 size;
NvU32 numEntries;
} PACKED_REGISTRY_TABLE;
/* Indicates the current state of mux */
typedef enum
{
dispMuxState_None = 0,
dispMuxState_IntegratedGPU,
dispMuxState_DiscreteGPU,
} DISPMUXSTATE;
typedef struct {
// supported function status and cache
NvU32 suppFuncStatus;
NvU8 suppFuncs[MAX_DSM_SUPPORTED_FUNCS_RTN_LEN];
NvU32 suppFuncsLen;
NvBool bArg3isInteger;
// callback status and cache
NvU32 callbackStatus;
NvU32 callback;
} ACPI_DSM_CACHE;
typedef struct {
ACPI_DSM_CACHE dsm[ACPI_DSM_FUNCTION_COUNT];
ACPI_DSM_FUNCTION dispStatusHotplugFunc;
ACPI_DSM_FUNCTION dispStatusConfigFunc;
ACPI_DSM_FUNCTION perfPostPowerStateFunc;
ACPI_DSM_FUNCTION stereo3dStateActiveFunc;
NvU32 dsmPlatCapsCache[ACPI_DSM_FUNCTION_COUNT];
NvU32 MDTLFeatureSupport;
// cache of generic func/subfunction remappings.
ACPI_DSM_FUNCTION dsmCurrentFunc[NV_ACPI_GENERIC_FUNC_COUNT];
NvU32 dsmCurrentSubFunc[NV_ACPI_GENERIC_FUNC_COUNT];
NvU32 dsmCurrentFuncSupport;
} ACPI_DATA;
typedef struct DOD_METHOD_DATA
{
NV_STATUS status;
NvU32 acpiIdListLen;
NvU32 acpiIdList[NV0073_CTRL_SYSTEM_ACPI_ID_MAP_MAX_DISPLAYS];
} DOD_METHOD_DATA;
typedef struct JT_METHOD_DATA
{
NV_STATUS status;
NvU32 jtCaps;
NvU16 jtRevId;
NvBool bSBIOSCaps;
} JT_METHOD_DATA;
typedef struct MUX_METHOD_DATA_ELEMENT
{
NvU32 acpiId;
NvU32 mode;
NV_STATUS status;
} MUX_METHOD_DATA_ELEMENT;
typedef struct MUX_METHOD_DATA
{
NvU32 tableLen;
MUX_METHOD_DATA_ELEMENT acpiIdMuxModeTable[NV0073_CTRL_SYSTEM_ACPI_ID_MAP_MAX_DISPLAYS];
MUX_METHOD_DATA_ELEMENT acpiIdMuxPartTable[NV0073_CTRL_SYSTEM_ACPI_ID_MAP_MAX_DISPLAYS];
MUX_METHOD_DATA_ELEMENT acpiIdMuxStateTable[NV0073_CTRL_SYSTEM_ACPI_ID_MAP_MAX_DISPLAYS];
} MUX_METHOD_DATA;
typedef struct CAPS_METHOD_DATA
{
NV_STATUS status;
NvU32 optimusCaps;
} CAPS_METHOD_DATA;
typedef struct ACPI_METHOD_DATA
{
NvBool bValid;
DOD_METHOD_DATA dodMethodData;
JT_METHOD_DATA jtMethodData;
MUX_METHOD_DATA muxMethodData;
CAPS_METHOD_DATA capsMethodData;
} ACPI_METHOD_DATA;
#define MAX_GROUP_COUNT 2
// #include "gpu/nvbitmask.h"
typedef enum
{
RM_ENGINE_TYPE_NULL = (0x00000000),
RM_ENGINE_TYPE_GR0 = (0x00000001),
RM_ENGINE_TYPE_GR1 = (0x00000002),
RM_ENGINE_TYPE_GR2 = (0x00000003),
RM_ENGINE_TYPE_GR3 = (0x00000004),
RM_ENGINE_TYPE_GR4 = (0x00000005),
RM_ENGINE_TYPE_GR5 = (0x00000006),
RM_ENGINE_TYPE_GR6 = (0x00000007),
RM_ENGINE_TYPE_GR7 = (0x00000008),
RM_ENGINE_TYPE_COPY0 = (0x00000009),
RM_ENGINE_TYPE_COPY1 = (0x0000000a),
RM_ENGINE_TYPE_COPY2 = (0x0000000b),
RM_ENGINE_TYPE_COPY3 = (0x0000000c),
RM_ENGINE_TYPE_COPY4 = (0x0000000d),
RM_ENGINE_TYPE_COPY5 = (0x0000000e),
RM_ENGINE_TYPE_COPY6 = (0x0000000f),
RM_ENGINE_TYPE_COPY7 = (0x00000010),
RM_ENGINE_TYPE_COPY8 = (0x00000011),
RM_ENGINE_TYPE_COPY9 = (0x00000012),
RM_ENGINE_TYPE_COPY10 = (0x00000013),
RM_ENGINE_TYPE_COPY11 = (0x00000014),
RM_ENGINE_TYPE_COPY12 = (0x00000015),
RM_ENGINE_TYPE_COPY13 = (0x00000016),
RM_ENGINE_TYPE_COPY14 = (0x00000017),
RM_ENGINE_TYPE_COPY15 = (0x00000018),
RM_ENGINE_TYPE_COPY16 = (0x00000019),
RM_ENGINE_TYPE_COPY17 = (0x0000001a),
RM_ENGINE_TYPE_COPY18 = (0x0000001b),
RM_ENGINE_TYPE_COPY19 = (0x0000001c),
RM_ENGINE_TYPE_NVDEC0 = (0x0000001d),
RM_ENGINE_TYPE_NVDEC1 = (0x0000001e),
RM_ENGINE_TYPE_NVDEC2 = (0x0000001f),
RM_ENGINE_TYPE_NVDEC3 = (0x00000020),
RM_ENGINE_TYPE_NVDEC4 = (0x00000021),
RM_ENGINE_TYPE_NVDEC5 = (0x00000022),
RM_ENGINE_TYPE_NVDEC6 = (0x00000023),
RM_ENGINE_TYPE_NVDEC7 = (0x00000024),
RM_ENGINE_TYPE_NVENC0 = (0x00000025),
RM_ENGINE_TYPE_NVENC1 = (0x00000026),
RM_ENGINE_TYPE_NVENC2 = (0x00000027),
// Bug 4175886 - Use this new value for all chips once GB20X is released
RM_ENGINE_TYPE_NVENC3 = (0x00000028),
RM_ENGINE_TYPE_VP = (0x00000029),
RM_ENGINE_TYPE_ME = (0x0000002a),
RM_ENGINE_TYPE_PPP = (0x0000002b),
RM_ENGINE_TYPE_MPEG = (0x0000002c),
RM_ENGINE_TYPE_SW = (0x0000002d),
RM_ENGINE_TYPE_TSEC = (0x0000002e),
RM_ENGINE_TYPE_VIC = (0x0000002f),
RM_ENGINE_TYPE_MP = (0x00000030),
RM_ENGINE_TYPE_SEC2 = (0x00000031),
RM_ENGINE_TYPE_HOST = (0x00000032),
RM_ENGINE_TYPE_DPU = (0x00000033),
RM_ENGINE_TYPE_PMU = (0x00000034),
RM_ENGINE_TYPE_FBFLCN = (0x00000035),
RM_ENGINE_TYPE_NVJPEG0 = (0x00000036),
RM_ENGINE_TYPE_NVJPEG1 = (0x00000037),
RM_ENGINE_TYPE_NVJPEG2 = (0x00000038),
RM_ENGINE_TYPE_NVJPEG3 = (0x00000039),
RM_ENGINE_TYPE_NVJPEG4 = (0x0000003a),
RM_ENGINE_TYPE_NVJPEG5 = (0x0000003b),
RM_ENGINE_TYPE_NVJPEG6 = (0x0000003c),
RM_ENGINE_TYPE_NVJPEG7 = (0x0000003d),
RM_ENGINE_TYPE_OFA0 = (0x0000003e),
RM_ENGINE_TYPE_OFA1 = (0x0000003f),
RM_ENGINE_TYPE_RESERVED40 = (0x00000040),
RM_ENGINE_TYPE_RESERVED41 = (0x00000041),
RM_ENGINE_TYPE_RESERVED42 = (0x00000042),
RM_ENGINE_TYPE_RESERVED43 = (0x00000043),
RM_ENGINE_TYPE_RESERVED44 = (0x00000044),
RM_ENGINE_TYPE_RESERVED45 = (0x00000045),
RM_ENGINE_TYPE_RESERVED46 = (0x00000046),
RM_ENGINE_TYPE_RESERVED47 = (0x00000047),
RM_ENGINE_TYPE_RESERVED48 = (0x00000048),
RM_ENGINE_TYPE_RESERVED49 = (0x00000049),
RM_ENGINE_TYPE_RESERVED4a = (0x0000004a),
RM_ENGINE_TYPE_RESERVED4b = (0x0000004b),
RM_ENGINE_TYPE_RESERVED4c = (0x0000004c),
RM_ENGINE_TYPE_RESERVED4d = (0x0000004d),
RM_ENGINE_TYPE_RESERVED4e = (0x0000004e),
RM_ENGINE_TYPE_RESERVED4f = (0x0000004f),
RM_ENGINE_TYPE_RESERVED50 = (0x00000050),
RM_ENGINE_TYPE_RESERVED51 = (0x00000051),
RM_ENGINE_TYPE_RESERVED52 = (0x00000052),
RM_ENGINE_TYPE_RESERVED53 = (0x00000053),
RM_ENGINE_TYPE_LAST = (0x00000054),
} RM_ENGINE_TYPE;
//
// The duplicates in the RM_ENGINE_TYPE. Using define instead of putting them
// in the enum to make sure that each item in the enum has a unique number.
//
#define RM_ENGINE_TYPE_GRAPHICS RM_ENGINE_TYPE_GR0
#define RM_ENGINE_TYPE_BSP RM_ENGINE_TYPE_NVDEC0
#define RM_ENGINE_TYPE_MSENC RM_ENGINE_TYPE_NVENC0
#define RM_ENGINE_TYPE_CIPHER RM_ENGINE_TYPE_TSEC
#define RM_ENGINE_TYPE_NVJPG RM_ENGINE_TYPE_NVJPEG0
#define RM_ENGINE_TYPE_COPY_SIZE 20
// Bug 4175886 - Use this new value for all chips once GB20X is released
#define RM_ENGINE_TYPE_NVENC_SIZE 4
#define RM_ENGINE_TYPE_NVJPEG_SIZE 8
#define RM_ENGINE_TYPE_NVDEC_SIZE 8
#define RM_ENGINE_TYPE_OFA_SIZE 2
#define RM_ENGINE_TYPE_GR_SIZE 8
#define NVGPU_ENGINE_CAPS_MASK_BITS 32
#define NVGPU_ENGINE_CAPS_MASK_ARRAY_MAX ((RM_ENGINE_TYPE_LAST-1)/NVGPU_ENGINE_CAPS_MASK_BITS + 1)
#define NVGPU_GET_ENGINE_CAPS_MASK(caps, id) (caps[(id)/NVGPU_ENGINE_CAPS_MASK_BITS] & NVBIT((id) % NVGPU_ENGINE_CAPS_MASK_BITS))
#define NVGPU_SET_ENGINE_CAPS_MASK(caps, id) (caps[(id)/NVGPU_ENGINE_CAPS_MASK_BITS] |= NVBIT((id) % NVGPU_ENGINE_CAPS_MASK_BITS))
// #include "gpu/gpu.h" // COMPUTE_BRANDING_TYPE
// #include "gpu/gpu_acpi_data.h" // ACPI_METHOD_DATA
// #include "vgpu/rpc_headers.h" // MAX_GPC_COUNT
// #include "platform/chipset/chipset.h" // BUSINFO
// #include "gpu/nvbitmask.h" // NVGPU_ENGINE_CAPS_MASK_ARRAY_MAX
typedef struct
{
NvU16 deviceID; // deviceID
NvU16 vendorID; // vendorID
NvU16 subdeviceID; // subsystem deviceID
NvU16 subvendorID; // subsystem vendorID
NvU8 revisionID; // revision ID
} BUSINFO;
// VF related info for GSP-RM
typedef struct GSP_VF_INFO
{
NvU32 totalVFs;
NvU32 firstVFOffset;
NvU64 FirstVFBar0Address;
NvU64 FirstVFBar1Address;
NvU64 FirstVFBar2Address;
NvBool b64bitBar0;
NvBool b64bitBar1;
NvBool b64bitBar2;
} GSP_VF_INFO;
// Cache config registers from pcie space
typedef struct
{
// Link capabilities
NvU32 linkCap;
} GSP_PCIE_CONFIG_REG;
typedef struct
{
NvU32 ecidLow;
NvU32 ecidHigh;
NvU32 ecidExtended;
} EcidManufacturingInfo;
typedef struct
{
NvU64 nonWprHeapOffset;
NvU64 frtsOffset;
} FW_WPR_LAYOUT_OFFSET;
// Fetched from GSP-RM into CPU-RM
typedef struct GspStaticConfigInfo_t
{
NvU8 grCapsBits[NV0080_CTRL_GR_CAPS_TBL_SIZE];
NV2080_CTRL_GPU_GET_GID_INFO_PARAMS gidInfo;
NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS SKUInfo;
NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_PARAMS fbRegionInfoParams;
NV0080_CTRL_GPU_GET_SRIOV_CAPS_PARAMS sriovCaps;
NvU32 sriovMaxGfid;
NvU32 engineCaps[NVGPU_ENGINE_CAPS_MASK_ARRAY_MAX];
NvBool poisonFuseEnabled;
NvU64 fb_length;
NvU64 fbio_mask;
NvU32 fb_bus_width;
NvU32 fb_ram_type;
NvU64 fbp_mask;
NvU32 l2_cache_size;
NvU8 gpuNameString[NV2080_GPU_MAX_NAME_STRING_LENGTH];
NvU8 gpuShortNameString[NV2080_GPU_MAX_NAME_STRING_LENGTH];
NvU16 gpuNameString_Unicode[NV2080_GPU_MAX_NAME_STRING_LENGTH];
NvBool bGpuInternalSku;
NvBool bIsQuadroGeneric;
NvBool bIsQuadroAd;
NvBool bIsNvidiaNvs;
NvBool bIsVgx;
NvBool bGeforceSmb;
NvBool bIsTitan;
NvBool bIsTesla;
NvBool bIsMobile;
NvBool bIsGc6Rtd3Allowed;
NvBool bIsGc8Rtd3Allowed;
NvBool bIsGcOffRtd3Allowed;
NvBool bIsGcoffLegacyAllowed;
NvBool bIsMigSupported;
/* "Total Board Power" refers to power requirement of GPU,
* while in GC6 state. Majority of this power will be used
* to keep V-RAM active to preserve its content.
* Some energy maybe consumed by Always-on components on GPU chip.
* This power will be provided by 3.3v voltage rail.
*/
NvU16 RTD3GC6TotalBoardPower;
/* PERST# (i.e. PCI Express Reset) is a sideband signal
* generated by the PCIe Host to indicate the PCIe devices,
* that the power-rails and the reference-clock are stable.
* The endpoint device typically uses this signal as a global reset.
*/
NvU16 RTD3GC6PerstDelay;
NvU64 bar1PdeBase;
NvU64 bar2PdeBase;
NvBool bVbiosValid;
NvU32 vbiosSubVendor;
NvU32 vbiosSubDevice;
NvBool bPageRetirementSupported;
NvBool bSplitVasBetweenServerClientRm;
NvBool bClRootportNeedsNosnoopWAR;
VIRTUAL_DISPLAY_GET_NUM_HEADS_PARAMS displaylessMaxHeads;
VIRTUAL_DISPLAY_GET_MAX_RESOLUTION_PARAMS displaylessMaxResolution;
NvU64 displaylessMaxPixels;
// Client handle for internal RMAPI control.
NvHandle hInternalClient;
// Device handle for internal RMAPI control.
NvHandle hInternalDevice;
// Subdevice handle for internal RMAPI control.
NvHandle hInternalSubdevice;
NvBool bSelfHostedMode;
NvBool bAtsSupported;
NvBool bIsGpuUefi;
NvBool bIsEfiInit;
EcidManufacturingInfo ecidInfo[MAX_GROUP_COUNT];
FW_WPR_LAYOUT_OFFSET fwWprLayoutOffset;
} GspStaticConfigInfo;
// Pushed from CPU-RM to GSP-RM
typedef struct GspSystemInfo
{
NvU64 gpuPhysAddr;
NvU64 gpuPhysFbAddr;
NvU64 gpuPhysInstAddr;
NvU64 gpuPhysIoAddr;
NvU64 nvDomainBusDeviceFunc;
NvU64 simAccessBufPhysAddr;
NvU64 notifyOpSharedSurfacePhysAddr;
NvU64 pcieAtomicsOpMask;
NvU64 consoleMemSize;
NvU64 maxUserVa;
NvU32 pciConfigMirrorBase;
NvU32 pciConfigMirrorSize;
NvU32 PCIDeviceID;
NvU32 PCISubDeviceID;
NvU32 PCIRevisionID;
NvU32 pcieAtomicsCplDeviceCapMask;
NvU8 oorArch;
NvU64 clPdbProperties;
NvU32 Chipset;
NvBool bGpuBehindBridge;
NvBool bFlrSupported;
NvBool b64bBar0Supported;
NvBool bMnocAvailable;
NvU32 chipsetL1ssEnable;
NvBool bUpstreamL0sUnsupported;
NvBool bUpstreamL1Unsupported;
NvBool bUpstreamL1PorSupported;
NvBool bUpstreamL1PorMobileOnly;
NvBool bSystemHasMux;
NvU8 upstreamAddressValid;
BUSINFO FHBBusInfo;
BUSINFO chipsetIDInfo;
ACPI_METHOD_DATA acpiMethodData;
NvU32 hypervisorType;
NvBool bIsPassthru;
NvU64 sysTimerOffsetNs;
GSP_VF_INFO gspVFInfo;
NvBool bIsPrimary;
NvBool isGridBuild;
GSP_PCIE_CONFIG_REG pcieConfigReg;
NvU32 gridBuildCsp;
NvBool bPreserveVideoMemoryAllocations;
NvBool bTdrEventSupported;
NvBool bFeatureStretchVblankCapable;
NvBool bEnableDynamicGranularityPageArrays;
NvBool bClockBoostSupported;
NvBool bRouteDispIntrsToCPU;
NvU64 hostPageSize;
} GspSystemInfo;
#endif /* GSP_STATIC_CONFIG_H */

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/* adapted from linux/drivers/gpu/drm/nouveau/include/nvfw/hs.h */
/* SPDX-License-Identifier: MIT */
#ifndef __NVFW_HS_H__
#define __NVFW_HS_H__
typedef unsigned int u32;
struct nvfw_hs_header {
u32 sig_dbg_offset;
u32 sig_dbg_size;
u32 sig_prod_offset;
u32 sig_prod_size;
u32 patch_loc;
u32 patch_sig;
u32 hdr_offset;
u32 hdr_size;
};
struct nvfw_hs_header_v2 {
u32 sig_prod_offset;
u32 sig_prod_size;
u32 patch_loc;
u32 patch_sig;
u32 meta_data_offset;
u32 meta_data_size;
u32 num_sig;
u32 header_offset;
u32 header_size;
};
struct nvfw_hs_load_header {
u32 non_sec_code_off;
u32 non_sec_code_size;
u32 data_dma_base;
u32 data_size;
u32 num_apps;
u32 apps[];
};
struct nvfw_hs_load_header_v2 {
u32 os_code_offset;
u32 os_code_size;
u32 os_data_offset;
u32 os_data_size;
u32 num_apps;
struct {
u32 offset;
u32 size;
u32 data_offset;
u32 data_size;
} app[];
};
#endif

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# type: ignore
import ctypes, ctypes.util, struct, platform, pathlib, re, time, os, signal
from tinygrad.helpers import from_mv, to_mv, getenv
from tinygrad.runtime.support.c import init_c_struct_t
from hexdump import hexdump
start = time.perf_counter()
# *** ioctl lib ***
libc = ctypes.CDLL(ctypes.util.find_library("c"))
processor = platform.processor()
IOCTL_SYSCALL = {"aarch64": 0x1d, "x86_64":16}[processor]
MMAP_SYSCALL = {"aarch64": 0xde, "x86_64":0x09}[processor]
IOCTL_PRINT = getenv("IOCTL_PRINT", getenv("IOCTL", 0))
GRAB_PMA = getenv("GRAB_PMA", 0)
def get_struct(argp, stype):
return ctypes.cast(ctypes.c_void_p(argp), ctypes.POINTER(stype)).contents
def dump_struct(st):
if IOCTL_PRINT == 0: return
print("\t", st.__class__.__name__, end=" { ")
for v in type(st)._real_fields_: print(f"{v[0]}={getattr(st, v[0])}", end=" ")
print("}")
def format_struct(s):
sdats = []
for field in s._real_fields_:
dat = getattr(s, field[0])
if isinstance(dat, int): sdats.append(f"{field[0]}:0x{dat:X}")
else: sdats.append(f"{field[0]}:{dat}")
return sdats
real_func_pool = {}
def install_hook(c_function, python_function):
orig_func = (ctypes.c_char*4096)()
python_function_addr = ctypes.cast(ctypes.byref(python_function), ctypes.POINTER(ctypes.c_ulong)).contents.value
# AARCH64 trampoline to ioctl
if processor == "aarch64":
# 0x0000000000000000: 70 00 00 10 adr x16, #0xc
# 0x0000000000000004: 10 02 40 F9 ldr x16, [x16]
# 0x0000000000000008: 00 02 1F D6 br x16
tramp = b"\x70\x00\x00\x10\x10\x02\x40\xf9\x00\x02\x1f\xd6"
tramp += struct.pack("Q", python_function_addr)
elif processor == "x86_64":
# 0x0000000000000000: 49 BB aa aa aa aa aa aa aa aa movabs r11, <address>
# 0x000000000000000a: 41 FF E3 jmp r11
tramp = b"\x49\xBB" + struct.pack("Q", python_function_addr) + b"\x41\xFF\xE3"
else:
raise Exception(f"processor {processor} not supported")
# get real ioctl address
ioctl_address = ctypes.cast(ctypes.byref(c_function), ctypes.POINTER(ctypes.c_ulong))
# hook ioctl
ret = libc.mprotect(ctypes.c_ulong((ioctl_address.contents.value//0x1000)*0x1000), 0x2000, 7)
assert ret == 0
ret = libc.mprotect(ctypes.c_ulong((ctypes.addressof(orig_func)//0x1000)*0x1000), 0x3000, 7)
assert ret == 0
libc.memcpy(orig_func, ioctl_address.contents, 0x1000)
libc.memcpy(ioctl_address.contents, ctypes.create_string_buffer(tramp), len(tramp))
return orig_func
# *** ioctl lib end ***
# PMA buffer tracking for raw PC sampling data (only when GRAB_PMA is enabled)
pma_mem_handle = 0 # hMemPmaBuffer from ALLOC_PMA_STREAM
pma_buffer_size = 0
pma_buffer_va = 0 # actual mapped VA (found via /proc/self/maps)
pma_get_offset = 0 # current read offset in ring buffer
pma_pending_map = False # flag to check for new mapping on next ioctl
pma_maps_before = set() # mappings before MAP_MEMORY
pma_raw_dumps: list[bytes] = [] # raw PMA buffer dumps
def get_pma_raw_dumps() -> list[bytes]: return pma_raw_dumps
def clear_pma_raw_dumps(): pma_raw_dumps.clear()
def get_proc_maps():
"""Read current process memory mappings as set of (start, end) tuples."""
result = set()
with open("/proc/self/maps", "r") as f:
for line in f:
addr_range = line.split()[0]
start, end = addr_range.split("-")
result.add((int(start, 16), int(end, 16)))
return result
from tinygrad.runtime.autogen import nv_570 as nv_gpu
nvescs = {getattr(nv_gpu, x):x for x in dir(nv_gpu) if x.startswith("NV_ESC")}
nvcmds = {getattr(nv_gpu, x):(x, getattr(nv_gpu, "struct_"+x+"_PARAMS", getattr(nv_gpu, "struct_"+x.replace("_CMD_", "_")+"_PARAMS", None))) for x in dir(nv_gpu) if \
x.startswith("NV") and x[6:].startswith("_CTRL_") and isinstance(getattr(nv_gpu, x), int)}
def get_classes():
res = {}
known_classes = {"NV01_DEVICE_0", "NV01_ROOT", "NV1_MEMORY_SYSTEM", "NV01_MEMORY_VIRTUAL", "NV1_MEMORY_USER", "NV50_MEMORY_VIRTUAL", "NV_FERMI_VASPACE_A",
"NV20_SUBDEVICE_0"}
for nm,val in nv_gpu.__dict__.items():
if not isinstance(val, int): continue
if nm.endswith("PARAMETERS_MESSAGE_ID"): continue
if 0x3000 < val < 0xffff: res[val] = nm
if nm in known_classes: res[val] = nm
return res
nvclasses = get_classes()
nvuvms = {getattr(nv_gpu, x):x for x in dir(nv_gpu) if x.startswith("UVM_") and nv_gpu.__dict__.get(x+"_PARAMS")}
nvqcmds = {int(getattr(nv_gpu, x)):x for x in dir(nv_gpu) if x[:7] in {"NVC9B0_", "NVC6C0_", "NVC56F_", "NVC6B5_"} and isinstance(getattr(nv_gpu, x), int)}
global_ioctl_id = 0
gpus_user_modes = []
gpus_mmio = []
gpus_fifo = []
offset_load = 0
@ctypes.CFUNCTYPE(ctypes.c_int, ctypes.c_int, ctypes.c_ulong, ctypes.c_void_p)
def ioctl(fd, request, argp):
global global_ioctl_id, gpus_user_modes, gpus_mmio
global pma_mem_handle, pma_buffer_size, pma_buffer_va, pma_get_offset, pma_pending_map, pma_maps_before
global_ioctl_id += 1
# Check for new PMA buffer mapping from previous MAP_MEMORY call (only when GRAB_PMA is enabled)
if GRAB_PMA and pma_pending_map:
pma_pending_map = False
new_maps = get_proc_maps()
for start, end in new_maps - pma_maps_before:
if end - start == pma_buffer_size:
pma_buffer_va = start
if IOCTL_PRINT >= 1: print(f"\t PMA buffer mapped at CPU VA=0x{pma_buffer_va:x}")
break
st = time.perf_counter()
ret = libc.syscall(IOCTL_SYSCALL, ctypes.c_int(fd), ctypes.c_ulong(request), ctypes.c_void_p(argp))
et = time.perf_counter()-st
fn = os.readlink(f"/proc/self/fd/{fd}")
idir, size, itype, nr = (request>>30), (request>>16)&0x3FFF, (request>>8)&0xFF, request&0xFF
if IOCTL_PRINT >= 1: print(f"#{global_ioctl_id}: ", end="")
if itype == ord(nv_gpu.NV_IOCTL_MAGIC):
if nr == nv_gpu.NV_ESC_RM_CONTROL:
s = get_struct(argp, nv_gpu.NVOS54_PARAMETERS)
if s.cmd in nvcmds:
name, struc = nvcmds[s.cmd]
if IOCTL_PRINT >= 1:
print(f"NV_ESC_RM_CONTROL cmd={name:30s} hClient={s.hClient}, hObject={s.hObject}, flags={s.flags}, params={s.params}, paramsSize={s.paramsSize}, status={s.status}")
if struc is not None: dump_struct(get_struct(s.params, struc))
elif hasattr(nv_gpu, name+"_PARAMS"): dump_struct(get_struct(argp, getattr(nv_gpu, name+"_PARAMS")))
elif name == "NVA06C_CTRL_CMD_GPFIFO_SCHEDULE": dump_struct(get_struct(argp, nv_gpu.NVA06C_CTRL_GPFIFO_SCHEDULE_PARAMS))
elif name == "NV83DE_CTRL_CMD_GET_MAPPINGS": dump_struct(get_struct(s.params, nv_gpu.NV83DE_CTRL_DEBUG_GET_MAPPINGS_PARAMETERS))
elif name == "NVB0CC_CTRL_CMD_SET_HS_CREDITS":
hs_params = get_struct(s.params, nv_gpu.NVB0CC_CTRL_SET_HS_CREDITS_PARAMS)
dump_struct(hs_params)
if IOCTL_PRINT >= 2:
for i in range(hs_params.numEntries):
print(f"\t\t", end="")
dump_struct(hs_params.creditInfo[i])
# PMA buffer tracking (only when GRAB_PMA is enabled)
if GRAB_PMA and name == "NVB0CC_CTRL_CMD_ALLOC_PMA_STREAM":
pma_params = get_struct(s.params, nv_gpu.struct_NVB0CC_CTRL_ALLOC_PMA_STREAM_PARAMS)
pma_mem_handle = pma_params.hMemPmaBuffer
pma_buffer_size = pma_params.pmaBufferSize
pma_get_offset = 0 # Reset read offset for new stream
if IOCTL_PRINT >= 1: print(f"\t PMA buffer: hMem=0x{pma_mem_handle:x} size={pma_buffer_size}")
if GRAB_PMA and name == "NVB0CC_CTRL_CMD_PMA_STREAM_UPDATE_GET_PUT":
pma_update = get_struct(s.params, nv_gpu.struct_NVB0CC_CTRL_PMA_STREAM_UPDATE_GET_PUT_PARAMS)
if pma_update.bytesAvailable > 0 and pma_buffer_va and pma_buffer_size > 0:
avail = pma_update.bytesAvailable
read_offset = pma_get_offset
# Handle ring buffer wrap-around
if pma_get_offset + avail <= pma_buffer_size:
pma_data = bytes(to_mv(pma_buffer_va + pma_get_offset, avail))
else:
# Wrap around: read to end, then from start
first_part = pma_buffer_size - pma_get_offset
second_part = avail - first_part
pma_data = bytes(to_mv(pma_buffer_va + pma_get_offset, first_part)) + bytes(to_mv(pma_buffer_va, second_part))
pma_raw_dumps.append(pma_data)
pma_get_offset = (pma_get_offset + avail) % pma_buffer_size
if IOCTL_PRINT >= 2:
print(f"\t PMA data: {avail} bytes from offset=0x{read_offset:x}, new offset=0x{pma_get_offset:x}")
hexdump(pma_data)
# Dump regOps for EXEC_REG_OPS when IOCTL >= 3
if name == "NVB0CC_CTRL_CMD_EXEC_REG_OPS" and struc is not None and IOCTL_PRINT >= 3:
reg_params = get_struct(s.params, struc)
for i in range(reg_params.regOpCount):
print(f"\t\t", end="")
dump_struct(reg_params.regOps[i])
# val = (op.regValueHi << 32) | op.regValueLo
# print(f"\t regOps[{i:3d}]: op={op.regOp} type={op.regType} status={op.regStatus} offset=0x{op.regOffset:08x} value=0x{val:016x}")
else:
if IOCTL_PRINT >= 1: print("unhandled cmd", hex(s.cmd))
# format_struct(s)
# print(f"{(st-start)*1000:7.2f} ms +{et*1000.:7.2f} ms : {ret:2d} = {name:40s}", ' '.join(format_struct(s)))
elif nr == nv_gpu.NV_ESC_RM_ALLOC:
s = get_struct(argp, nv_gpu.NVOS21_PARAMETERS)
if IOCTL_PRINT >= 1: print(f"NV_ESC_RM_ALLOC hClass={nvclasses.get(s.hClass, f'unk=0x{s.hClass:X}'):30s}, hRoot={s.hRoot}, hObjectParent={s.hObjectParent}, pAllocParms={s.pAllocParms}, hObjectNew={s.hObjectNew} status={s.status}")
if s.pAllocParms is not None:
if s.hClass == nv_gpu.NV01_DEVICE_0: dump_struct(get_struct(s.pAllocParms, nv_gpu.NV0080_ALLOC_PARAMETERS))
if s.hClass == nv_gpu.FERMI_VASPACE_A: dump_struct(get_struct(s.pAllocParms, nv_gpu.NV_VASPACE_ALLOCATION_PARAMETERS))
if s.hClass == nv_gpu.NV50_MEMORY_VIRTUAL: dump_struct(get_struct(s.pAllocParms, nv_gpu.NV_MEMORY_ALLOCATION_PARAMS))
if s.hClass == nv_gpu.NV1_MEMORY_USER: dump_struct(get_struct(s.pAllocParms, nv_gpu.NV_MEMORY_ALLOCATION_PARAMS))
if s.hClass == nv_gpu.NV1_MEMORY_SYSTEM: dump_struct(get_struct(s.pAllocParms, nv_gpu.NV_MEMORY_ALLOCATION_PARAMS))
if s.hClass == nv_gpu.GT200_DEBUGGER: dump_struct(get_struct(s.pAllocParms, nv_gpu.NV83DE_ALLOC_PARAMETERS))
if s.hClass == nv_gpu.MAXWELL_PROFILER_DEVICE: dump_struct(get_struct(s.pAllocParms, nv_gpu.NVB2CC_ALLOC_PARAMETERS))
if s.hClass in {nv_gpu.AMPERE_CHANNEL_GPFIFO_A, nv_gpu.BLACKWELL_CHANNEL_GPFIFO_A}:
sx = get_struct(s.pAllocParms, nv_gpu.NV_CHANNELGPFIFO_ALLOCATION_PARAMETERS)
dump_struct(sx)
gpus_fifo.append((sx.gpFifoOffset, sx.gpFifoEntries))
if s.hClass == nv_gpu.KEPLER_CHANNEL_GROUP_A: dump_struct(get_struct(s.pAllocParms, nv_gpu.NV_CHANNEL_GROUP_ALLOCATION_PARAMETERS))
if s.hClass == nv_gpu.TURING_USERMODE_A: gpus_user_modes.append(s.hObjectNew)
elif nr == nv_gpu.NV_ESC_RM_MAP_MEMORY:
# nv_ioctl_nvos33_parameters_with_fd
s = get_struct(argp, nv_gpu.NVOS33_PARAMETERS)
if IOCTL_PRINT >= 1:
print(f"NV_ESC_RM_MAP_MEMORY hClient={s.hClient}, hDevice={s.hDevice}, hMemory={s.hMemory}, length={s.length} flags={s.flags} pLinearAddress={s.pLinearAddress}")
# Track PMA buffer mapping - save maps now, check for new mapping on next ioctl (after mmap happens)
if GRAB_PMA and pma_mem_handle and s.hMemory == pma_mem_handle:
pma_maps_before = get_proc_maps()
pma_pending_map = True
elif nr == nv_gpu.NV_ESC_RM_UPDATE_DEVICE_MAPPING_INFO:
if IOCTL_PRINT >= 1:
s = get_struct(argp, nv_gpu.NVOS56_PARAMETERS)
print(f"NV_ESC_RM_UPDATE_DEVICE_MAPPING_INFO hClient={s.hClient}, hDevice={s.hDevice}, hMemory={s.hMemory}, pOldCpuAddress={s.pOldCpuAddress} pNewCpuAddress={s.pNewCpuAddress} status={s.status}")
elif nr == nv_gpu.NV_ESC_RM_ALLOC_MEMORY:
if IOCTL_PRINT >= 1:
s = get_struct(argp, nv_gpu.nv_ioctl_nvos02_parameters_with_fd)
print(f"NV_ESC_RM_ALLOC_MEMORY fd={s.fd}, hRoot={s.params.hRoot}, hObjectParent={s.params.hObjectParent}, hObjectNew={s.params.hObjectNew}, hClass={s.params.hClass}, flags={s.params.flags}, pMemory={s.params.pMemory}, limit={s.params.limit}, status={s.params.status}")
elif nr == nv_gpu.NV_ESC_ALLOC_OS_EVENT:
if IOCTL_PRINT >= 1:
s = get_struct(argp, nv_gpu.nv_ioctl_alloc_os_event_t)
print(f"NV_ESC_ALLOC_OS_EVENT hClient={s.hClient} hDevice={s.hDevice} fd={s.fd} Status={s.Status}")
elif nr == nv_gpu.NV_ESC_REGISTER_FD:
if IOCTL_PRINT >= 1:
s = get_struct(argp, nv_gpu.nv_ioctl_register_fd_t)
print(f"NV_ESC_REGISTER_FD fd={s.ctl_fd}")
elif nr in nvescs:
if IOCTL_PRINT >= 1: print(nvescs[nr])
else:
if IOCTL_PRINT >= 1: print("unhandled NR", nr)
elif fn.endswith("nvidia-uvm"):
if IOCTL_PRINT >= 1:
print(f"{nvuvms.get(request, f'UVM UNKNOWN {request=}')}")
if nvuvms.get(request) is not None: dump_struct(get_struct(argp, getattr(nv_gpu, nvuvms.get(request)+"_PARAMS")))
if nvuvms.get(request) == "UVM_MAP_EXTERNAL_ALLOCATION":
st = get_struct(argp, getattr(nv_gpu, nvuvms.get(request)+"_PARAMS"))
for i in range(st.gpuAttributesCount):
print("perGpuAttributes[{i}] = ", end="")
dump_struct(st.perGpuAttributes[i])
if IOCTL_PRINT >= 2: print("ioctl", f"{idir=} {size=} {itype=} {nr=} {fd=} {ret=}", fn)
return ret
@ctypes.CFUNCTYPE(ctypes.c_void_p, ctypes.c_void_p, ctypes.c_size_t, ctypes.c_int, ctypes.c_int, ctypes.c_int, ctypes.c_long)
def _mmap(addr, length, prot, flags, fd, offset):
mmap_type = ctypes.CFUNCTYPE(ctypes.c_void_p, ctypes.c_void_p, ctypes.c_size_t, ctypes.c_int, ctypes.c_int, ctypes.c_int, ctypes.c_long)
orig_mmap = mmap_type(ctypes.addressof(orig_mmap_mv))
ret = orig_mmap(addr, length, prot, flags, fd, offset)
# ll = os.readlink(f"/proc/self/fd/{fd}") if fd >= 0 else ""
print(f"mmap {addr=}, {length=}, {prot=}, {flags=}, {fd=}, {offset=} {ret=}")
return ret
install_hook(libc.ioctl, ioctl)
if getenv("IOCTL") >= 4: orig_mmap_mv = install_hook(libc.mmap, _mmap)
import collections
old_gpputs = collections.defaultdict(int)
def _dump_gpfifo(mark):
launches = []
print("_dump_gpfifo:", mark)
for start, size in gpus_fifo:
gpfifo_controls = nv_gpu.AmpereAControlGPFifo.from_address(start+size*8)
gpfifo = to_mv(start, size * 8).cast("Q")
while old_gpputs[start] != gpfifo_controls.GPPut:
addr = ((gpfifo[old_gpputs[start]] & ((1 << 40)-1)) >> 2) << 2
pckt_cnt = (gpfifo[old_gpputs[start]]>>42)&((1 << 20)-1)
# print(f"\t{i}: 0x{gpfifo[i % size]:x}: addr:0x{addr:x} packets:{pckt_cnt} sync:{(gpfifo[i % size] >> 63) & 0x1} fetch:{gpfifo[i % size] & 0x1}")
x = _dump_qmd(addr, pckt_cnt)
if isinstance(x, list): launches += x
old_gpputs[start] += 1
old_gpputs[start] %= size
return launches
import types
def make_qmd_struct_type():
fields: List[Tuple[str, Union[Type[ctypes.c_uint64], Type[ctypes.c_uint32]], Any]] = []
bits = [(name,dt) for name,dt in nv_gpu.__dict__.items() if name.startswith("NVC6C0_QMDV03_00") and isinstance(dt, tuple)]
bits += [(name+f"_{i}",dt(i)) for name,dt in nv_gpu.__dict__.items() for i in range(8) if name.startswith("NVC6C0_QMDV03_00") and callable(dt)]
bits = sorted(bits, key=lambda x: x[1][1])
for i,(name, data) in enumerate(bits):
if i > 0 and (gap:=(data[1] - bits[i-1][1][0] - 1)) != 0: fields.append((f"_reserved{i}", ctypes.c_uint32, gap))
fields.append((name.replace("NVC6C0_QMDV03_00_", "").lower(), ctypes.c_uint32, data[0]-data[1]+1))
if len(fields) >= 2 and fields[-2][0].endswith('_lower') and fields[-1][0].endswith('_upper') and fields[-1][0][:-6] == fields[-2][0][:-6]:
fields = fields[:-2] + [(fields[-1][0][:-6], ctypes.c_uint64, fields[-1][2] + fields[-2][2])]
return init_c_struct_t(0x40 * 4, tuple(fields))
qmd_struct_t = make_qmd_struct_type()
assert ctypes.sizeof(qmd_struct_t) == 0x40 * 4
def _dump_qmd(address, packets):
qmds = []
gpfifo = to_mv(address, packets * 4).cast("I")
i = 0
while i < packets:
dat = gpfifo[i]
typ = (dat>>28) & 0xF
if typ == 0: break
size = (dat>>16) & 0xFFF
subc = (dat>>13) & 7
mthd = (dat<<2) & 0x7FFF
method_name = nvqcmds.get(mthd, f"unknown method #{mthd}")
if IOCTL_PRINT >= 1:
print(f"\t\t{method_name}, {typ=} {size=} {subc=} {mthd=}")
for j in range(size): print(f"\t\t\t{j}: {gpfifo[i+j+1]} | 0x{gpfifo[i+j+1]:x}")
if mthd == 792:
qmds.append(qmd_struct_t.from_address(address + 12 + i * 4))
elif mthd == nv_gpu.NVC6C0_SEND_PCAS_A:
qmds.append(qmd_struct_t.from_address(gpfifo[i+1] << 8))
i += size + 1
return qmds
# This is to be used in fuzzer, check cuda/nv side by side.
# Return a state which should be compare and compare function.
def before_launch(): _dump_gpfifo("before launch")
def collect_last_launch_state(): return _dump_gpfifo("after launch")
def compare_launch_state(states, good_states):
states = states or list()
good_states = good_states or list()
if len(states) != 1 or len(good_states) != 1:
return False, f"Some states not captured. {len(states)}!=1 || {len(good_states)}!=1"
for i in range(len(states)):
state, good_state = states[i], good_states[i]
for n in ['qmd_major_version', 'invalidate_shader_data_cache', 'invalidate_shader_data_cache',
'sm_global_caching_enable', 'invalidate_texture_header_cache', 'invalidate_texture_sampler_cache',
'barrier_count', 'sampler_index', 'api_visible_call_limit', 'cwd_membar_type', 'sass_version',
'max_sm_config_shared_mem_size', 'register_count_v', 'shared_memory_size']:
if getattr(state, n) != getattr(good_state, n):
return False, f"Field {n} mismatch: {getattr(state, n)} vs {getattr(good_state, n)}"
# Allow NV to allocate more, at least this is not exact problem, so ignore it here.
# Hmm, CUDA minimum is 0x640, is this hw-required minimum (will check)?
if state.shader_local_memory_high_size < good_state.shader_local_memory_high_size and good_state.shader_local_memory_high_size > 0x640:
return False, f"Field shader_local_memory_high_size mismatch: {state.shader_local_memory_high_size}vs{good_state.shader_local_memory_high_size}"
# TODO: Can't request more, since it might not be optimal, but need to investigate their formula for this.. #7133
if state.min_sm_config_shared_mem_size > good_state.min_sm_config_shared_mem_size and good_state.min_sm_config_shared_mem_size > 5:
return (False,
f"Field min_sm_config_shared_mem_size mismatch: {state.min_sm_config_shared_mem_size}vs{good_state.min_sm_config_shared_mem_size}")
if state.target_sm_config_shared_mem_size > good_state.target_sm_config_shared_mem_size and good_state.target_sm_config_shared_mem_size > 5:
return (False,
f"Field target_sm_config_shared_mem_size mismatch: {state.target_sm_config_shared_mem_size}vs{good_state.target_sm_config_shared_mem_size}")
for i in range(8):
if i in {1, 7}: continue # shaders don't use that. what's cuda put here?
n = f"constant_buffer_valid_{i}"
if getattr(state, n) != getattr(good_state, n):
return False, f"Field {n} mismatch: {getattr(state, n)} vs {getattr(good_state, n)}"
return True, "PASS"
# IOCTL=1 CUDA=1 CUDA_PTX=1 python3 test/test_ops.py TestOps.test_tiny_add

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/*
* SPDX-FileCopyrightText: Copyright (c) 1993-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef PCIEXPTBL_H
#define PCIEXPTBL_H
#define NV_BCRT_HASH_INFO_BASE_CODE_TYPE_VBIOS_BASE 0x00
#define NV_BCRT_HASH_INFO_BASE_CODE_TYPE_VBIOS_EXT 0xE0
//
// The VBIOS object comes from walking the PCI expansion code block
// The following structure holds the expansion code format.
//
#define PCI_EXP_ROM_SIGNATURE 0xaa55
#define PCI_EXP_ROM_SIGNATURE_NV 0x4e56 // "VN" in word format
#define PCI_EXP_ROM_SIGNATURE_NV2 0xbb77
#define IS_VALID_PCI_ROM_SIG(sig) ((sig == PCI_EXP_ROM_SIGNATURE) || \
(sig == PCI_EXP_ROM_SIGNATURE_NV) || \
(sig == PCI_EXP_ROM_SIGNATURE_NV2))
#define OFFSETOF_PCI_EXP_ROM_SIG 0x0
#define OFFSETOF_PCI_EXP_ROM_NBSI_DATA_OFFSET 0x16
#define OFFSETOF_PCI_EXP_ROM_PCI_DATA_STRUCT_PTR 0x18
#pragma pack(1)
typedef struct _PCI_EXP_ROM_STANDARD
{
NvU16 sig; // 00h: ROM Signature 0xaa55
NvU8 reserved [0x16]; // 02h: Reserved (processor architecture unique data)
NvU16 pciDataStrucPtr; // 18h: Pointer to PCI Data Structure
NvU32 sizeOfBlock; // 1Ah: <NBSI-specific appendage>
} PCI_EXP_ROM_STANDARD, *PPCI_EXP_ROM_STANDARD;
#pragma pack()
#pragma pack(1)
typedef struct _PCI_EXP_ROM_NBSI
{
NvU16 sig; // 00h: ROM Signature 0xaa55
NvU8 reserved [0x14]; // 02h: Reserved (processor architecture unique data)
NvU16 nbsiDataOffset; // 16h: Offset from header to NBSI image
NvU16 pciDataStrucPtr; // 18h: Pointer to PCI Data Structure
NvU32 sizeOfBlock; // 1Ah: <NBSI-specific appendage>
} PCI_EXP_ROM_NBSI, *PPCI_EXP_ROM_NBSI;
#pragma pack()
typedef union _PCI_EXP_ROM {
PCI_EXP_ROM_STANDARD standard;
PCI_EXP_ROM_NBSI nbsi;
} PCI_EXP_ROM, *PPCI_EXP_ROM;
#define PCI_DATA_STRUCT_SIGNATURE 0x52494350 // "PCIR" in dword format
#define PCI_DATA_STRUCT_SIGNATURE_NV 0x5344504E // "NPDS" in dword format
#define PCI_DATA_STRUCT_SIGNATURE_NV2 0x53494752 // "RGIS" in dword format
#define IS_VALID_PCI_DATA_SIG(sig) ((sig == PCI_DATA_STRUCT_SIGNATURE) || \
(sig == PCI_DATA_STRUCT_SIGNATURE_NV) || \
(sig == PCI_DATA_STRUCT_SIGNATURE_NV2))
#define PCI_LAST_IMAGE NVBIT(7)
#define PCI_ROM_IMAGE_BLOCK_SIZE 512U
#define OFFSETOF_PCI_DATA_STRUCT_SIG 0x0
#define OFFSETOF_PCI_DATA_STRUCT_VENDOR_ID 0x4
#define OFFSETOF_PCI_DATA_STRUCT_LEN 0xa
#define OFFSETOF_PCI_DATA_STRUCT_CLASS_CODE 0xd
#define OFFSETOF_PCI_DATA_STRUCT_CODE_TYPE 0x14
#define OFFSETOF_PCI_DATA_STRUCT_IMAGE_LEN 0x10
#define OFFSETOF_PCI_DATA_STRUCT_LAST_IMAGE 0x15
#pragma pack(1)
typedef struct _PCI_DATA_STRUCT
{
NvU32 sig; // 00h: Signature, the string "PCIR" or NVIDIA's alternate "NPDS"
NvU16 vendorID; // 04h: Vendor Identification
NvU16 deviceID; // 06h: Device Identification
NvU16 deviceListPtr; // 08h: Device List Pointer
NvU16 pciDataStructLen; // 0Ah: PCI Data Structure Length
NvU8 pciDataStructRev; // 0Ch: PCI Data Structure Revision
NvU8 classCode[3]; // 0Dh: Class Code
NvU16 imageLen; // 10h: Image Length (units of 512 bytes)
NvU16 vendorRomRev; // 12h: Revision Level of the Vendor's ROM
NvU8 codeType; // 14h: holds NBSI_OBJ_CODE_TYPE (0x70) and others
NvU8 lastImage; // 15h: Last Image Indicator: bit7=1 is lastImage
NvU16 maxRunTimeImageLen; // 16h: Maximum Run-time Image Length (units of 512 bytes)
} PCI_DATA_STRUCT, *PPCI_DATA_STRUCT;
#pragma pack()
#define NV_PCI_DATA_EXT_SIG 0x4544504E // "NPDE" in dword format
#define NV_PCI_DATA_EXT_REV_10 0x100 // 1.0
#define NV_PCI_DATA_EXT_REV_11 0x101 // 1.1
#define OFFSETOF_PCI_DATA_EXT_STRUCT_SIG 0x0
#define OFFSETOF_PCI_DATA_EXT_STRUCT_LEN 0x6
#define OFFSETOF_PCI_DATA_EXT_STRUCT_REV 0x4
#define OFFSETOF_PCI_DATA_EXT_STRUCT_SUBIMAGE_LEN 0x8
#define OFFSETOF_PCI_DATA_EXT_STRUCT_LAST_IMAGE 0xa
#define OFFSETOF_PCI_DATA_EXT_STRUCT_FLAGS 0xb
#define PCI_DATA_EXT_STRUCT_FLAGS_CHECKSUM_DISABLED 0x04
#pragma pack(1)
typedef struct _NV_PCI_DATA_EXT_STRUCT
{
NvU32 signature; // 00h: Signature, the string "NPDE"
NvU16 nvPciDataExtRev; // 04h: NVIDIA PCI Data Extension Revision
NvU16 nvPciDataExtLen; // 06h: NVIDIA PCI Data Extension Length
NvU16 subimageLen; // 08h: Sub-image Length
NvU8 privLastImage; // 0Ah: Private Last Image Indicator
NvU8 flags; // 0Bh: Private images enabled if bit0=1
} NV_PCI_DATA_EXT_STRUCT, *PNV_PCI_DATA_EXT_STRUCT;
#pragma pack()
#endif // PCIEXPTBL_H

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/*
* SPDX-FileCopyrightText: Copyright (c) 2019-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef VBIOS_H
#define VBIOS_H
#include "gpu/vbios/bios_types.h"
#define FALCON_APPLICATION_INTERFACE_ENTRY_ID_DMEMMAPPER (0x4)
typedef struct
{
NvU8 version;
NvU8 headerSize;
NvU8 entrySize;
NvU8 entryCount;
} __attribute__((packed)) FALCON_APPLICATION_INTERFACE_HEADER_V1;
typedef struct
{
NvU32 id;
NvU32 dmemOffset;
} __attribute__((packed)) FALCON_APPLICATION_INTERFACE_ENTRY_V1;
typedef struct
{
NvU32 signature;
NvU16 version;
NvU16 size;
NvU32 cmd_in_buffer_offset;
NvU32 cmd_in_buffer_size;
NvU32 cmd_out_buffer_offset;
NvU32 cmd_out_buffer_size;
NvU32 nvf_img_data_buffer_offset;
NvU32 nvf_img_data_buffer_size;
NvU32 printfBufferHdr;
NvU32 ucode_build_time_stamp;
NvU32 ucode_signature;
NvU32 init_cmd;
NvU32 ucode_feature;
NvU32 ucode_cmd_mask0;
NvU32 ucode_cmd_mask1;
NvU32 multiTgtTbl;
} __attribute__((packed)) FALCON_APPLICATION_INTERFACE_DMEM_MAPPER_V3;
#define FALCON_APPLICATION_INTERFACE_DMEM_MAPPER_V3_CMD_FRTS (0x15)
#define FALCON_APPLICATION_INTERFACE_DMEM_MAPPER_V3_CMD_SB (0x19)
#define BIT_HEADER_ID 0xB8FF
#define BIT_HEADER_SIGNATURE 0x00544942 // "BIT\0"
#define BIT_HEADER_SIZE_OFFSET 8
struct __attribute__((packed)) BIT_HEADER_V1_00
{
unsigned short Id;
unsigned int Signature;
unsigned short BCD_Version;
unsigned char HeaderSize;
unsigned char TokenSize;
unsigned char TokenEntries;
unsigned char HeaderChksum;
};
#define BIT_HEADER_V1_00_FMT "1w1d1w4b"
typedef struct BIT_HEADER_V1_00 BIT_HEADER_V1_00;
struct __attribute__((packed)) BIT_TOKEN_V1_00
{
unsigned char TokenId;
unsigned char DataVersion;
unsigned short DataSize;
unsigned int DataPtr;
};
#define BIT_TOKEN_V1_00_SIZE_6 6U
#define BIT_TOKEN_V1_00_SIZE_8 8U
#define BIT_TOKEN_V1_00_FMT_SIZE_6 "2b2w"
#define BIT_TOKEN_V1_00_FMT_SIZE_8 "2b1w1d"
typedef struct BIT_TOKEN_V1_00 BIT_TOKEN_V1_00;
#define BIT_TOKEN_BIOSDATA 0x42
// structure for only version info from BIT_DATA_BIOSDATA_V1 and BIT_DATA_BIOSDATA_V2
typedef struct
{
unsigned int Version; // BIOS Binary Version Ex. 5.40.00.01.12 = 0x05400001
unsigned char OemVersion; // OEM Version Number Ex. 5.40.00.01.12 = 0x12
} __attribute__((packed)) BIT_DATA_BIOSDATA_BINVER;
#define BIT_DATA_BIOSDATA_VERSION_1 0x1
#define BIT_DATA_BIOSDATA_VERSION_2 0x2
#define BIT_DATA_BIOSDATA_BINVER_FMT "1d1b"
#define BIT_DATA_BIOSDATA_BINVER_SIZE_5 5
#define BIT_TOKEN_FALCON_DATA 0x70
typedef struct
{
unsigned int FalconUcodeTablePtr;
} __attribute__((packed)) BIT_DATA_FALCON_DATA_V2;
#define BIT_DATA_FALCON_DATA_V2_4_FMT "1d"
#define BIT_DATA_FALCON_DATA_V2_SIZE_4 4
typedef struct
{
unsigned char Version;
unsigned char HeaderSize;
unsigned char EntrySize;
unsigned char EntryCount;
unsigned char DescVersion;
unsigned char DescSize;
} __attribute__((packed)) FALCON_UCODE_TABLE_HDR_V1;
#define FALCON_UCODE_TABLE_HDR_V1_VERSION 1
#define FALCON_UCODE_TABLE_HDR_V1_SIZE_6 6
#define FALCON_UCODE_TABLE_HDR_V1_6_FMT "6b"
typedef struct
{
unsigned char ApplicationID;
unsigned char TargetID;
unsigned int DescPtr;
} __attribute__((packed)) FALCON_UCODE_TABLE_ENTRY_V1;
#define FALCON_UCODE_TABLE_ENTRY_V1_VERSION 1
#define FALCON_UCODE_TABLE_ENTRY_V1_SIZE_6 6
#define FALCON_UCODE_TABLE_ENTRY_V1_6_FMT "2b1d"
#define FALCON_UCODE_ENTRY_APPID_FIRMWARE_SEC_LIC 0x05
#define FALCON_UCODE_ENTRY_APPID_FWSEC_DBG 0x45
#define FALCON_UCODE_ENTRY_APPID_FWSEC_PROD 0x85
#define NV_BIT_FALCON_UCODE_DESC_HEADER_VDESC_FLAGS_VERSION 0:0
#define NV_BIT_FALCON_UCODE_DESC_HEADER_VDESC_FLAGS_VERSION_UNAVAILABLE 0x00
#define NV_BIT_FALCON_UCODE_DESC_HEADER_VDESC_FLAGS_VERSION_AVAILABLE 0x01
#define NV_BIT_FALCON_UCODE_DESC_HEADER_VDESC_FLAGS_RESERVED 1:1
#define NV_BIT_FALCON_UCODE_DESC_HEADER_VDESC_FLAGS_ENCRYPTED 2:2
#define NV_BIT_FALCON_UCODE_DESC_HEADER_VDESC_RESERVED 7:3
#define NV_BIT_FALCON_UCODE_DESC_HEADER_VDESC_VERSION 15:8
#define NV_BIT_FALCON_UCODE_DESC_HEADER_VDESC_VERSION_V1 0x01
#define NV_BIT_FALCON_UCODE_DESC_HEADER_VDESC_VERSION_V2 0x02
#define NV_BIT_FALCON_UCODE_DESC_HEADER_VDESC_VERSION_V3 0x03
#define NV_BIT_FALCON_UCODE_DESC_HEADER_VDESC_VERSION_V4 0x04
#define NV_BIT_FALCON_UCODE_DESC_HEADER_VDESC_SIZE 31:16
typedef struct
{
unsigned int vDesc;
} __attribute__((packed)) FALCON_UCODE_DESC_HEADER;
#define FALCON_UCODE_DESC_HEADER_FORMAT "1d"
typedef struct {
FALCON_UCODE_DESC_HEADER Hdr;
unsigned int StoredSize;
unsigned int PKCDataOffset;
unsigned int InterfaceOffset;
unsigned int IMEMPhysBase;
unsigned int IMEMLoadSize;
unsigned int IMEMVirtBase;
unsigned int DMEMPhysBase;
unsigned int DMEMLoadSize;
unsigned short EngineIdMask;
unsigned char UcodeId;
unsigned char SignatureCount;
unsigned short SignatureVersions;
unsigned short Reserved;
} FALCON_UCODE_DESC_V3;
#define FALCON_UCODE_DESC_V3_SIZE_44 44
#define FALCON_UCODE_DESC_V3_44_FMT "9d1w2b2w"
#define BCRT30_RSA3K_SIG_SIZE 384
typedef struct
{
NvU32 version;
NvU32 size;
NvU64 gfwImageOffset;
NvU32 gfwImageSize;
NvU32 flags;
} __attribute__((packed)) FWSECLIC_READ_VBIOS_DESC;
#define FWSECLIC_READ_VBIOS_STRUCT_FLAGS (2)
typedef struct
{
NvU32 version;
NvU32 size;
NvU32 frtsRegionOffset4K;
NvU32 frtsRegionSize;
NvU32 frtsRegionMediaType;
} __attribute__((packed)) FWSECLIC_FRTS_REGION_DESC;
#define FWSECLIC_FRTS_REGION_MEDIA_FB (2)
#define FWSECLIC_FRTS_REGION_SIZE_1MB_IN_4K (0x100)
typedef struct
{
FWSECLIC_READ_VBIOS_DESC readVbiosDesc;
FWSECLIC_FRTS_REGION_DESC frtsRegionDesc;
} __attribute__((packed)) FWSECLIC_FRTS_CMD;
#endif /* VBIOS_H */