forked from IQ.Lvbs/IQ.Pilot
IQ.Pilot Release Commit @ 0798119
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IQ.Lvbs history cleanup
102
tinygrad_repo/tinygrad/runtime/autogen/am/__init__.py
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102
tinygrad_repo/tinygrad/runtime/autogen/am/__init__.py
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import pathlib, hashlib, re, itertools
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from tinygrad.runtime.autogen import load, root
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__all__ = ["am", "pm4_soc15", "pm4_nv", "sdma_4_0_0", "sdma_5_0_0", "sdma_6_0_0", "smu_13_0_0", "smu_13_0_6", "smu_13_0_12", "smu_14_0_2",
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"fw", "navi_offsets", "vega_offsets", "regs", "soc_9", "soc_11", "soc_12", "pmc"]
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am_src="https://github.com/ROCm/ROCK-Kernel-Driver/archive/33970e1351f5e511029602454979f3de7e22260f.tar.gz"
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rocm_src="https://github.com/ROCm/rocm-systems/archive/cccc350dc620e61ae2554978b62ab3532dc10bd9.tar.gz"
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AMD, AMDINC = "{}/drivers/gpu/drm/amd", "{}/drivers/gpu/drm/amd/include"
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inc, kern_rules = ["-include", "stdint.h"], [(r'le32_to_cpu', ''),]
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fw_src="https://gitlab.com/kernel-firmware/linux-firmware/-/archive/1e2c15348485939baf1b6d1f5a7a3b799d80703d/1e2c15348485939baf1b6d1f5a7a3b799d80703d.tar.gz"
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pmc_src="https://raw.githubusercontent.com/ROCm/rocm-systems/cccc350dc620e61ae2554978b62ab3532dc10bd9/projects/rocprofiler-compute/src/rocprof_compute_soc/profile_configs/counter_defs.yaml"
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reg_files = {
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"gc": [(9,4,3), (11,0,0), (11,0,3), (11,5,0), (12,0,0)],
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"mmhub": [(1,8,0), (3,0,0), (3,0,1), (3,0,2), (3,3,0), (4,1,0)],
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"nbio": [(4,3,0), (7,2,0), (7,7,0), (7,9,0), (7,11,0)], "nbif": [(6,3,1)],
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"mp": [(11,0,0), (13,0,0), (14,0,2)], "hdp": [(4,4,2), (6,0,0), (7,0,0)],
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"osssys": [(4,4,2), (6,0,0), (6,1,0), (7,0,0)], "sdma": [(4,4,2)]
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}
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reg_patterns = {
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"gc": ["GCVM", "GCMC_VM", "CP_(HQD|MQD|MEC|ME_CNTL|PERFMON|RB_WPTR_POLL_CNTL|INT_CNTL|STAT|PFP_PRGRM|ME_PRGRM|COHER_START)", "COMPUTE_",
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"(SQ|GL2C|TCC)_PERFCOUNTER", "SQ_THREAD_TRACE", "SPI_(CONFIG_CNTL|COMPUTE_QUEUE_RESET)", "GRBM", "SH_MEM", "RLC", "TCP", "GB_ADDR_CONFIG",
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"SDMA[01]_(WATCHDOG_CNTL|UTCL1_(CNTL|PAGE)|MCU_CNTL|F32_CNTL|CNTL|QUEUE0_|RLC_CGCG_CTRL)", "SCRATCH_REG[67]"],
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"mmhub": ["MMVM", "MMMC_VM", "MM_ATC_L2_MISC_CG"],
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"nbio": (nbio:=["BIF_BX_PF[01]_GPU_HDP_FLUSH", "BIF_BX_PF0_RSMU", "BIF_BX0_(REMAP_HDP_MEM_FLUSH_CNTL|BIF_DOORBELL_INT_CNTL|PCIE_INDEX2|PCIE_DATA2)",
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"BIFC_(DOORBELL_ACCESS_EN_PF|GFX_INT_MONITOR_MASK)", "XCC_DOORBELL_FENCE", "DOORBELL0_CTRL_ENTRY", "GDC_S2A0_S2A_DOORBELL_ENTRY",
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"S2A_DOORBELL_ENTRY", "RCC_DEV0_EPF0_RCC_DOORBELL_APER_EN", "RCC_DEV0_EPF2_STRAP2"]),
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"nbif": nbio,
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"mp": ["MP([01]|ASP)_SMN_C2PMSG"], "hdp": ["HDP_MEM_POWER_CTRL"], "oss": ["IH_"], "sdma": ["SDMA_GFX", "SDMA_CNTL"]
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}
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soc_patterns = ["SQ_TT", "VGT_EVENT_TYPE", "CS", "MTYPE", "SH"]
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def __getattr__(nm):
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match nm:
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case "am": return load("am/am", [root/f"extra/amdpci/headers/{s}.h" for s in ["v11_structs", "v12_structs", "amdgpu_vm",
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"discovery", "amdgpu_ucode", "psp_gfx_if", "amdgpu_psp", "amdgpu_irq", "amdgpu_doorbell"]] + [f"{AMD}/amdkfd/soc15_int.h"] + \
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[f"{AMDINC}/ivsrcid/{s}.h" for s in [f"gfx/irqsrcs_gfx_{x}_0" for x in ('9','11_0','12_0')] + [f"sdma0/irqsrcs_sdma0_{x}_0" for x in (4,5)]] + \
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[f"{AMDINC}/{s}.h" for s in ["v9_structs", "soc15_ih_clientid"]], args=inc, srcs=am_src, rules=kern_rules)
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case "pm4_soc15": return load("am/pm4_soc15", [f"{AMD}/amdkfd/kfd_pm4_headers_ai.h", f"{AMD}/amdgpu/soc15d.h"], srcs=am_src)
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case "pm4_nv": return load("am/pm4_nv", [f"{AMD}/amdkfd/kfd_pm4_headers_ai.h", f"{AMD}/amdgpu/nvd.h"], srcs=am_src)
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case "sdma_4_0_0": return load("am/sdma_4_0_0", [root/"extra/hip_gpu_driver/sdma_registers.h", f"{AMD}/amdgpu/vega10_sdma_pkt_open.h"],
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args=["-I/opt/rocm/include", "-x", "c++"], srcs=am_src)
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case "sdma_5_0_0": return load("am/sdma_5_0_0", [root/"extra/hip_gpu_driver/sdma_registers.h", f"{AMD}/amdgpu/navi10_sdma_pkt_open.h"],
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args=["-I/opt/rocm/include", "-x", "c++"], srcs=am_src)
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case "sdma_6_0_0": return load("am/sdma_6_0_0", [root/"extra/hip_gpu_driver/sdma_registers.h", f"{AMD}/amdgpu/sdma_v6_0_0_pkt_open.h"],
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args=["-I/opt/rocm/include", "-x", "c++"], srcs=am_src)
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case "smu_13_0_0": return load("am/smu_13_0_0", [f"{AMD}/pm/swsmu/inc/pmfw_if/{s}.h" for s in ["smu_v13_0_0_ppsmc","smu13_driver_if_v13_0_0"]]
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+[root/"extra/amdpci/headers/amdgpu_smu.h"], args=inc, srcs=am_src)
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case "smu_13_0_6": return load("am/smu_13_0_6", [f"{AMD}/pm/swsmu/inc/pmfw_if/{s}.h" for s in ["smu_v13_0_6_ppsmc","smu_v13_0_6_pmfw", \
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"smu13_driver_if_v13_0_6"]] +[root/"extra/amdpci/headers/amdgpu_smu.h"], args=inc, srcs=am_src)
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case "smu_13_0_12": return load("am/smu_13_0_12", [f"{AMD}/pm/swsmu/inc/pmfw_if/{s}.h" for s in ["smu_v13_0_12_ppsmc","smu_v13_0_12_pmfw",
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"smu13_driver_if_v13_0_6"]] +[root/"extra/amdpci/headers/amdgpu_smu.h"], args=inc, srcs=am_src)
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case "smu_14_0_2": return load("am/smu_14_0_2", [f"{AMD}/pm/swsmu/inc/pmfw_if/{s}.h" for s in ["smu_v14_0_0_pmfw", "smu_v14_0_2_ppsmc",
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"smu14_driver_if_v14_0"]]+[root/"extra/amdpci/headers/amdgpu_smu.h"], args=inc, srcs=am_src)
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# firmware hashes
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case "fw":
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def genfw(name, files, **kwargs): return "\n".join(["hashes = {"] + [f" {p.name!r}: {hashlib.sha256(p.read_bytes()).hexdigest()!r},"
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for f in files if (p:=pathlib.Path(f)).is_file()] + ["}"])
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return load("am/fw", ["{}/amdgpu/psp_*_sos.bin", "{}/amdgpu/smu_*.bin", "{}/amdgpu/sdma_*.bin"] +
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[f"{{}}/amdgpu/gc_*_{x}.bin" for x in ["pfp", "me", "mec", "imu", "rlc"]], srcs=fw_src, gen=genfw)
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case "navi_offsets": return load("am/navi_offsets", [f"{AMD}/include/sienna_cichlid_ip_offset.h"], srcs=am_src)
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case "vega_offsets": return load("am/vega_offsets", [f"{AMD}/include/vega20_ip_offset.h"], srcs=am_src)
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case "regs":
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def genreg(_, files, **kwargs):
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out = ["__all__ = " + repr([file.split('/')[-1] for file in files])]
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for file, nm in [(file.replace("mp_11_0_0", "mp_11_0"), file.split('/')[-1]) for file in files]:
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pats = reg_patterns[prefix := {"osssys": "oss"}.get(x:=nm.split("_", 1)[0], x)]
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def split_name(name): return name[:(pos:=next((i for i,c in enumerate(name) if c.isupper()), len(name)))], name[pos:]
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# handle CDNA's different register names
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def normalize(reg):
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return s[0] + prefix.upper()[:2] + s[1] if prefix in ("gc", "mmhub") and (s:=split_name(reg))[1].startswith(("VM_", "MC_VM_")) else reg
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def extract(lines, pat): return ((normalize(m.group(1)), int(m.group(2), 0)) for l in lines if (m:=re.match(pat, l)))
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offset, sh_mask = pathlib.Path(f"{file}_offset.h").read_text().splitlines(), pathlib.Path(f"{file}_sh_mask.h").read_text().splitlines()
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defs = {k:v for k,v in extract(offset, r'#define\s+((?:mm|reg)\S+)\s+(0x[\da-fA-F]+|\d+)') if any(re.match("(mm|reg)"+p, k) for p in pats)}
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fields = {reg: {name.split('__')[1].lower(): ((mask & -mask).bit_length() - 1, mask.bit_length() - 1) for name, mask in fs}
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for reg, fs in itertools.groupby(extract(sh_mask, r'#define\s+(\S+)_MASK\s+(0x[\da-fA-F]+|\d+)'), lambda x: x[0].split('__')[0])}
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regs = {reg: (off, defs[f"{reg}_BASE_IDX"], fields.get(split_name(reg)[1], {})) for reg,off in defs.items() if f"{reg}_BASE_IDX" in defs}
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print(f"defined {len(regs)} registers for {nm}")
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out.extend([f"{nm} = {{"] + [f" {k!r}: {v!r}," for k,v in regs.items()] + ["}"])
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return "\n".join(out)
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return load("am/regs", [AMDINC + "/asic_reg/" + {"osssys":"oss"}.get(pre, pre) + f"/{pre}_{'_'.join(map(str, ver))}"
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for pre in reg_files for ver in sorted(reg_files[pre])], srcs=am_src, gen=genreg)
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case "soc_9" | "soc_11" | "soc_12":
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return load(f"am/{nm}", ["{}/projects/aqlprofile/linux/" + {9: "vega10", 11: "soc21", 12: "soc24"}[int(nm.split('_')[1])] + "_enum.h"],
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srcs=rocm_src, patterns=soc_patterns, macros=False)
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case "pmc":
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def genpmc(_, files, **kwargs):
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from yaml import safe_load # type: ignore
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with open(files[0], "r") as f: data = safe_load(f)
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out = ["counters = {"]
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for counter in [c for c in data['rocprofiler-sdk']['counters'] if any('block' in d for d in c['definitions'])]:
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out.extend([f" {counter['name']!r}: {{",
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*[f" {a!r}: ({d['block']!r}, {d['event']})," for d in counter['definitions'] for a in d['architectures']], " },"])
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return "\n".join(out + ["}"])
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return load("am/pmc", ["{}/counter_defs.yaml"], srcs=pmc_src, gen=genpmc)
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case _: raise AttributeError(f"no such autogen: {nm}")
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4468
tinygrad_repo/tinygrad/runtime/autogen/am/am.py
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4468
tinygrad_repo/tinygrad/runtime/autogen/am/am.py
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File diff suppressed because one or more lines are too long
106
tinygrad_repo/tinygrad/runtime/autogen/am/fw.py
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106
tinygrad_repo/tinygrad/runtime/autogen/am/fw.py
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hashes = {
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'psp_13_0_0_sos.bin': 'b5592f46885585b935e013f46c949db8ff2f15c0b346caf70e7fcd2776623d13',
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'psp_13_0_10_sos.bin': '0bcaaad9cd8578d3841ae69155a6bd4fc3ceae8f4fb5a6ba4f576e7ace94d1d9',
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'psp_13_0_12_sos.bin': '89da90bf4286b38678b1fd175c78462a426afa3d258d15872cd14072d7098b9b',
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'psp_13_0_14_sos.bin': 'a4f0d5f76d27b77409ec0b71d7cc6a848ddfd29f8c84f3003edf74ad3999fb7d',
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'psp_13_0_6_sos.bin': '27657daa0f91ad8095d3610224a7de748b8b348a4cb211ecb5fccabe47369716',
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'psp_13_0_7_sos.bin': 'ef1af0ecea38abbac6f85cce71789f19848c498d0cb8ef13748dab2d65b23c31',
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'psp_14_0_2_sos.bin': '7b538448b57d4f9dd06b2eea90d4f86a16e65e3027cdecee8db71c2c5f1fa243',
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'psp_14_0_3_sos.bin': '23bea01a0c6f36d00759d0765d46cb4cb4aa87398b2fbccacbf547a890c0bf51',
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'smu_13_0_0.bin': '2ffac37fd8534965eeba19755db0e5ec80278213487dc4af0fbc8453befb64b1',
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'smu_13_0_0_kicker.bin': '7f83656a2a89b7fce1c8a85e96d91cd8265a91fe883a7027f1a0ed18ced501de',
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'smu_13_0_10.bin': 'daedb9cbdf48942be7ffe00d31b7c16bb36e11ff5a9d7495f218e95c07717b71',
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'smu_13_0_14.bin': 'a4f36de75fdcecd8000246762e027b4be489b6787afea57675225b0b39d35625',
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'smu_13_0_6.bin': 'ad7232264e8c57c2094244fbdd5a55d7a4575ffe9b44d229884bc0b6a44fb0b1',
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'smu_13_0_7.bin': 'ccecc0fd0196b9613c920a51c2fd9436e739ff19dda5bdf74d97562387231732',
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'smu_14_0_2.bin': '6951995d1d606f4dc60c895f19d34ed18aa40e62129f83d8510c45e8aa9ae2fc',
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'smu_14_0_3.bin': 'df230947ddb7bbfd6e77d1280001db886e69adf2b2a448b47fa668a48bc0009f',
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'smu_14_0_3_kicker.bin': '8ddc1da5b4e1619796c2cc81f19f388a35bf7d78bfe476cee559625589cb4dc7',
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'sdma_4_4_2.bin': '456061b814268425843537da6f2191c8861d4e1a18d4c5d90c44ea6be18c78ff',
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'sdma_4_4_4.bin': 'af47a2940e72b932d3e3a7e8f34f7a182624e5e433f7c56dff939ca5549cd33a',
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'sdma_4_4_5.bin': '6127baabea3de7b18db3868c983b02c0fbf2cd75997f7f11241a5b1be27e5134',
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'sdma_5_2_6.bin': '3a163db00eb7e4752be8adbd61cf7dd8f08d924e59a6f798ced7dfcd89f340ed',
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'sdma_5_2_7.bin': '16fe80dc866b323e15a06f51646ef0f036878ad34da66921fcdb8167207d6b2b',
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'sdma_6_0_0.bin': '0f3da6b211f376356335b41be07149f650c10cfa4e23f7e25d53836006ed11f5',
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'sdma_6_0_1.bin': 'ff565d3c215a30737560d4e3df6fc2c637738407e91d212fb200fdfb185b6744',
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||||
'sdma_6_0_2.bin': '398380184bb69113ef4c8964a3b55f6184deb0c1ffd96c9683490a3eec3ba8f3',
|
||||
'sdma_6_0_3.bin': '0e8a83513087db865ba926f8b65cfb003fd41098f707e178d7a7ae2941fed0b1',
|
||||
'sdma_6_1_0.bin': '22e55d0ad5f0247a7f0fffc67cfd3161b39f24ad6062ff3c91ec7ff38bd7e1e1',
|
||||
'sdma_6_1_1.bin': '74533a581b8e3e2743b3c9c803d0666405e80898c4a630acefed82cb6b516ba2',
|
||||
'sdma_6_1_2.bin': '4fe04b0286ec739b0414e8aee17e62e85e691f0246d1d9b56bc18a1219072314',
|
||||
'sdma_6_1_3.bin': '35c9ed7e3a237c0d4a83b4975c63b62488f72aeafbb648342f384618e103f66b',
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||||
'sdma_7_0_0.bin': 'beaafb53993a106edd392392d5896245ae2a957c6d0f495d0002eec72ad8ad38',
|
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'sdma_7_0_1.bin': '73c29e1c1714ebc95d2221ba56e187910902891593010653bf9518937e414a59',
|
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'gc_10_3_6_pfp.bin': '793d678427887a0e724c79e356440aec33e6d1301f2a4e63543500249ebec064',
|
||||
'gc_10_3_7_pfp.bin': '3ae29aac3f424f7de97f82ce7158beba69509afb2dcbf1a428dc315df474a524',
|
||||
'gc_11_0_0_pfp.bin': 'e175cb0f580a38c961a6f7366142c08e413995f57f78f39795368b15442df8a3',
|
||||
'gc_11_0_1_pfp.bin': 'f5bf21dfbd9e72a30b4caf4704282c27854710c1b7c4affbb2a19530466b12a8',
|
||||
'gc_11_0_2_pfp.bin': '001c4dec1119e29314d725cc1280fc4f0cd9cabdf61ea5ee2260cfd4e62ec141',
|
||||
'gc_11_0_3_pfp.bin': '0488034c85be97125e39e860308d33c3f76a01df8250092a32d4d55acb2526fd',
|
||||
'gc_11_0_4_pfp.bin': '5ae8b7bb6316f87ae8b978354c088e3bd8c890959382d72886377cda25b1ffd1',
|
||||
'gc_11_5_0_pfp.bin': '0124f540871a7759fa8aaae046d458dfb34aeea12a1183ff962c3f1a33067d5a',
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||||
'gc_11_5_1_pfp.bin': '7794ea46d0d3cf9cb3f7938affbdf09dd7a9970340da5cd02b774cb393436d24',
|
||||
'gc_11_5_2_pfp.bin': '55e64741de28c506524959f7f696713a72aafe46f49ccd827781d67a9475b386',
|
||||
'gc_11_5_3_pfp.bin': 'ce805040fb347fddbc89b2715e66b446865dda9e2056a9b233269b72bc09c387',
|
||||
'gc_12_0_0_pfp.bin': '16bfd64c10fe73b5e760055069a60e5841dba16c0ed4edb56c20d675e23901f6',
|
||||
'gc_12_0_1_pfp.bin': '49efb319305c5fffd90ac1eef7d7a0bdec72998ecb5cf4526996311788a53dc3',
|
||||
'gc_10_3_6_me.bin': '141b59faad3f2f1be16a2178833b7ca8e97519e1e844c8fda6689572c3767902',
|
||||
'gc_10_3_7_me.bin': '9eb0b56e9bcc9dad5d53437b162226fcb37e5df102832260f1232832f3658edf',
|
||||
'gc_11_0_0_me.bin': 'f8fba8a63dd4293b8fc1e4aab78b6fac630e575d1d62838c7996d9210f82aea1',
|
||||
'gc_11_0_1_me.bin': '5030040b00955de94876341ec64ea43b96640413d7a03dc460a83c8386bf76e0',
|
||||
'gc_11_0_2_me.bin': '0f21fd43f1dfbc6ccced9a2b3774de25c993c61a689aabab8b45333937b7945e',
|
||||
'gc_11_0_3_me.bin': '3acb5061dba342ade81d329d1932f19ec01f0c5bf44e6e3568008a951a351bac',
|
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'gc_11_0_4_me.bin': 'e4f1f6abcd213d54ad9e885d9f550083b0e2f67d983566015e8a53981e1cb155',
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||||
'gc_11_5_0_me.bin': '8f906b64d0a29503daa662c93ec44d076fcac11b78f70cd50ce0af2b500a05a6',
|
||||
'gc_11_5_1_me.bin': '7e42602bcbaf1e511f8b4f6ed2246844ad1f6e351ce2b663d89062a7be263663',
|
||||
'gc_11_5_2_me.bin': 'aae26255d8efff81e0e3bbcb727efb8b837d8e25fe85c708545f5328f1077b50',
|
||||
'gc_11_5_3_me.bin': '93cd588348b16fe432609fe8da6e6b5da0a52da5c5884882aecf7b1001f72700',
|
||||
'gc_12_0_0_me.bin': 'd7eba5197f2580f32b8256b1d9cb68e723e9e644293a34446a7913e3c093cba5',
|
||||
'gc_12_0_1_me.bin': '365e7f193b39cbb10d3af44905fefaca0e9844721801755276baebac7b19c1ea',
|
||||
'gc_10_3_6_mec.bin': '247943415658159704a21f670dd7b3e7cb2d2fc0c17b000a5098715979c8d95e',
|
||||
'gc_10_3_7_mec.bin': 'ee58a523375bcf5b89400b32b801f95e182b632a26bce4f2bed5c07928d486dc',
|
||||
'gc_11_0_0_mec.bin': '801a09c9bf06188260db9b51ad8f978f15d84c72ca91b90643a2ef8af4074776',
|
||||
'gc_11_0_1_mec.bin': '6afadcb7504bb11bcc9d4a205cdf73f7934a615e28f178fcf7285971df2ccd05',
|
||||
'gc_11_0_2_mec.bin': '0da0edee28c73a6fa1191f77853d380ec2503cbf43e0aaae4617f32f1f8a48fa',
|
||||
'gc_11_0_3_mec.bin': '323cfa6658b6b5169830f852e2ff0552acae8dfb9e44b42c63de7b2900d3fd9e',
|
||||
'gc_11_0_4_mec.bin': '5d89cf6b60354f3746c2cbd1ff0cb1a741556ca20d72745242cb69b553d0985c',
|
||||
'gc_11_5_0_mec.bin': 'a01c324ab14ec89792449a621a541829b9af26865019027a411a14b910145dfa',
|
||||
'gc_11_5_1_mec.bin': 'eab05719371caa68df09d4f7574e3958a3c4f5044ab3c7b0d2b214add0c6d1c4',
|
||||
'gc_11_5_2_mec.bin': 'a374b2335802e24f8b9a3ce40000a1d37a52a14eb87099bebcc6680c27cc93e5',
|
||||
'gc_11_5_3_mec.bin': '165025437cba80dd32c19ebbc83b756fa7adac7053ff7780ba4aa2f8089c6a3f',
|
||||
'gc_12_0_0_mec.bin': '1931593440b8f9423580d9e2cdc5b34e7c682cdffe1ca4b74b0c2f6a0420236d',
|
||||
'gc_12_0_1_mec.bin': 'f57541688a5108730bf210663f1137ffc2121f3acfe614a6de09ec1982c69a2f',
|
||||
'gc_9_4_3_mec.bin': '3159176e72301fb88dc416721fb3d0ab82ece484cf93a43c3f37430c7e6673a1',
|
||||
'gc_9_4_3_sjt_mec.bin': 'd19468dbb47849640bd0e6cdc8d7e25a3c8442c7ca2ca81357702e0d6baab50f',
|
||||
'gc_9_4_4_mec.bin': '5004f73e43db2dd45e77d65942e33d4a69e7157618cfd23944c30f801c77a0f3',
|
||||
'gc_9_4_4_sjt_mec.bin': '627a9e98102e70fe3bf0947eb764187f29f5e775d1130c7310e0ba5fc0502dbe',
|
||||
'gc_9_5_0_mec.bin': 'c5eca4311a6f6e8f81cf41c2c46941d5dcf90789ee8326901da2dfc86ac14c31',
|
||||
'gc_9_5_0_sjt_mec.bin': 'f162e509379288e3f3b1eead541b315c2262d625d433287ecd34ca185614d312',
|
||||
'gc_11_0_0_imu.bin': 'b4f8fc056b45709a6abf48e7885fb1b4ab8d3cc092cbfa2c554a78564a6403bc',
|
||||
'gc_11_0_1_imu.bin': 'ac71f4eec713fc35b4a1fe27531e3eb04edd81eeac2cef64df01ac50d8510805',
|
||||
'gc_11_0_2_imu.bin': '9befca62b0b0cfd252c3df4a9edca295526f4d43821cd99a6326454995a6ca2d',
|
||||
'gc_11_0_3_imu.bin': 'beaf704d5acdf4623456b0d0cbcea8b8e428058340cd922a259a9045f5c457a3',
|
||||
'gc_11_0_4_imu.bin': 'ac71f4eec713fc35b4a1fe27531e3eb04edd81eeac2cef64df01ac50d8510805',
|
||||
'gc_11_5_0_imu.bin': '469add57cafead90ab1953d6039cd8e39bc50dfd78aa5fd78f019ccf66a0af41',
|
||||
'gc_11_5_1_imu.bin': '0aaca8a01b2237fca1b3c0cd082b5e12a271df334ff368bbf8e2be17f192b785',
|
||||
'gc_11_5_2_imu.bin': 'fb684842839c61a0706a19df8e15eb8afc17e20c14267eb71e7d7d824c180acf',
|
||||
'gc_11_5_3_imu.bin': 'fb684842839c61a0706a19df8e15eb8afc17e20c14267eb71e7d7d824c180acf',
|
||||
'gc_12_0_0_imu.bin': 'aa15e5b3156bffc45e0c50bccbcd364fbd3f958531b695b7487a803d780b8328',
|
||||
'gc_12_0_1_imu.bin': 'b3b301fb636efc77b63ce4d2ced0f90c851d03c19681852faa45598e6f5773fd',
|
||||
'gc_10_3_6_rlc.bin': 'acfbac75c0dcfbfe40e222640ef17eb3dc8d206d30bc3863f275f2dd1cb132a5',
|
||||
'gc_10_3_7_rlc.bin': 'a02585ebe3b36d942e883057119572d9497600c52fc65b8a523487eb65d874f2',
|
||||
'gc_11_0_0_rlc.bin': 'dabd49039772d02f5fd5e48dc21d35ad52a6b1283b470dabca86ca159c4c7c8e',
|
||||
'gc_11_0_1_rlc.bin': '86145719a58e9428562930c6b5ee3b6ced4701d34a80d0b4d84d6026c93134f2',
|
||||
'gc_11_0_2_rlc.bin': 'b43eb2fd0600f50a1a5796bc9983d6b39b5c20960234920f5e89cb362193e0b8',
|
||||
'gc_11_0_3_rlc.bin': '29b0b456f5b53076ddffa6f09de3bb697219e8e7b33504bf6c197e8b858426dc',
|
||||
'gc_11_0_4_rlc.bin': '823573078b608108fbe4dd8176c396ec582632913db9c59a512d82b068f8eba0',
|
||||
'gc_11_5_0_rlc.bin': '68cd85567f4f2f8d6b80db294988806d956bf826979c3597daccb71c7ee6aadd',
|
||||
'gc_11_5_1_rlc.bin': '92731ecabbeb77865fb71787b4268dc738a58779f1190bdc2056482cb88a08f6',
|
||||
'gc_11_5_2_rlc.bin': 'ef3a9209d3eccfbe18fce9e972c146ac283719798bb788096c176b796dc9aee5',
|
||||
'gc_11_5_3_rlc.bin': '10a68940c6258d5818d9c05fd98eb0ccc8d5aee99b2769fbad30e5abd0d9327e',
|
||||
'gc_12_0_0_rlc.bin': '6436b582734a413456fff3d3c7195e71cc9e78a7ed31ee21c83ffd6fae1ad186',
|
||||
'gc_12_0_1_rlc.bin': '6ba4459532246a5c415d3cb33c9b1248294e48f67b827e2accb292a8d1a5c0ec',
|
||||
'gc_9_4_3_rlc.bin': '5345d388712d547b0ae16f199ad5ccadb65643584b3efa7817049ddeb3fdcd12',
|
||||
'gc_9_4_4_rlc.bin': 'e0c3585c72f8136670ca63e607fba32c1ae4948f493f13e33fc4d466bd6318a8',
|
||||
'gc_9_5_0_rlc.bin': '9b1268f5751153fe57f527c9acb417bfa53ed42c9bc083c9d3da2ba61fe5fdc4',
|
||||
}
|
||||
823
tinygrad_repo/tinygrad/runtime/autogen/am/navi_offsets.py
Normal file
823
tinygrad_repo/tinygrad/runtime/autogen/am/navi_offsets.py
Normal file
@@ -0,0 +1,823 @@
|
||||
# mypy: disable-error-code="empty-body"
|
||||
from __future__ import annotations
|
||||
import ctypes
|
||||
from typing import Literal, TypeAlias
|
||||
from tinygrad.runtime.support.c import _IO, _IOW, _IOR, _IOWR
|
||||
from tinygrad.runtime.support import c
|
||||
@c.record
|
||||
class struct_IP_BASE_INSTANCE(c.Struct):
|
||||
SIZE = 20
|
||||
segment: c.Array[ctypes.c_uint32, Literal[5]]
|
||||
struct_IP_BASE_INSTANCE.register_fields([('segment', c.Array[ctypes.c_uint32, Literal[5]], 0)])
|
||||
@c.record
|
||||
class struct_IP_BASE(c.Struct):
|
||||
SIZE = 140
|
||||
instance: c.Array[struct_IP_BASE_INSTANCE, Literal[7]]
|
||||
struct_IP_BASE.register_fields([('instance', c.Array[struct_IP_BASE_INSTANCE, Literal[7]], 0)])
|
||||
MAX_INSTANCE = 7
|
||||
MAX_SEGMENT = 5
|
||||
ATHUB_BASE__INST0_SEG0 = 0x00000C00
|
||||
ATHUB_BASE__INST0_SEG1 = 0x02408C00
|
||||
ATHUB_BASE__INST0_SEG2 = 0
|
||||
ATHUB_BASE__INST0_SEG3 = 0
|
||||
ATHUB_BASE__INST0_SEG4 = 0
|
||||
ATHUB_BASE__INST1_SEG0 = 0
|
||||
ATHUB_BASE__INST1_SEG1 = 0
|
||||
ATHUB_BASE__INST1_SEG2 = 0
|
||||
ATHUB_BASE__INST1_SEG3 = 0
|
||||
ATHUB_BASE__INST1_SEG4 = 0
|
||||
ATHUB_BASE__INST2_SEG0 = 0
|
||||
ATHUB_BASE__INST2_SEG1 = 0
|
||||
ATHUB_BASE__INST2_SEG2 = 0
|
||||
ATHUB_BASE__INST2_SEG3 = 0
|
||||
ATHUB_BASE__INST2_SEG4 = 0
|
||||
ATHUB_BASE__INST3_SEG0 = 0
|
||||
ATHUB_BASE__INST3_SEG1 = 0
|
||||
ATHUB_BASE__INST3_SEG2 = 0
|
||||
ATHUB_BASE__INST3_SEG3 = 0
|
||||
ATHUB_BASE__INST3_SEG4 = 0
|
||||
ATHUB_BASE__INST4_SEG0 = 0
|
||||
ATHUB_BASE__INST4_SEG1 = 0
|
||||
ATHUB_BASE__INST4_SEG2 = 0
|
||||
ATHUB_BASE__INST4_SEG3 = 0
|
||||
ATHUB_BASE__INST4_SEG4 = 0
|
||||
ATHUB_BASE__INST5_SEG0 = 0
|
||||
ATHUB_BASE__INST5_SEG1 = 0
|
||||
ATHUB_BASE__INST5_SEG2 = 0
|
||||
ATHUB_BASE__INST5_SEG3 = 0
|
||||
ATHUB_BASE__INST5_SEG4 = 0
|
||||
ATHUB_BASE__INST6_SEG0 = 0
|
||||
ATHUB_BASE__INST6_SEG1 = 0
|
||||
ATHUB_BASE__INST6_SEG2 = 0
|
||||
ATHUB_BASE__INST6_SEG3 = 0
|
||||
ATHUB_BASE__INST6_SEG4 = 0
|
||||
CLK_BASE__INST0_SEG0 = 0x00016C00
|
||||
CLK_BASE__INST0_SEG1 = 0x02401800
|
||||
CLK_BASE__INST0_SEG2 = 0
|
||||
CLK_BASE__INST0_SEG3 = 0
|
||||
CLK_BASE__INST0_SEG4 = 0
|
||||
CLK_BASE__INST1_SEG0 = 0x00016E00
|
||||
CLK_BASE__INST1_SEG1 = 0x02401C00
|
||||
CLK_BASE__INST1_SEG2 = 0
|
||||
CLK_BASE__INST1_SEG3 = 0
|
||||
CLK_BASE__INST1_SEG4 = 0
|
||||
CLK_BASE__INST2_SEG0 = 0x00017000
|
||||
CLK_BASE__INST2_SEG1 = 0x02402000
|
||||
CLK_BASE__INST2_SEG2 = 0
|
||||
CLK_BASE__INST2_SEG3 = 0
|
||||
CLK_BASE__INST2_SEG4 = 0
|
||||
CLK_BASE__INST3_SEG0 = 0x00017200
|
||||
CLK_BASE__INST3_SEG1 = 0x02402400
|
||||
CLK_BASE__INST3_SEG2 = 0
|
||||
CLK_BASE__INST3_SEG3 = 0
|
||||
CLK_BASE__INST3_SEG4 = 0
|
||||
CLK_BASE__INST4_SEG0 = 0x0001B000
|
||||
CLK_BASE__INST4_SEG1 = 0x0242D800
|
||||
CLK_BASE__INST4_SEG2 = 0
|
||||
CLK_BASE__INST4_SEG3 = 0
|
||||
CLK_BASE__INST4_SEG4 = 0
|
||||
CLK_BASE__INST5_SEG0 = 0x0001B200
|
||||
CLK_BASE__INST5_SEG1 = 0x0242DC00
|
||||
CLK_BASE__INST5_SEG2 = 0
|
||||
CLK_BASE__INST5_SEG3 = 0
|
||||
CLK_BASE__INST5_SEG4 = 0
|
||||
CLK_BASE__INST6_SEG0 = 0x0001B400
|
||||
CLK_BASE__INST6_SEG1 = 0x0242E000
|
||||
CLK_BASE__INST6_SEG2 = 0
|
||||
CLK_BASE__INST6_SEG3 = 0
|
||||
CLK_BASE__INST6_SEG4 = 0
|
||||
DF_BASE__INST0_SEG0 = 0x00007000
|
||||
DF_BASE__INST0_SEG1 = 0x0240B800
|
||||
DF_BASE__INST0_SEG2 = 0
|
||||
DF_BASE__INST0_SEG3 = 0
|
||||
DF_BASE__INST0_SEG4 = 0
|
||||
DF_BASE__INST1_SEG0 = 0
|
||||
DF_BASE__INST1_SEG1 = 0
|
||||
DF_BASE__INST1_SEG2 = 0
|
||||
DF_BASE__INST1_SEG3 = 0
|
||||
DF_BASE__INST1_SEG4 = 0
|
||||
DF_BASE__INST2_SEG0 = 0
|
||||
DF_BASE__INST2_SEG1 = 0
|
||||
DF_BASE__INST2_SEG2 = 0
|
||||
DF_BASE__INST2_SEG3 = 0
|
||||
DF_BASE__INST2_SEG4 = 0
|
||||
DF_BASE__INST3_SEG0 = 0
|
||||
DF_BASE__INST3_SEG1 = 0
|
||||
DF_BASE__INST3_SEG2 = 0
|
||||
DF_BASE__INST3_SEG3 = 0
|
||||
DF_BASE__INST3_SEG4 = 0
|
||||
DF_BASE__INST4_SEG0 = 0
|
||||
DF_BASE__INST4_SEG1 = 0
|
||||
DF_BASE__INST4_SEG2 = 0
|
||||
DF_BASE__INST4_SEG3 = 0
|
||||
DF_BASE__INST4_SEG4 = 0
|
||||
DF_BASE__INST5_SEG0 = 0
|
||||
DF_BASE__INST5_SEG1 = 0
|
||||
DF_BASE__INST5_SEG2 = 0
|
||||
DF_BASE__INST5_SEG3 = 0
|
||||
DF_BASE__INST5_SEG4 = 0
|
||||
DF_BASE__INST6_SEG0 = 0
|
||||
DF_BASE__INST6_SEG1 = 0
|
||||
DF_BASE__INST6_SEG2 = 0
|
||||
DF_BASE__INST6_SEG3 = 0
|
||||
DF_BASE__INST6_SEG4 = 0
|
||||
DIO_BASE__INST0_SEG0 = 0x02404000
|
||||
DIO_BASE__INST0_SEG1 = 0
|
||||
DIO_BASE__INST0_SEG2 = 0
|
||||
DIO_BASE__INST0_SEG3 = 0
|
||||
DIO_BASE__INST0_SEG4 = 0
|
||||
DIO_BASE__INST1_SEG0 = 0
|
||||
DIO_BASE__INST1_SEG1 = 0
|
||||
DIO_BASE__INST1_SEG2 = 0
|
||||
DIO_BASE__INST1_SEG3 = 0
|
||||
DIO_BASE__INST1_SEG4 = 0
|
||||
DIO_BASE__INST2_SEG0 = 0
|
||||
DIO_BASE__INST2_SEG1 = 0
|
||||
DIO_BASE__INST2_SEG2 = 0
|
||||
DIO_BASE__INST2_SEG3 = 0
|
||||
DIO_BASE__INST2_SEG4 = 0
|
||||
DIO_BASE__INST3_SEG0 = 0
|
||||
DIO_BASE__INST3_SEG1 = 0
|
||||
DIO_BASE__INST3_SEG2 = 0
|
||||
DIO_BASE__INST3_SEG3 = 0
|
||||
DIO_BASE__INST3_SEG4 = 0
|
||||
DIO_BASE__INST4_SEG0 = 0
|
||||
DIO_BASE__INST4_SEG1 = 0
|
||||
DIO_BASE__INST4_SEG2 = 0
|
||||
DIO_BASE__INST4_SEG3 = 0
|
||||
DIO_BASE__INST4_SEG4 = 0
|
||||
DIO_BASE__INST5_SEG0 = 0
|
||||
DIO_BASE__INST5_SEG1 = 0
|
||||
DIO_BASE__INST5_SEG2 = 0
|
||||
DIO_BASE__INST5_SEG3 = 0
|
||||
DIO_BASE__INST5_SEG4 = 0
|
||||
DIO_BASE__INST6_SEG0 = 0
|
||||
DIO_BASE__INST6_SEG1 = 0
|
||||
DIO_BASE__INST6_SEG2 = 0
|
||||
DIO_BASE__INST6_SEG3 = 0
|
||||
DIO_BASE__INST6_SEG4 = 0
|
||||
DCN_BASE__INST0_SEG0 = 0x00000012
|
||||
DCN_BASE__INST0_SEG1 = 0x000000C0
|
||||
DCN_BASE__INST0_SEG2 = 0x000034C0
|
||||
DCN_BASE__INST0_SEG3 = 0x00009000
|
||||
DCN_BASE__INST0_SEG4 = 0x02403C00
|
||||
DCN_BASE__INST1_SEG0 = 0
|
||||
DCN_BASE__INST1_SEG1 = 0
|
||||
DCN_BASE__INST1_SEG2 = 0
|
||||
DCN_BASE__INST1_SEG3 = 0
|
||||
DCN_BASE__INST1_SEG4 = 0
|
||||
DCN_BASE__INST2_SEG0 = 0
|
||||
DCN_BASE__INST2_SEG1 = 0
|
||||
DCN_BASE__INST2_SEG2 = 0
|
||||
DCN_BASE__INST2_SEG3 = 0
|
||||
DCN_BASE__INST2_SEG4 = 0
|
||||
DCN_BASE__INST3_SEG0 = 0
|
||||
DCN_BASE__INST3_SEG1 = 0
|
||||
DCN_BASE__INST3_SEG2 = 0
|
||||
DCN_BASE__INST3_SEG3 = 0
|
||||
DCN_BASE__INST3_SEG4 = 0
|
||||
DCN_BASE__INST4_SEG0 = 0
|
||||
DCN_BASE__INST4_SEG1 = 0
|
||||
DCN_BASE__INST4_SEG2 = 0
|
||||
DCN_BASE__INST4_SEG3 = 0
|
||||
DCN_BASE__INST4_SEG4 = 0
|
||||
DCN_BASE__INST5_SEG0 = 0
|
||||
DCN_BASE__INST5_SEG1 = 0
|
||||
DCN_BASE__INST5_SEG2 = 0
|
||||
DCN_BASE__INST5_SEG3 = 0
|
||||
DCN_BASE__INST5_SEG4 = 0
|
||||
DCN_BASE__INST6_SEG0 = 0
|
||||
DCN_BASE__INST6_SEG1 = 0
|
||||
DCN_BASE__INST6_SEG2 = 0
|
||||
DCN_BASE__INST6_SEG3 = 0
|
||||
DCN_BASE__INST6_SEG4 = 0
|
||||
DPCS_BASE__INST0_SEG0 = 0x00000012
|
||||
DPCS_BASE__INST0_SEG1 = 0x000000C0
|
||||
DPCS_BASE__INST0_SEG2 = 0x000034C0
|
||||
DPCS_BASE__INST0_SEG3 = 0x00009000
|
||||
DPCS_BASE__INST0_SEG4 = 0x02403C00
|
||||
DPCS_BASE__INST1_SEG0 = 0
|
||||
DPCS_BASE__INST1_SEG1 = 0
|
||||
DPCS_BASE__INST1_SEG2 = 0
|
||||
DPCS_BASE__INST1_SEG3 = 0
|
||||
DPCS_BASE__INST1_SEG4 = 0
|
||||
DPCS_BASE__INST2_SEG0 = 0
|
||||
DPCS_BASE__INST2_SEG1 = 0
|
||||
DPCS_BASE__INST2_SEG2 = 0
|
||||
DPCS_BASE__INST2_SEG3 = 0
|
||||
DPCS_BASE__INST2_SEG4 = 0
|
||||
DPCS_BASE__INST3_SEG0 = 0
|
||||
DPCS_BASE__INST3_SEG1 = 0
|
||||
DPCS_BASE__INST3_SEG2 = 0
|
||||
DPCS_BASE__INST3_SEG3 = 0
|
||||
DPCS_BASE__INST3_SEG4 = 0
|
||||
DPCS_BASE__INST4_SEG0 = 0
|
||||
DPCS_BASE__INST4_SEG1 = 0
|
||||
DPCS_BASE__INST4_SEG2 = 0
|
||||
DPCS_BASE__INST4_SEG3 = 0
|
||||
DPCS_BASE__INST4_SEG4 = 0
|
||||
DPCS_BASE__INST5_SEG0 = 0
|
||||
DPCS_BASE__INST5_SEG1 = 0
|
||||
DPCS_BASE__INST5_SEG2 = 0
|
||||
DPCS_BASE__INST5_SEG3 = 0
|
||||
DPCS_BASE__INST5_SEG4 = 0
|
||||
DPCS_BASE__INST6_SEG0 = 0
|
||||
DPCS_BASE__INST6_SEG1 = 0
|
||||
DPCS_BASE__INST6_SEG2 = 0
|
||||
DPCS_BASE__INST6_SEG3 = 0
|
||||
DPCS_BASE__INST6_SEG4 = 0
|
||||
FUSE_BASE__INST0_SEG0 = 0x00017400
|
||||
FUSE_BASE__INST0_SEG1 = 0x02401400
|
||||
FUSE_BASE__INST0_SEG2 = 0
|
||||
FUSE_BASE__INST0_SEG3 = 0
|
||||
FUSE_BASE__INST0_SEG4 = 0
|
||||
FUSE_BASE__INST1_SEG0 = 0
|
||||
FUSE_BASE__INST1_SEG1 = 0
|
||||
FUSE_BASE__INST1_SEG2 = 0
|
||||
FUSE_BASE__INST1_SEG3 = 0
|
||||
FUSE_BASE__INST1_SEG4 = 0
|
||||
FUSE_BASE__INST2_SEG0 = 0
|
||||
FUSE_BASE__INST2_SEG1 = 0
|
||||
FUSE_BASE__INST2_SEG2 = 0
|
||||
FUSE_BASE__INST2_SEG3 = 0
|
||||
FUSE_BASE__INST2_SEG4 = 0
|
||||
FUSE_BASE__INST3_SEG0 = 0
|
||||
FUSE_BASE__INST3_SEG1 = 0
|
||||
FUSE_BASE__INST3_SEG2 = 0
|
||||
FUSE_BASE__INST3_SEG3 = 0
|
||||
FUSE_BASE__INST3_SEG4 = 0
|
||||
FUSE_BASE__INST4_SEG0 = 0
|
||||
FUSE_BASE__INST4_SEG1 = 0
|
||||
FUSE_BASE__INST4_SEG2 = 0
|
||||
FUSE_BASE__INST4_SEG3 = 0
|
||||
FUSE_BASE__INST4_SEG4 = 0
|
||||
FUSE_BASE__INST5_SEG0 = 0
|
||||
FUSE_BASE__INST5_SEG1 = 0
|
||||
FUSE_BASE__INST5_SEG2 = 0
|
||||
FUSE_BASE__INST5_SEG3 = 0
|
||||
FUSE_BASE__INST5_SEG4 = 0
|
||||
FUSE_BASE__INST6_SEG0 = 0
|
||||
FUSE_BASE__INST6_SEG1 = 0
|
||||
FUSE_BASE__INST6_SEG2 = 0
|
||||
FUSE_BASE__INST6_SEG3 = 0
|
||||
FUSE_BASE__INST6_SEG4 = 0
|
||||
GC_BASE__INST0_SEG0 = 0x00001260
|
||||
GC_BASE__INST0_SEG1 = 0x0000A000
|
||||
GC_BASE__INST0_SEG2 = 0x0001C000
|
||||
GC_BASE__INST0_SEG3 = 0x02402C00
|
||||
GC_BASE__INST0_SEG4 = 0
|
||||
GC_BASE__INST1_SEG0 = 0
|
||||
GC_BASE__INST1_SEG1 = 0
|
||||
GC_BASE__INST1_SEG2 = 0
|
||||
GC_BASE__INST1_SEG3 = 0
|
||||
GC_BASE__INST1_SEG4 = 0
|
||||
GC_BASE__INST2_SEG0 = 0
|
||||
GC_BASE__INST2_SEG1 = 0
|
||||
GC_BASE__INST2_SEG2 = 0
|
||||
GC_BASE__INST2_SEG3 = 0
|
||||
GC_BASE__INST2_SEG4 = 0
|
||||
GC_BASE__INST3_SEG0 = 0
|
||||
GC_BASE__INST3_SEG1 = 0
|
||||
GC_BASE__INST3_SEG2 = 0
|
||||
GC_BASE__INST3_SEG3 = 0
|
||||
GC_BASE__INST3_SEG4 = 0
|
||||
GC_BASE__INST4_SEG0 = 0
|
||||
GC_BASE__INST4_SEG1 = 0
|
||||
GC_BASE__INST4_SEG2 = 0
|
||||
GC_BASE__INST4_SEG3 = 0
|
||||
GC_BASE__INST4_SEG4 = 0
|
||||
GC_BASE__INST5_SEG0 = 0
|
||||
GC_BASE__INST5_SEG1 = 0
|
||||
GC_BASE__INST5_SEG2 = 0
|
||||
GC_BASE__INST5_SEG3 = 0
|
||||
GC_BASE__INST5_SEG4 = 0
|
||||
GC_BASE__INST6_SEG0 = 0
|
||||
GC_BASE__INST6_SEG1 = 0
|
||||
GC_BASE__INST6_SEG2 = 0
|
||||
GC_BASE__INST6_SEG3 = 0
|
||||
GC_BASE__INST6_SEG4 = 0
|
||||
HDA_BASE__INST0_SEG0 = 0x004C0000
|
||||
HDA_BASE__INST0_SEG1 = 0x02404800
|
||||
HDA_BASE__INST0_SEG2 = 0
|
||||
HDA_BASE__INST0_SEG3 = 0
|
||||
HDA_BASE__INST0_SEG4 = 0
|
||||
HDA_BASE__INST1_SEG0 = 0
|
||||
HDA_BASE__INST1_SEG1 = 0
|
||||
HDA_BASE__INST1_SEG2 = 0
|
||||
HDA_BASE__INST1_SEG3 = 0
|
||||
HDA_BASE__INST1_SEG4 = 0
|
||||
HDA_BASE__INST2_SEG0 = 0
|
||||
HDA_BASE__INST2_SEG1 = 0
|
||||
HDA_BASE__INST2_SEG2 = 0
|
||||
HDA_BASE__INST2_SEG3 = 0
|
||||
HDA_BASE__INST2_SEG4 = 0
|
||||
HDA_BASE__INST3_SEG0 = 0
|
||||
HDA_BASE__INST3_SEG1 = 0
|
||||
HDA_BASE__INST3_SEG2 = 0
|
||||
HDA_BASE__INST3_SEG3 = 0
|
||||
HDA_BASE__INST3_SEG4 = 0
|
||||
HDA_BASE__INST4_SEG0 = 0
|
||||
HDA_BASE__INST4_SEG1 = 0
|
||||
HDA_BASE__INST4_SEG2 = 0
|
||||
HDA_BASE__INST4_SEG3 = 0
|
||||
HDA_BASE__INST4_SEG4 = 0
|
||||
HDA_BASE__INST5_SEG0 = 0
|
||||
HDA_BASE__INST5_SEG1 = 0
|
||||
HDA_BASE__INST5_SEG2 = 0
|
||||
HDA_BASE__INST5_SEG3 = 0
|
||||
HDA_BASE__INST5_SEG4 = 0
|
||||
HDA_BASE__INST6_SEG0 = 0
|
||||
HDA_BASE__INST6_SEG1 = 0
|
||||
HDA_BASE__INST6_SEG2 = 0
|
||||
HDA_BASE__INST6_SEG3 = 0
|
||||
HDA_BASE__INST6_SEG4 = 0
|
||||
HDP_BASE__INST0_SEG0 = 0x00000F20
|
||||
HDP_BASE__INST0_SEG1 = 0x0240A400
|
||||
HDP_BASE__INST0_SEG2 = 0
|
||||
HDP_BASE__INST0_SEG3 = 0
|
||||
HDP_BASE__INST0_SEG4 = 0
|
||||
HDP_BASE__INST1_SEG0 = 0
|
||||
HDP_BASE__INST1_SEG1 = 0
|
||||
HDP_BASE__INST1_SEG2 = 0
|
||||
HDP_BASE__INST1_SEG3 = 0
|
||||
HDP_BASE__INST1_SEG4 = 0
|
||||
HDP_BASE__INST2_SEG0 = 0
|
||||
HDP_BASE__INST2_SEG1 = 0
|
||||
HDP_BASE__INST2_SEG2 = 0
|
||||
HDP_BASE__INST2_SEG3 = 0
|
||||
HDP_BASE__INST2_SEG4 = 0
|
||||
HDP_BASE__INST3_SEG0 = 0
|
||||
HDP_BASE__INST3_SEG1 = 0
|
||||
HDP_BASE__INST3_SEG2 = 0
|
||||
HDP_BASE__INST3_SEG3 = 0
|
||||
HDP_BASE__INST3_SEG4 = 0
|
||||
HDP_BASE__INST4_SEG0 = 0
|
||||
HDP_BASE__INST4_SEG1 = 0
|
||||
HDP_BASE__INST4_SEG2 = 0
|
||||
HDP_BASE__INST4_SEG3 = 0
|
||||
HDP_BASE__INST4_SEG4 = 0
|
||||
HDP_BASE__INST5_SEG0 = 0
|
||||
HDP_BASE__INST5_SEG1 = 0
|
||||
HDP_BASE__INST5_SEG2 = 0
|
||||
HDP_BASE__INST5_SEG3 = 0
|
||||
HDP_BASE__INST5_SEG4 = 0
|
||||
HDP_BASE__INST6_SEG0 = 0
|
||||
HDP_BASE__INST6_SEG1 = 0
|
||||
HDP_BASE__INST6_SEG2 = 0
|
||||
HDP_BASE__INST6_SEG3 = 0
|
||||
HDP_BASE__INST6_SEG4 = 0
|
||||
MMHUB_BASE__INST0_SEG0 = 0x0001A000
|
||||
MMHUB_BASE__INST0_SEG1 = 0x02408800
|
||||
MMHUB_BASE__INST0_SEG2 = 0
|
||||
MMHUB_BASE__INST0_SEG3 = 0
|
||||
MMHUB_BASE__INST0_SEG4 = 0
|
||||
MMHUB_BASE__INST1_SEG0 = 0
|
||||
MMHUB_BASE__INST1_SEG1 = 0
|
||||
MMHUB_BASE__INST1_SEG2 = 0
|
||||
MMHUB_BASE__INST1_SEG3 = 0
|
||||
MMHUB_BASE__INST1_SEG4 = 0
|
||||
MMHUB_BASE__INST2_SEG0 = 0
|
||||
MMHUB_BASE__INST2_SEG1 = 0
|
||||
MMHUB_BASE__INST2_SEG2 = 0
|
||||
MMHUB_BASE__INST2_SEG3 = 0
|
||||
MMHUB_BASE__INST2_SEG4 = 0
|
||||
MMHUB_BASE__INST3_SEG0 = 0
|
||||
MMHUB_BASE__INST3_SEG1 = 0
|
||||
MMHUB_BASE__INST3_SEG2 = 0
|
||||
MMHUB_BASE__INST3_SEG3 = 0
|
||||
MMHUB_BASE__INST3_SEG4 = 0
|
||||
MMHUB_BASE__INST4_SEG0 = 0
|
||||
MMHUB_BASE__INST4_SEG1 = 0
|
||||
MMHUB_BASE__INST4_SEG2 = 0
|
||||
MMHUB_BASE__INST4_SEG3 = 0
|
||||
MMHUB_BASE__INST4_SEG4 = 0
|
||||
MMHUB_BASE__INST5_SEG0 = 0
|
||||
MMHUB_BASE__INST5_SEG1 = 0
|
||||
MMHUB_BASE__INST5_SEG2 = 0
|
||||
MMHUB_BASE__INST5_SEG3 = 0
|
||||
MMHUB_BASE__INST5_SEG4 = 0
|
||||
MMHUB_BASE__INST6_SEG0 = 0
|
||||
MMHUB_BASE__INST6_SEG1 = 0
|
||||
MMHUB_BASE__INST6_SEG2 = 0
|
||||
MMHUB_BASE__INST6_SEG3 = 0
|
||||
MMHUB_BASE__INST6_SEG4 = 0
|
||||
MP0_BASE__INST0_SEG0 = 0x00016000
|
||||
MP0_BASE__INST0_SEG1 = 0x00DC0000
|
||||
MP0_BASE__INST0_SEG2 = 0x00E00000
|
||||
MP0_BASE__INST0_SEG3 = 0x00E40000
|
||||
MP0_BASE__INST0_SEG4 = 0x0243FC00
|
||||
MP0_BASE__INST1_SEG0 = 0
|
||||
MP0_BASE__INST1_SEG1 = 0
|
||||
MP0_BASE__INST1_SEG2 = 0
|
||||
MP0_BASE__INST1_SEG3 = 0
|
||||
MP0_BASE__INST1_SEG4 = 0
|
||||
MP0_BASE__INST2_SEG0 = 0
|
||||
MP0_BASE__INST2_SEG1 = 0
|
||||
MP0_BASE__INST2_SEG2 = 0
|
||||
MP0_BASE__INST2_SEG3 = 0
|
||||
MP0_BASE__INST2_SEG4 = 0
|
||||
MP0_BASE__INST3_SEG0 = 0
|
||||
MP0_BASE__INST3_SEG1 = 0
|
||||
MP0_BASE__INST3_SEG2 = 0
|
||||
MP0_BASE__INST3_SEG3 = 0
|
||||
MP0_BASE__INST3_SEG4 = 0
|
||||
MP0_BASE__INST4_SEG0 = 0
|
||||
MP0_BASE__INST4_SEG1 = 0
|
||||
MP0_BASE__INST4_SEG2 = 0
|
||||
MP0_BASE__INST4_SEG3 = 0
|
||||
MP0_BASE__INST4_SEG4 = 0
|
||||
MP0_BASE__INST5_SEG0 = 0
|
||||
MP0_BASE__INST5_SEG1 = 0
|
||||
MP0_BASE__INST5_SEG2 = 0
|
||||
MP0_BASE__INST5_SEG3 = 0
|
||||
MP0_BASE__INST5_SEG4 = 0
|
||||
MP0_BASE__INST6_SEG0 = 0
|
||||
MP0_BASE__INST6_SEG1 = 0
|
||||
MP0_BASE__INST6_SEG2 = 0
|
||||
MP0_BASE__INST6_SEG3 = 0
|
||||
MP0_BASE__INST6_SEG4 = 0
|
||||
MP1_BASE__INST0_SEG0 = 0x00016000
|
||||
MP1_BASE__INST0_SEG1 = 0x00DC0000
|
||||
MP1_BASE__INST0_SEG2 = 0x00E00000
|
||||
MP1_BASE__INST0_SEG3 = 0x00E40000
|
||||
MP1_BASE__INST0_SEG4 = 0x0243FC00
|
||||
MP1_BASE__INST1_SEG0 = 0
|
||||
MP1_BASE__INST1_SEG1 = 0
|
||||
MP1_BASE__INST1_SEG2 = 0
|
||||
MP1_BASE__INST1_SEG3 = 0
|
||||
MP1_BASE__INST1_SEG4 = 0
|
||||
MP1_BASE__INST2_SEG0 = 0
|
||||
MP1_BASE__INST2_SEG1 = 0
|
||||
MP1_BASE__INST2_SEG2 = 0
|
||||
MP1_BASE__INST2_SEG3 = 0
|
||||
MP1_BASE__INST2_SEG4 = 0
|
||||
MP1_BASE__INST3_SEG0 = 0
|
||||
MP1_BASE__INST3_SEG1 = 0
|
||||
MP1_BASE__INST3_SEG2 = 0
|
||||
MP1_BASE__INST3_SEG3 = 0
|
||||
MP1_BASE__INST3_SEG4 = 0
|
||||
MP1_BASE__INST4_SEG0 = 0
|
||||
MP1_BASE__INST4_SEG1 = 0
|
||||
MP1_BASE__INST4_SEG2 = 0
|
||||
MP1_BASE__INST4_SEG3 = 0
|
||||
MP1_BASE__INST4_SEG4 = 0
|
||||
MP1_BASE__INST5_SEG0 = 0
|
||||
MP1_BASE__INST5_SEG1 = 0
|
||||
MP1_BASE__INST5_SEG2 = 0
|
||||
MP1_BASE__INST5_SEG3 = 0
|
||||
MP1_BASE__INST5_SEG4 = 0
|
||||
MP1_BASE__INST6_SEG0 = 0
|
||||
MP1_BASE__INST6_SEG1 = 0
|
||||
MP1_BASE__INST6_SEG2 = 0
|
||||
MP1_BASE__INST6_SEG3 = 0
|
||||
MP1_BASE__INST6_SEG4 = 0
|
||||
NBIO_BASE__INST0_SEG0 = 0x00000000
|
||||
NBIO_BASE__INST0_SEG1 = 0x00000014
|
||||
NBIO_BASE__INST0_SEG2 = 0x00000D20
|
||||
NBIO_BASE__INST0_SEG3 = 0x00010400
|
||||
NBIO_BASE__INST0_SEG4 = 0x0241B000
|
||||
NBIO_BASE__INST1_SEG0 = 0
|
||||
NBIO_BASE__INST1_SEG1 = 0
|
||||
NBIO_BASE__INST1_SEG2 = 0
|
||||
NBIO_BASE__INST1_SEG3 = 0
|
||||
NBIO_BASE__INST1_SEG4 = 0
|
||||
NBIO_BASE__INST2_SEG0 = 0
|
||||
NBIO_BASE__INST2_SEG1 = 0
|
||||
NBIO_BASE__INST2_SEG2 = 0
|
||||
NBIO_BASE__INST2_SEG3 = 0
|
||||
NBIO_BASE__INST2_SEG4 = 0
|
||||
NBIO_BASE__INST3_SEG0 = 0
|
||||
NBIO_BASE__INST3_SEG1 = 0
|
||||
NBIO_BASE__INST3_SEG2 = 0
|
||||
NBIO_BASE__INST3_SEG3 = 0
|
||||
NBIO_BASE__INST3_SEG4 = 0
|
||||
NBIO_BASE__INST4_SEG0 = 0
|
||||
NBIO_BASE__INST4_SEG1 = 0
|
||||
NBIO_BASE__INST4_SEG2 = 0
|
||||
NBIO_BASE__INST4_SEG3 = 0
|
||||
NBIO_BASE__INST4_SEG4 = 0
|
||||
NBIO_BASE__INST5_SEG0 = 0
|
||||
NBIO_BASE__INST5_SEG1 = 0
|
||||
NBIO_BASE__INST5_SEG2 = 0
|
||||
NBIO_BASE__INST5_SEG3 = 0
|
||||
NBIO_BASE__INST5_SEG4 = 0
|
||||
NBIO_BASE__INST6_SEG0 = 0
|
||||
NBIO_BASE__INST6_SEG1 = 0
|
||||
NBIO_BASE__INST6_SEG2 = 0
|
||||
NBIO_BASE__INST6_SEG3 = 0
|
||||
NBIO_BASE__INST6_SEG4 = 0
|
||||
OSSSYS_BASE__INST0_SEG0 = 0x000010A0
|
||||
OSSSYS_BASE__INST0_SEG1 = 0x0240A000
|
||||
OSSSYS_BASE__INST0_SEG2 = 0
|
||||
OSSSYS_BASE__INST0_SEG3 = 0
|
||||
OSSSYS_BASE__INST0_SEG4 = 0
|
||||
OSSSYS_BASE__INST1_SEG0 = 0
|
||||
OSSSYS_BASE__INST1_SEG1 = 0
|
||||
OSSSYS_BASE__INST1_SEG2 = 0
|
||||
OSSSYS_BASE__INST1_SEG3 = 0
|
||||
OSSSYS_BASE__INST1_SEG4 = 0
|
||||
OSSSYS_BASE__INST2_SEG0 = 0
|
||||
OSSSYS_BASE__INST2_SEG1 = 0
|
||||
OSSSYS_BASE__INST2_SEG2 = 0
|
||||
OSSSYS_BASE__INST2_SEG3 = 0
|
||||
OSSSYS_BASE__INST2_SEG4 = 0
|
||||
OSSSYS_BASE__INST3_SEG0 = 0
|
||||
OSSSYS_BASE__INST3_SEG1 = 0
|
||||
OSSSYS_BASE__INST3_SEG2 = 0
|
||||
OSSSYS_BASE__INST3_SEG3 = 0
|
||||
OSSSYS_BASE__INST3_SEG4 = 0
|
||||
OSSSYS_BASE__INST4_SEG0 = 0
|
||||
OSSSYS_BASE__INST4_SEG1 = 0
|
||||
OSSSYS_BASE__INST4_SEG2 = 0
|
||||
OSSSYS_BASE__INST4_SEG3 = 0
|
||||
OSSSYS_BASE__INST4_SEG4 = 0
|
||||
OSSSYS_BASE__INST5_SEG0 = 0
|
||||
OSSSYS_BASE__INST5_SEG1 = 0
|
||||
OSSSYS_BASE__INST5_SEG2 = 0
|
||||
OSSSYS_BASE__INST5_SEG3 = 0
|
||||
OSSSYS_BASE__INST5_SEG4 = 0
|
||||
OSSSYS_BASE__INST6_SEG0 = 0
|
||||
OSSSYS_BASE__INST6_SEG1 = 0
|
||||
OSSSYS_BASE__INST6_SEG2 = 0
|
||||
OSSSYS_BASE__INST6_SEG3 = 0
|
||||
OSSSYS_BASE__INST6_SEG4 = 0
|
||||
PCIE0_BASE__INST0_SEG0 = 0x00000000
|
||||
PCIE0_BASE__INST0_SEG1 = 0x00000014
|
||||
PCIE0_BASE__INST0_SEG2 = 0x00000D20
|
||||
PCIE0_BASE__INST0_SEG3 = 0x00010400
|
||||
PCIE0_BASE__INST0_SEG4 = 0x0241B000
|
||||
PCIE0_BASE__INST1_SEG0 = 0
|
||||
PCIE0_BASE__INST1_SEG1 = 0
|
||||
PCIE0_BASE__INST1_SEG2 = 0
|
||||
PCIE0_BASE__INST1_SEG3 = 0
|
||||
PCIE0_BASE__INST1_SEG4 = 0
|
||||
PCIE0_BASE__INST2_SEG0 = 0
|
||||
PCIE0_BASE__INST2_SEG1 = 0
|
||||
PCIE0_BASE__INST2_SEG2 = 0
|
||||
PCIE0_BASE__INST2_SEG3 = 0
|
||||
PCIE0_BASE__INST2_SEG4 = 0
|
||||
PCIE0_BASE__INST3_SEG0 = 0
|
||||
PCIE0_BASE__INST3_SEG1 = 0
|
||||
PCIE0_BASE__INST3_SEG2 = 0
|
||||
PCIE0_BASE__INST3_SEG3 = 0
|
||||
PCIE0_BASE__INST3_SEG4 = 0
|
||||
PCIE0_BASE__INST4_SEG0 = 0
|
||||
PCIE0_BASE__INST4_SEG1 = 0
|
||||
PCIE0_BASE__INST4_SEG2 = 0
|
||||
PCIE0_BASE__INST4_SEG3 = 0
|
||||
PCIE0_BASE__INST4_SEG4 = 0
|
||||
PCIE0_BASE__INST5_SEG0 = 0
|
||||
PCIE0_BASE__INST5_SEG1 = 0
|
||||
PCIE0_BASE__INST5_SEG2 = 0
|
||||
PCIE0_BASE__INST5_SEG3 = 0
|
||||
PCIE0_BASE__INST5_SEG4 = 0
|
||||
PCIE0_BASE__INST6_SEG0 = 0
|
||||
PCIE0_BASE__INST6_SEG1 = 0
|
||||
PCIE0_BASE__INST6_SEG2 = 0
|
||||
PCIE0_BASE__INST6_SEG3 = 0
|
||||
PCIE0_BASE__INST6_SEG4 = 0
|
||||
SDMA0_BASE__INST0_SEG0 = 0x00001260
|
||||
SDMA0_BASE__INST0_SEG1 = 0x0000A000
|
||||
SDMA0_BASE__INST0_SEG2 = 0x0001C000
|
||||
SDMA0_BASE__INST0_SEG3 = 0x02402C00
|
||||
SDMA0_BASE__INST0_SEG4 = 0
|
||||
SDMA0_BASE__INST1_SEG0 = 0
|
||||
SDMA0_BASE__INST1_SEG1 = 0
|
||||
SDMA0_BASE__INST1_SEG2 = 0
|
||||
SDMA0_BASE__INST1_SEG3 = 0
|
||||
SDMA0_BASE__INST1_SEG4 = 0
|
||||
SDMA0_BASE__INST2_SEG0 = 0
|
||||
SDMA0_BASE__INST2_SEG1 = 0
|
||||
SDMA0_BASE__INST2_SEG2 = 0
|
||||
SDMA0_BASE__INST2_SEG3 = 0
|
||||
SDMA0_BASE__INST2_SEG4 = 0
|
||||
SDMA0_BASE__INST3_SEG0 = 0
|
||||
SDMA0_BASE__INST3_SEG1 = 0
|
||||
SDMA0_BASE__INST3_SEG2 = 0
|
||||
SDMA0_BASE__INST3_SEG3 = 0
|
||||
SDMA0_BASE__INST3_SEG4 = 0
|
||||
SDMA0_BASE__INST4_SEG0 = 0
|
||||
SDMA0_BASE__INST4_SEG1 = 0
|
||||
SDMA0_BASE__INST4_SEG2 = 0
|
||||
SDMA0_BASE__INST4_SEG3 = 0
|
||||
SDMA0_BASE__INST4_SEG4 = 0
|
||||
SDMA0_BASE__INST5_SEG0 = 0
|
||||
SDMA0_BASE__INST5_SEG1 = 0
|
||||
SDMA0_BASE__INST5_SEG2 = 0
|
||||
SDMA0_BASE__INST5_SEG3 = 0
|
||||
SDMA0_BASE__INST5_SEG4 = 0
|
||||
SDMA0_BASE__INST6_SEG0 = 0
|
||||
SDMA0_BASE__INST6_SEG1 = 0
|
||||
SDMA0_BASE__INST6_SEG2 = 0
|
||||
SDMA0_BASE__INST6_SEG3 = 0
|
||||
SDMA0_BASE__INST6_SEG4 = 0
|
||||
SDMA1_BASE__INST0_SEG0 = 0x00001260
|
||||
SDMA1_BASE__INST0_SEG1 = 0x0000A000
|
||||
SDMA1_BASE__INST0_SEG2 = 0x0001C000
|
||||
SDMA1_BASE__INST0_SEG3 = 0x02402C00
|
||||
SDMA1_BASE__INST0_SEG4 = 0
|
||||
SDMA1_BASE__INST1_SEG0 = 0
|
||||
SDMA1_BASE__INST1_SEG1 = 0
|
||||
SDMA1_BASE__INST1_SEG2 = 0
|
||||
SDMA1_BASE__INST1_SEG3 = 0
|
||||
SDMA1_BASE__INST1_SEG4 = 0
|
||||
SDMA1_BASE__INST2_SEG0 = 0
|
||||
SDMA1_BASE__INST2_SEG1 = 0
|
||||
SDMA1_BASE__INST2_SEG2 = 0
|
||||
SDMA1_BASE__INST2_SEG3 = 0
|
||||
SDMA1_BASE__INST2_SEG4 = 0
|
||||
SDMA1_BASE__INST3_SEG0 = 0
|
||||
SDMA1_BASE__INST3_SEG1 = 0
|
||||
SDMA1_BASE__INST3_SEG2 = 0
|
||||
SDMA1_BASE__INST3_SEG3 = 0
|
||||
SDMA1_BASE__INST3_SEG4 = 0
|
||||
SDMA1_BASE__INST4_SEG0 = 0
|
||||
SDMA1_BASE__INST4_SEG1 = 0
|
||||
SDMA1_BASE__INST4_SEG2 = 0
|
||||
SDMA1_BASE__INST4_SEG3 = 0
|
||||
SDMA1_BASE__INST4_SEG4 = 0
|
||||
SDMA1_BASE__INST5_SEG0 = 0
|
||||
SDMA1_BASE__INST5_SEG1 = 0
|
||||
SDMA1_BASE__INST5_SEG2 = 0
|
||||
SDMA1_BASE__INST5_SEG3 = 0
|
||||
SDMA1_BASE__INST5_SEG4 = 0
|
||||
SDMA1_BASE__INST6_SEG0 = 0
|
||||
SDMA1_BASE__INST6_SEG1 = 0
|
||||
SDMA1_BASE__INST6_SEG2 = 0
|
||||
SDMA1_BASE__INST6_SEG3 = 0
|
||||
SDMA1_BASE__INST6_SEG4 = 0
|
||||
SMUIO_BASE__INST0_SEG0 = 0x00016800
|
||||
SMUIO_BASE__INST0_SEG1 = 0x00016A00
|
||||
SMUIO_BASE__INST0_SEG2 = 0x00440000
|
||||
SMUIO_BASE__INST0_SEG3 = 0x02401000
|
||||
SMUIO_BASE__INST0_SEG4 = 0
|
||||
SMUIO_BASE__INST1_SEG0 = 0
|
||||
SMUIO_BASE__INST1_SEG1 = 0
|
||||
SMUIO_BASE__INST1_SEG2 = 0
|
||||
SMUIO_BASE__INST1_SEG3 = 0
|
||||
SMUIO_BASE__INST1_SEG4 = 0
|
||||
SMUIO_BASE__INST2_SEG0 = 0
|
||||
SMUIO_BASE__INST2_SEG1 = 0
|
||||
SMUIO_BASE__INST2_SEG2 = 0
|
||||
SMUIO_BASE__INST2_SEG3 = 0
|
||||
SMUIO_BASE__INST2_SEG4 = 0
|
||||
SMUIO_BASE__INST3_SEG0 = 0
|
||||
SMUIO_BASE__INST3_SEG1 = 0
|
||||
SMUIO_BASE__INST3_SEG2 = 0
|
||||
SMUIO_BASE__INST3_SEG3 = 0
|
||||
SMUIO_BASE__INST3_SEG4 = 0
|
||||
SMUIO_BASE__INST4_SEG0 = 0
|
||||
SMUIO_BASE__INST4_SEG1 = 0
|
||||
SMUIO_BASE__INST4_SEG2 = 0
|
||||
SMUIO_BASE__INST4_SEG3 = 0
|
||||
SMUIO_BASE__INST4_SEG4 = 0
|
||||
SMUIO_BASE__INST5_SEG0 = 0
|
||||
SMUIO_BASE__INST5_SEG1 = 0
|
||||
SMUIO_BASE__INST5_SEG2 = 0
|
||||
SMUIO_BASE__INST5_SEG3 = 0
|
||||
SMUIO_BASE__INST5_SEG4 = 0
|
||||
SMUIO_BASE__INST6_SEG0 = 0
|
||||
SMUIO_BASE__INST6_SEG1 = 0
|
||||
SMUIO_BASE__INST6_SEG2 = 0
|
||||
SMUIO_BASE__INST6_SEG3 = 0
|
||||
SMUIO_BASE__INST6_SEG4 = 0
|
||||
THM_BASE__INST0_SEG0 = 0x00016600
|
||||
THM_BASE__INST0_SEG1 = 0x02400C00
|
||||
THM_BASE__INST0_SEG2 = 0
|
||||
THM_BASE__INST0_SEG3 = 0
|
||||
THM_BASE__INST0_SEG4 = 0
|
||||
THM_BASE__INST1_SEG0 = 0
|
||||
THM_BASE__INST1_SEG1 = 0
|
||||
THM_BASE__INST1_SEG2 = 0
|
||||
THM_BASE__INST1_SEG3 = 0
|
||||
THM_BASE__INST1_SEG4 = 0
|
||||
THM_BASE__INST2_SEG0 = 0
|
||||
THM_BASE__INST2_SEG1 = 0
|
||||
THM_BASE__INST2_SEG2 = 0
|
||||
THM_BASE__INST2_SEG3 = 0
|
||||
THM_BASE__INST2_SEG4 = 0
|
||||
THM_BASE__INST3_SEG0 = 0
|
||||
THM_BASE__INST3_SEG1 = 0
|
||||
THM_BASE__INST3_SEG2 = 0
|
||||
THM_BASE__INST3_SEG3 = 0
|
||||
THM_BASE__INST3_SEG4 = 0
|
||||
THM_BASE__INST4_SEG0 = 0
|
||||
THM_BASE__INST4_SEG1 = 0
|
||||
THM_BASE__INST4_SEG2 = 0
|
||||
THM_BASE__INST4_SEG3 = 0
|
||||
THM_BASE__INST4_SEG4 = 0
|
||||
THM_BASE__INST5_SEG0 = 0
|
||||
THM_BASE__INST5_SEG1 = 0
|
||||
THM_BASE__INST5_SEG2 = 0
|
||||
THM_BASE__INST5_SEG3 = 0
|
||||
THM_BASE__INST5_SEG4 = 0
|
||||
THM_BASE__INST6_SEG0 = 0
|
||||
THM_BASE__INST6_SEG1 = 0
|
||||
THM_BASE__INST6_SEG2 = 0
|
||||
THM_BASE__INST6_SEG3 = 0
|
||||
THM_BASE__INST6_SEG4 = 0
|
||||
UMC_BASE__INST0_SEG0 = 0x00014000
|
||||
UMC_BASE__INST0_SEG1 = 0x02425800
|
||||
UMC_BASE__INST0_SEG2 = 0
|
||||
UMC_BASE__INST0_SEG3 = 0
|
||||
UMC_BASE__INST0_SEG4 = 0
|
||||
UMC_BASE__INST1_SEG0 = 0x00054000
|
||||
UMC_BASE__INST1_SEG1 = 0x02425C00
|
||||
UMC_BASE__INST1_SEG2 = 0
|
||||
UMC_BASE__INST1_SEG3 = 0
|
||||
UMC_BASE__INST1_SEG4 = 0
|
||||
UMC_BASE__INST2_SEG0 = 0x00094000
|
||||
UMC_BASE__INST2_SEG1 = 0x02426000
|
||||
UMC_BASE__INST2_SEG2 = 0
|
||||
UMC_BASE__INST2_SEG3 = 0
|
||||
UMC_BASE__INST2_SEG4 = 0
|
||||
UMC_BASE__INST3_SEG0 = 0x000D4000
|
||||
UMC_BASE__INST3_SEG1 = 0x02426400
|
||||
UMC_BASE__INST3_SEG2 = 0
|
||||
UMC_BASE__INST3_SEG3 = 0
|
||||
UMC_BASE__INST3_SEG4 = 0
|
||||
UMC_BASE__INST4_SEG0 = 0x00114000
|
||||
UMC_BASE__INST4_SEG1 = 0x02426800
|
||||
UMC_BASE__INST4_SEG2 = 0
|
||||
UMC_BASE__INST4_SEG3 = 0
|
||||
UMC_BASE__INST4_SEG4 = 0
|
||||
UMC_BASE__INST5_SEG0 = 0x00154000
|
||||
UMC_BASE__INST5_SEG1 = 0x02426C00
|
||||
UMC_BASE__INST5_SEG2 = 0
|
||||
UMC_BASE__INST5_SEG3 = 0
|
||||
UMC_BASE__INST5_SEG4 = 0
|
||||
UMC_BASE__INST6_SEG0 = 0x00194000
|
||||
UMC_BASE__INST6_SEG1 = 0x02427000
|
||||
UMC_BASE__INST6_SEG2 = 0
|
||||
UMC_BASE__INST6_SEG3 = 0
|
||||
UMC_BASE__INST6_SEG4 = 0
|
||||
USB0_BASE__INST0_SEG0 = 0x0242A800
|
||||
USB0_BASE__INST0_SEG1 = 0x05B00000
|
||||
USB0_BASE__INST0_SEG2 = 0
|
||||
USB0_BASE__INST0_SEG3 = 0
|
||||
USB0_BASE__INST0_SEG4 = 0
|
||||
USB0_BASE__INST1_SEG0 = 0
|
||||
USB0_BASE__INST1_SEG1 = 0
|
||||
USB0_BASE__INST1_SEG2 = 0
|
||||
USB0_BASE__INST1_SEG3 = 0
|
||||
USB0_BASE__INST1_SEG4 = 0
|
||||
USB0_BASE__INST2_SEG0 = 0
|
||||
USB0_BASE__INST2_SEG1 = 0
|
||||
USB0_BASE__INST2_SEG2 = 0
|
||||
USB0_BASE__INST2_SEG3 = 0
|
||||
USB0_BASE__INST2_SEG4 = 0
|
||||
USB0_BASE__INST3_SEG0 = 0
|
||||
USB0_BASE__INST3_SEG1 = 0
|
||||
USB0_BASE__INST3_SEG2 = 0
|
||||
USB0_BASE__INST3_SEG3 = 0
|
||||
USB0_BASE__INST3_SEG4 = 0
|
||||
USB0_BASE__INST4_SEG0 = 0
|
||||
USB0_BASE__INST4_SEG1 = 0
|
||||
USB0_BASE__INST4_SEG2 = 0
|
||||
USB0_BASE__INST4_SEG3 = 0
|
||||
USB0_BASE__INST4_SEG4 = 0
|
||||
USB0_BASE__INST5_SEG0 = 0
|
||||
USB0_BASE__INST5_SEG1 = 0
|
||||
USB0_BASE__INST5_SEG2 = 0
|
||||
USB0_BASE__INST5_SEG3 = 0
|
||||
USB0_BASE__INST5_SEG4 = 0
|
||||
USB0_BASE__INST6_SEG0 = 0
|
||||
USB0_BASE__INST6_SEG1 = 0
|
||||
USB0_BASE__INST6_SEG2 = 0
|
||||
USB0_BASE__INST6_SEG3 = 0
|
||||
USB0_BASE__INST6_SEG4 = 0
|
||||
VCN_BASE__INST0_SEG0 = 0x00007800
|
||||
VCN_BASE__INST0_SEG1 = 0x00007E00
|
||||
VCN_BASE__INST0_SEG2 = 0x02403000
|
||||
VCN_BASE__INST0_SEG3 = 0
|
||||
VCN_BASE__INST0_SEG4 = 0
|
||||
VCN_BASE__INST1_SEG0 = 0x00007B00
|
||||
VCN_BASE__INST1_SEG1 = 0x00012000
|
||||
VCN_BASE__INST1_SEG2 = 0x02445000
|
||||
VCN_BASE__INST1_SEG3 = 0
|
||||
VCN_BASE__INST1_SEG4 = 0
|
||||
VCN_BASE__INST2_SEG0 = 0
|
||||
VCN_BASE__INST2_SEG1 = 0
|
||||
VCN_BASE__INST2_SEG2 = 0
|
||||
VCN_BASE__INST2_SEG3 = 0
|
||||
VCN_BASE__INST2_SEG4 = 0
|
||||
VCN_BASE__INST3_SEG0 = 0
|
||||
VCN_BASE__INST3_SEG1 = 0
|
||||
VCN_BASE__INST3_SEG2 = 0
|
||||
VCN_BASE__INST3_SEG3 = 0
|
||||
VCN_BASE__INST3_SEG4 = 0
|
||||
VCN_BASE__INST4_SEG0 = 0
|
||||
VCN_BASE__INST4_SEG1 = 0
|
||||
VCN_BASE__INST4_SEG2 = 0
|
||||
VCN_BASE__INST4_SEG3 = 0
|
||||
VCN_BASE__INST4_SEG4 = 0
|
||||
VCN_BASE__INST5_SEG0 = 0
|
||||
VCN_BASE__INST5_SEG1 = 0
|
||||
VCN_BASE__INST5_SEG2 = 0
|
||||
VCN_BASE__INST5_SEG3 = 0
|
||||
VCN_BASE__INST5_SEG4 = 0
|
||||
VCN_BASE__INST6_SEG0 = 0
|
||||
VCN_BASE__INST6_SEG1 = 0
|
||||
VCN_BASE__INST6_SEG2 = 0
|
||||
VCN_BASE__INST6_SEG3 = 0
|
||||
VCN_BASE__INST6_SEG4 = 0
|
||||
487
tinygrad_repo/tinygrad/runtime/autogen/am/pm4_nv.py
Normal file
487
tinygrad_repo/tinygrad/runtime/autogen/am/pm4_nv.py
Normal file
@@ -0,0 +1,487 @@
|
||||
# mypy: disable-error-code="empty-body"
|
||||
from __future__ import annotations
|
||||
import ctypes
|
||||
from typing import Literal, TypeAlias
|
||||
from tinygrad.runtime.support.c import _IO, _IOW, _IOR, _IOWR
|
||||
from tinygrad.runtime.support import c
|
||||
class union_PM4_MES_TYPE_3_HEADER(c.Struct): pass
|
||||
enum_mes_set_resources_queue_type_enum: dict[int, str] = {(queue_type__mes_set_resources__kernel_interface_queue_kiq:=0): 'queue_type__mes_set_resources__kernel_interface_queue_kiq', (queue_type__mes_set_resources__hsa_interface_queue_hiq:=1): 'queue_type__mes_set_resources__hsa_interface_queue_hiq', (queue_type__mes_set_resources__hsa_debug_interface_queue:=4): 'queue_type__mes_set_resources__hsa_debug_interface_queue'}
|
||||
class struct_pm4_mes_set_resources(c.Struct): pass
|
||||
class struct_pm4_mes_runlist(c.Struct): pass
|
||||
class struct_pm4_mes_map_process(c.Struct): pass
|
||||
class struct_PM4_MES_MAP_PROCESS_VM(c.Struct): pass
|
||||
enum_mes_map_queues_queue_sel_enum: dict[int, str] = {(queue_sel__mes_map_queues__map_to_specified_queue_slots_vi:=0): 'queue_sel__mes_map_queues__map_to_specified_queue_slots_vi', (queue_sel__mes_map_queues__map_to_hws_determined_queue_slots_vi:=1): 'queue_sel__mes_map_queues__map_to_hws_determined_queue_slots_vi'}
|
||||
enum_mes_map_queues_queue_type_enum: dict[int, str] = {(queue_type__mes_map_queues__normal_compute_vi:=0): 'queue_type__mes_map_queues__normal_compute_vi', (queue_type__mes_map_queues__debug_interface_queue_vi:=1): 'queue_type__mes_map_queues__debug_interface_queue_vi', (queue_type__mes_map_queues__normal_latency_static_queue_vi:=2): 'queue_type__mes_map_queues__normal_latency_static_queue_vi', (queue_type__mes_map_queues__low_latency_static_queue_vi:=3): 'queue_type__mes_map_queues__low_latency_static_queue_vi'}
|
||||
enum_mes_map_queues_engine_sel_enum: dict[int, str] = {(engine_sel__mes_map_queues__compute_vi:=0): 'engine_sel__mes_map_queues__compute_vi', (engine_sel__mes_map_queues__sdma0_vi:=2): 'engine_sel__mes_map_queues__sdma0_vi', (engine_sel__mes_map_queues__sdma1_vi:=3): 'engine_sel__mes_map_queues__sdma1_vi'}
|
||||
enum_mes_map_queues_extended_engine_sel_enum: dict[int, str] = {(extended_engine_sel__mes_map_queues__legacy_engine_sel:=0): 'extended_engine_sel__mes_map_queues__legacy_engine_sel', (extended_engine_sel__mes_map_queues__sdma0_to_7_sel:=1): 'extended_engine_sel__mes_map_queues__sdma0_to_7_sel', (extended_engine_sel__mes_map_queues__sdma8_to_15_sel:=2): 'extended_engine_sel__mes_map_queues__sdma8_to_15_sel'}
|
||||
class struct_pm4_mes_map_queues(c.Struct): pass
|
||||
enum_mes_query_status_interrupt_sel_enum: dict[int, str] = {(interrupt_sel__mes_query_status__completion_status:=0): 'interrupt_sel__mes_query_status__completion_status', (interrupt_sel__mes_query_status__process_status:=1): 'interrupt_sel__mes_query_status__process_status', (interrupt_sel__mes_query_status__queue_status:=2): 'interrupt_sel__mes_query_status__queue_status'}
|
||||
enum_mes_query_status_command_enum: dict[int, str] = {(command__mes_query_status__interrupt_only:=0): 'command__mes_query_status__interrupt_only', (command__mes_query_status__fence_only_immediate:=1): 'command__mes_query_status__fence_only_immediate', (command__mes_query_status__fence_only_after_write_ack:=2): 'command__mes_query_status__fence_only_after_write_ack', (command__mes_query_status__fence_wait_for_write_ack_send_interrupt:=3): 'command__mes_query_status__fence_wait_for_write_ack_send_interrupt'}
|
||||
enum_mes_query_status_engine_sel_enum: dict[int, str] = {(engine_sel__mes_query_status__compute:=0): 'engine_sel__mes_query_status__compute', (engine_sel__mes_query_status__sdma0_queue:=2): 'engine_sel__mes_query_status__sdma0_queue', (engine_sel__mes_query_status__sdma1_queue:=3): 'engine_sel__mes_query_status__sdma1_queue'}
|
||||
class struct_pm4_mes_query_status(c.Struct): pass
|
||||
enum_mes_unmap_queues_action_enum: dict[int, str] = {(action__mes_unmap_queues__preempt_queues:=0): 'action__mes_unmap_queues__preempt_queues', (action__mes_unmap_queues__reset_queues:=1): 'action__mes_unmap_queues__reset_queues', (action__mes_unmap_queues__disable_process_queues:=2): 'action__mes_unmap_queues__disable_process_queues', (action__mes_unmap_queues__reserved:=3): 'action__mes_unmap_queues__reserved'}
|
||||
enum_mes_unmap_queues_queue_sel_enum: dict[int, str] = {(queue_sel__mes_unmap_queues__perform_request_on_specified_queues:=0): 'queue_sel__mes_unmap_queues__perform_request_on_specified_queues', (queue_sel__mes_unmap_queues__perform_request_on_pasid_queues:=1): 'queue_sel__mes_unmap_queues__perform_request_on_pasid_queues', (queue_sel__mes_unmap_queues__unmap_all_queues:=2): 'queue_sel__mes_unmap_queues__unmap_all_queues', (queue_sel__mes_unmap_queues__unmap_all_non_static_queues:=3): 'queue_sel__mes_unmap_queues__unmap_all_non_static_queues'}
|
||||
enum_mes_unmap_queues_engine_sel_enum: dict[int, str] = {(engine_sel__mes_unmap_queues__compute:=0): 'engine_sel__mes_unmap_queues__compute', (engine_sel__mes_unmap_queues__sdma0:=2): 'engine_sel__mes_unmap_queues__sdma0', (engine_sel__mes_unmap_queues__sdmal:=3): 'engine_sel__mes_unmap_queues__sdmal'}
|
||||
enum_mes_unmap_queues_extended_engine_sel_enum: dict[int, str] = {(extended_engine_sel__mes_unmap_queues__legacy_engine_sel:=0): 'extended_engine_sel__mes_unmap_queues__legacy_engine_sel', (extended_engine_sel__mes_unmap_queues__sdma0_to_7_sel:=1): 'extended_engine_sel__mes_unmap_queues__sdma0_to_7_sel'}
|
||||
class struct_pm4_mes_unmap_queues(c.Struct): pass
|
||||
enum_mec_release_mem_event_index_enum: dict[int, str] = {(event_index__mec_release_mem__end_of_pipe:=5): 'event_index__mec_release_mem__end_of_pipe', (event_index__mec_release_mem__shader_done:=6): 'event_index__mec_release_mem__shader_done'}
|
||||
enum_mec_release_mem_cache_policy_enum: dict[int, str] = {(cache_policy__mec_release_mem__lru:=0): 'cache_policy__mec_release_mem__lru', (cache_policy__mec_release_mem__stream:=1): 'cache_policy__mec_release_mem__stream'}
|
||||
enum_mec_release_mem_pq_exe_status_enum: dict[int, str] = {(pq_exe_status__mec_release_mem__default:=0): 'pq_exe_status__mec_release_mem__default', (pq_exe_status__mec_release_mem__phase_update:=1): 'pq_exe_status__mec_release_mem__phase_update'}
|
||||
enum_mec_release_mem_dst_sel_enum: dict[int, str] = {(dst_sel__mec_release_mem__memory_controller:=0): 'dst_sel__mec_release_mem__memory_controller', (dst_sel__mec_release_mem__tc_l2:=1): 'dst_sel__mec_release_mem__tc_l2', (dst_sel__mec_release_mem__queue_write_pointer_register:=2): 'dst_sel__mec_release_mem__queue_write_pointer_register', (dst_sel__mec_release_mem__queue_write_pointer_poll_mask_bit:=3): 'dst_sel__mec_release_mem__queue_write_pointer_poll_mask_bit'}
|
||||
enum_mec_release_mem_int_sel_enum: dict[int, str] = {(int_sel__mec_release_mem__none:=0): 'int_sel__mec_release_mem__none', (int_sel__mec_release_mem__send_interrupt_only:=1): 'int_sel__mec_release_mem__send_interrupt_only', (int_sel__mec_release_mem__send_interrupt_after_write_confirm:=2): 'int_sel__mec_release_mem__send_interrupt_after_write_confirm', (int_sel__mec_release_mem__send_data_after_write_confirm:=3): 'int_sel__mec_release_mem__send_data_after_write_confirm', (int_sel__mec_release_mem__unconditionally_send_int_ctxid:=4): 'int_sel__mec_release_mem__unconditionally_send_int_ctxid', (int_sel__mec_release_mem__conditionally_send_int_ctxid_based_on_32_bit_compare:=5): 'int_sel__mec_release_mem__conditionally_send_int_ctxid_based_on_32_bit_compare', (int_sel__mec_release_mem__conditionally_send_int_ctxid_based_on_64_bit_compare:=6): 'int_sel__mec_release_mem__conditionally_send_int_ctxid_based_on_64_bit_compare'}
|
||||
enum_mec_release_mem_data_sel_enum: dict[int, str] = {(data_sel__mec_release_mem__none:=0): 'data_sel__mec_release_mem__none', (data_sel__mec_release_mem__send_32_bit_low:=1): 'data_sel__mec_release_mem__send_32_bit_low', (data_sel__mec_release_mem__send_64_bit_data:=2): 'data_sel__mec_release_mem__send_64_bit_data', (data_sel__mec_release_mem__send_gpu_clock_counter:=3): 'data_sel__mec_release_mem__send_gpu_clock_counter', (data_sel__mec_release_mem__send_cp_perfcounter_hi_lo:=4): 'data_sel__mec_release_mem__send_cp_perfcounter_hi_lo', (data_sel__mec_release_mem__store_gds_data_to_memory:=5): 'data_sel__mec_release_mem__store_gds_data_to_memory'}
|
||||
class struct_pm4_mec_release_mem(c.Struct): pass
|
||||
enum_WRITE_DATA_dst_sel_enum: dict[int, str] = {(dst_sel___write_data__mem_mapped_register:=0): 'dst_sel___write_data__mem_mapped_register', (dst_sel___write_data__tc_l2:=2): 'dst_sel___write_data__tc_l2', (dst_sel___write_data__gds:=3): 'dst_sel___write_data__gds', (dst_sel___write_data__memory:=5): 'dst_sel___write_data__memory', (dst_sel___write_data__memory_mapped_adc_persistent_state:=6): 'dst_sel___write_data__memory_mapped_adc_persistent_state'}
|
||||
enum_WRITE_DATA_addr_incr_enum: dict[int, str] = {(addr_incr___write_data__increment_address:=0): 'addr_incr___write_data__increment_address', (addr_incr___write_data__do_not_increment_address:=1): 'addr_incr___write_data__do_not_increment_address'}
|
||||
enum_WRITE_DATA_wr_confirm_enum: dict[int, str] = {(wr_confirm___write_data__do_not_wait_for_write_confirmation:=0): 'wr_confirm___write_data__do_not_wait_for_write_confirmation', (wr_confirm___write_data__wait_for_write_confirmation:=1): 'wr_confirm___write_data__wait_for_write_confirmation'}
|
||||
enum_WRITE_DATA_cache_policy_enum: dict[int, str] = {(cache_policy___write_data__lru:=0): 'cache_policy___write_data__lru', (cache_policy___write_data__stream:=1): 'cache_policy___write_data__stream'}
|
||||
class struct_pm4_mec_write_data_mmio(c.Struct): pass
|
||||
_anonenum0: dict[int, str] = {(CACHE_FLUSH_AND_INV_TS_EVENT:=20): 'CACHE_FLUSH_AND_INV_TS_EVENT'}
|
||||
PACKET_TYPE0 = 0
|
||||
PACKET_TYPE1 = 1
|
||||
PACKET_TYPE2 = 2
|
||||
PACKET_TYPE3 = 3
|
||||
CP_PACKET_GET_TYPE = lambda h: (((h) >> 30) & 3) # type: ignore
|
||||
CP_PACKET_GET_COUNT = lambda h: (((h) >> 16) & 0x3FFF) # type: ignore
|
||||
CP_PACKET0_GET_REG = lambda h: ((h) & 0xFFFF) # type: ignore
|
||||
CP_PACKET3_GET_OPCODE = lambda h: (((h) >> 8) & 0xFF) # type: ignore
|
||||
PACKET0 = lambda reg,n: ((PACKET_TYPE0 << 30) | ((reg) & 0xFFFF) | ((n) & 0x3FFF) << 16) # type: ignore
|
||||
CP_PACKET2 = 0x80000000
|
||||
PACKET2_PAD_SHIFT = 0
|
||||
PACKET2_PAD_MASK = (0x3fffffff << 0)
|
||||
PACKET2 = lambda v: (CP_PACKET2 | REG_SET(PACKET2_PAD, (v))) # type: ignore
|
||||
PACKET3 = lambda op,n: ((PACKET_TYPE3 << 30) | (((op) & 0xFF) << 8) | ((n) & 0x3FFF) << 16) # type: ignore
|
||||
PACKET3_COMPUTE = lambda op,n: (PACKET3(op, n) | 1 << 1) # type: ignore
|
||||
PACKET3_NOP = 0x10
|
||||
PACKET3_SET_BASE = 0x11
|
||||
PACKET3_BASE_INDEX = lambda x: ((x) << 0) # type: ignore
|
||||
CE_PARTITION_BASE = 3
|
||||
PACKET3_CLEAR_STATE = 0x12
|
||||
PACKET3_INDEX_BUFFER_SIZE = 0x13
|
||||
PACKET3_DISPATCH_DIRECT = 0x15
|
||||
PACKET3_DISPATCH_INDIRECT = 0x16
|
||||
PACKET3_INDIRECT_BUFFER_END = 0x17
|
||||
PACKET3_INDIRECT_BUFFER_CNST_END = 0x19
|
||||
PACKET3_ATOMIC_GDS = 0x1D
|
||||
PACKET3_ATOMIC_MEM = 0x1E
|
||||
PACKET3_ATOMIC_MEM__ATOMIC = lambda x: ((((unsigned)(x)) & 0x7F) << 0) # type: ignore
|
||||
PACKET3_ATOMIC_MEM__COMMAND = lambda x: ((((unsigned)(x)) & 0xF) << 8) # type: ignore
|
||||
PACKET3_ATOMIC_MEM__CACHE_POLICY = lambda x: ((((unsigned)(x)) & 0x3) << 25) # type: ignore
|
||||
PACKET3_ATOMIC_MEM__ADDR_LO = lambda x: (((unsigned)(x))) # type: ignore
|
||||
PACKET3_ATOMIC_MEM__ADDR_HI = lambda x: (((unsigned)(x))) # type: ignore
|
||||
PACKET3_ATOMIC_MEM__SRC_DATA_LO = lambda x: (((unsigned)(x))) # type: ignore
|
||||
PACKET3_ATOMIC_MEM__SRC_DATA_HI = lambda x: (((unsigned)(x))) # type: ignore
|
||||
PACKET3_ATOMIC_MEM__CMP_DATA_LO = lambda x: (((unsigned)(x))) # type: ignore
|
||||
PACKET3_ATOMIC_MEM__CMP_DATA_HI = lambda x: (((unsigned)(x))) # type: ignore
|
||||
PACKET3_ATOMIC_MEM__LOOP_INTERVAL = lambda x: ((((unsigned)(x)) & 0x1FFF) << 0) # type: ignore
|
||||
PACKET3_ATOMIC_MEM__COMMAND__SINGLE_PASS_ATOMIC = 0
|
||||
PACKET3_ATOMIC_MEM__COMMAND__LOOP_UNTIL_COMPARE_SATISFIED = 1
|
||||
PACKET3_ATOMIC_MEM__COMMAND__WAIT_FOR_WRITE_CONFIRMATION = 2
|
||||
PACKET3_ATOMIC_MEM__COMMAND__SEND_AND_CONTINUE = 3
|
||||
PACKET3_ATOMIC_MEM__CACHE_POLICY__LRU = 0
|
||||
PACKET3_ATOMIC_MEM__CACHE_POLICY__STREAM = 1
|
||||
PACKET3_ATOMIC_MEM__CACHE_POLICY__NOA = 2
|
||||
PACKET3_ATOMIC_MEM__CACHE_POLICY__BYPASS = 3
|
||||
PACKET3_OCCLUSION_QUERY = 0x1F
|
||||
PACKET3_SET_PREDICATION = 0x20
|
||||
PACKET3_REG_RMW = 0x21
|
||||
PACKET3_COND_EXEC = 0x22
|
||||
PACKET3_PRED_EXEC = 0x23
|
||||
PACKET3_DRAW_INDIRECT = 0x24
|
||||
PACKET3_DRAW_INDEX_INDIRECT = 0x25
|
||||
PACKET3_INDEX_BASE = 0x26
|
||||
PACKET3_DRAW_INDEX_2 = 0x27
|
||||
PACKET3_CONTEXT_CONTROL = 0x28
|
||||
PACKET3_INDEX_TYPE = 0x2A
|
||||
PACKET3_DRAW_INDIRECT_MULTI = 0x2C
|
||||
PACKET3_DRAW_INDEX_AUTO = 0x2D
|
||||
PACKET3_NUM_INSTANCES = 0x2F
|
||||
PACKET3_DRAW_INDEX_MULTI_AUTO = 0x30
|
||||
PACKET3_INDIRECT_BUFFER_PRIV = 0x32
|
||||
PACKET3_INDIRECT_BUFFER_CNST = 0x33
|
||||
PACKET3_COND_INDIRECT_BUFFER_CNST = 0x33
|
||||
PACKET3_STRMOUT_BUFFER_UPDATE = 0x34
|
||||
PACKET3_DRAW_INDEX_OFFSET_2 = 0x35
|
||||
PACKET3_DRAW_PREAMBLE = 0x36
|
||||
PACKET3_WRITE_DATA = 0x37
|
||||
WRITE_DATA_DST_SEL = lambda x: ((x) << 8) # type: ignore
|
||||
WR_ONE_ADDR = (1 << 16)
|
||||
WR_CONFIRM = (1 << 20)
|
||||
WRITE_DATA_CACHE_POLICY = lambda x: ((x) << 25) # type: ignore
|
||||
WRITE_DATA_ENGINE_SEL = lambda x: ((x) << 30) # type: ignore
|
||||
PACKET3_WRITE_DATA__DST_SEL = lambda x: ((((unsigned)(x)) & 0xF) << 8) # type: ignore
|
||||
PACKET3_WRITE_DATA__ADDR_INCR = lambda x: ((((unsigned)(x)) & 0x1) << 16) # type: ignore
|
||||
PACKET3_WRITE_DATA__WR_CONFIRM = lambda x: ((((unsigned)(x)) & 0x1) << 20) # type: ignore
|
||||
PACKET3_WRITE_DATA__CACHE_POLICY = lambda x: ((((unsigned)(x)) & 0x3) << 25) # type: ignore
|
||||
PACKET3_WRITE_DATA__DST_MMREG_ADDR = lambda x: ((((unsigned)(x)) & 0x3FFFF) << 0) # type: ignore
|
||||
PACKET3_WRITE_DATA__DST_GDS_ADDR = lambda x: ((((unsigned)(x)) & 0xFFFF) << 0) # type: ignore
|
||||
PACKET3_WRITE_DATA__DST_MEM_ADDR_LO = lambda x: ((((unsigned)(x)) & 0x3FFFFFFF) << 2) # type: ignore
|
||||
PACKET3_WRITE_DATA__DST_MEM_ADDR_HI = lambda x: ((unsigned)(x)) # type: ignore
|
||||
PACKET3_WRITE_DATA__MODE = lambda x: ((((unsigned)(x)) & 0x1) << 21) # type: ignore
|
||||
PACKET3_WRITE_DATA__AID_ID = lambda x: ((((unsigned)(x)) & 0x3) << 22) # type: ignore
|
||||
PACKET3_WRITE_DATA__TEMPORAL = lambda x: ((((unsigned)(x)) & 0x3) << 24) # type: ignore
|
||||
PACKET3_WRITE_DATA__DST_MMREG_ADDR_LO = lambda x: ((unsigned)(x)) # type: ignore
|
||||
PACKET3_WRITE_DATA__DST_MMREG_ADDR_HI = lambda x: ((((unsigned)(x)) & 0xFF) << 0) # type: ignore
|
||||
PACKET3_WRITE_DATA__DST_SEL__MEM_MAPPED_REGISTER = 0
|
||||
PACKET3_WRITE_DATA__DST_SEL__TC_L2 = 2
|
||||
PACKET3_WRITE_DATA__DST_SEL__GDS = 3
|
||||
PACKET3_WRITE_DATA__DST_SEL__MEMORY = 5
|
||||
PACKET3_WRITE_DATA__DST_SEL__MEMORY_MAPPED_ADC_PERSISTENT_STATE = 6
|
||||
PACKET3_WRITE_DATA__ADDR_INCR__INCREMENT_ADDRESS = 0
|
||||
PACKET3_WRITE_DATA__ADDR_INCR__DO_NOT_INCREMENT_ADDRESS = 1
|
||||
PACKET3_WRITE_DATA__WR_CONFIRM__DO_NOT_WAIT_FOR_WRITE_CONFIRMATION = 0
|
||||
PACKET3_WRITE_DATA__WR_CONFIRM__WAIT_FOR_WRITE_CONFIRMATION = 1
|
||||
PACKET3_WRITE_DATA__MODE__PF_VF_DISABLED = 0
|
||||
PACKET3_WRITE_DATA__MODE__PF_VF_ENABLED = 1
|
||||
PACKET3_WRITE_DATA__TEMPORAL__RT = 0
|
||||
PACKET3_WRITE_DATA__TEMPORAL__NT = 1
|
||||
PACKET3_WRITE_DATA__TEMPORAL__HT = 2
|
||||
PACKET3_WRITE_DATA__TEMPORAL__LU = 3
|
||||
PACKET3_WRITE_DATA__CACHE_POLICY__LRU = 0
|
||||
PACKET3_WRITE_DATA__CACHE_POLICY__STREAM = 1
|
||||
PACKET3_WRITE_DATA__CACHE_POLICY__NOA = 2
|
||||
PACKET3_WRITE_DATA__CACHE_POLICY__BYPASS = 3
|
||||
PACKET3_DRAW_INDEX_INDIRECT_MULTI = 0x38
|
||||
PACKET3_MEM_SEMAPHORE = 0x39
|
||||
PACKET3_SEM_USE_MAILBOX = (0x1 << 16)
|
||||
PACKET3_SEM_SEL_SIGNAL_TYPE = (0x1 << 20)
|
||||
PACKET3_SEM_SEL_SIGNAL = (0x6 << 29)
|
||||
PACKET3_SEM_SEL_WAIT = (0x7 << 29)
|
||||
PACKET3_DRAW_INDEX_MULTI_INST = 0x3A
|
||||
PACKET3_COPY_DW = 0x3B
|
||||
PACKET3_WAIT_REG_MEM = 0x3C
|
||||
WAIT_REG_MEM_FUNCTION = lambda x: ((x) << 0) # type: ignore
|
||||
WAIT_REG_MEM_MEM_SPACE = lambda x: ((x) << 4) # type: ignore
|
||||
WAIT_REG_MEM_OPERATION = lambda x: ((x) << 6) # type: ignore
|
||||
WAIT_REG_MEM_ENGINE = lambda x: ((x) << 8) # type: ignore
|
||||
PACKET3_WAIT_REG_MEM__FUNCTION = lambda x: ((((unsigned)(x)) & 0x7) << 0) # type: ignore
|
||||
PACKET3_WAIT_REG_MEM__MEM_SPACE = lambda x: ((((unsigned)(x)) & 0x3) << 4) # type: ignore
|
||||
PACKET3_WAIT_REG_MEM__OPERATION = lambda x: ((((unsigned)(x)) & 0x3) << 6) # type: ignore
|
||||
PACKET3_WAIT_REG_MEM__MES_INTR_PIPE = lambda x: ((((unsigned)(x)) & 0x3) << 22) # type: ignore
|
||||
PACKET3_WAIT_REG_MEM__MES_ACTION = lambda x: ((((unsigned)(x)) & 0x1) << 24) # type: ignore
|
||||
PACKET3_WAIT_REG_MEM__CACHE_POLICY = lambda x: ((((unsigned)(x)) & 0x3) << 25) # type: ignore
|
||||
PACKET3_WAIT_REG_MEM__TEMPORAL = lambda x: ((((unsigned)(x)) & 0x3) << 25) # type: ignore
|
||||
PACKET3_WAIT_REG_MEM__MEM_POLL_ADDR_LO = lambda x: ((((unsigned)(x)) & 0x3FFFFFFF) << 2) # type: ignore
|
||||
PACKET3_WAIT_REG_MEM__REG_POLL_ADDR = lambda x: ((((unsigned)(x)) & 0X3FFFF) << 0) # type: ignore
|
||||
PACKET3_WAIT_REG_MEM__REG_WRITE_ADDR1 = lambda x: ((((unsigned)(x)) & 0X3FFFF) << 0) # type: ignore
|
||||
PACKET3_WAIT_REG_MEM__MEM_POLL_ADDR_HI = lambda x: ((unsigned)(x)) # type: ignore
|
||||
PACKET3_WAIT_REG_MEM__REG_WRITE_ADDR2 = lambda x: ((((unsigned)(x)) & 0x3FFFF) << 0) # type: ignore
|
||||
PACKET3_WAIT_REG_MEM__REFERENCE = lambda x: ((unsigned)(x)) # type: ignore
|
||||
PACKET3_WAIT_REG_MEM__MASK = lambda x: ((unsigned)(x)) # type: ignore
|
||||
PACKET3_WAIT_REG_MEM__POLL_INTERVAL = lambda x: ((((unsigned)(x)) & 0xFFFF) << 0) # type: ignore
|
||||
PACKET3_WAIT_REG_MEM__OPTIMIZE_ACE_OFFLOAD_MODE = lambda x: ((((unsigned)(x)) & 0x1) << 31) # type: ignore
|
||||
PACKET3_WAIT_REG_MEM__FUNCTION__ALWAYS_PASS = 0
|
||||
PACKET3_WAIT_REG_MEM__FUNCTION__LESS_THAN_REF_VALUE = 1
|
||||
PACKET3_WAIT_REG_MEM__FUNCTION__LESS_THAN_EQUAL_TO_THE_REF_VALUE = 2
|
||||
PACKET3_WAIT_REG_MEM__FUNCTION__EQUAL_TO_THE_REFERENCE_VALUE = 3
|
||||
PACKET3_WAIT_REG_MEM__FUNCTION__NOT_EQUAL_REFERENCE_VALUE = 4
|
||||
PACKET3_WAIT_REG_MEM__FUNCTION__GREATER_THAN_OR_EQUAL_REFERENCE_VALUE = 5
|
||||
PACKET3_WAIT_REG_MEM__FUNCTION__GREATER_THAN_REFERENCE_VALUE = 6
|
||||
PACKET3_WAIT_REG_MEM__MEM_SPACE__REGISTER_SPACE = 0
|
||||
PACKET3_WAIT_REG_MEM__MEM_SPACE__MEMORY_SPACE = 1
|
||||
PACKET3_WAIT_REG_MEM__OPERATION__WAIT_REG_MEM = 0
|
||||
PACKET3_WAIT_REG_MEM__OPERATION__WR_WAIT_WR_REG = 1
|
||||
PACKET3_WAIT_REG_MEM__OPERATION__WAIT_MEM_PREEMPTABLE = 3
|
||||
PACKET3_WAIT_REG_MEM__CACHE_POLICY__LRU = 0
|
||||
PACKET3_WAIT_REG_MEM__CACHE_POLICY__STREAM = 1
|
||||
PACKET3_WAIT_REG_MEM__CACHE_POLICY__NOA = 2
|
||||
PACKET3_WAIT_REG_MEM__CACHE_POLICY__BYPASS = 3
|
||||
PACKET3_WAIT_REG_MEM__TEMPORAL__RT = 0
|
||||
PACKET3_WAIT_REG_MEM__TEMPORAL__NT = 1
|
||||
PACKET3_WAIT_REG_MEM__TEMPORAL__HT = 2
|
||||
PACKET3_WAIT_REG_MEM__TEMPORAL__LU = 3
|
||||
PACKET3_INDIRECT_BUFFER = 0x3F
|
||||
INDIRECT_BUFFER_VALID = (1 << 23)
|
||||
INDIRECT_BUFFER_CACHE_POLICY = lambda x: ((x) << 28) # type: ignore
|
||||
INDIRECT_BUFFER_PRE_ENB = lambda x: ((x) << 21) # type: ignore
|
||||
INDIRECT_BUFFER_PRE_RESUME = lambda x: ((x) << 30) # type: ignore
|
||||
PACKET3_INDIRECT_BUFFER__IB_BASE_LO = lambda x: ((((unsigned)(x)) & 0x3FFFFFFF) << 2) # type: ignore
|
||||
PACKET3_INDIRECT_BUFFER__IB_BASE_HI = lambda x: ((unsigned)(x)) # type: ignore
|
||||
PACKET3_INDIRECT_BUFFER__IB_SIZE = lambda x: ((((unsigned)(x)) & 0xFFFFF) << 0) # type: ignore
|
||||
PACKET3_INDIRECT_BUFFER__CHAIN = lambda x: ((((unsigned)(x)) & 0x1) << 20) # type: ignore
|
||||
PACKET3_INDIRECT_BUFFER__OFFLOAD_POLLING = lambda x: ((((unsigned)(x)) & 0x1) << 21) # type: ignore
|
||||
PACKET3_INDIRECT_BUFFER__VALID = lambda x: ((((unsigned)(x)) & 0x1) << 23) # type: ignore
|
||||
PACKET3_INDIRECT_BUFFER__VMID = lambda x: ((((unsigned)(x)) & 0xF) << 24) # type: ignore
|
||||
PACKET3_INDIRECT_BUFFER__CACHE_POLICY = lambda x: ((((unsigned)(x)) & 0x3) << 28) # type: ignore
|
||||
PACKET3_INDIRECT_BUFFER__TEMPORAL = lambda x: ((((unsigned)(x)) & 0x3) << 28) # type: ignore
|
||||
PACKET3_INDIRECT_BUFFER__PRIV = lambda x: ((((unsigned)(x)) & 0x1) << 31) # type: ignore
|
||||
PACKET3_INDIRECT_BUFFER__TEMPORAL__RT = 0
|
||||
PACKET3_INDIRECT_BUFFER__TEMPORAL__NT = 1
|
||||
PACKET3_INDIRECT_BUFFER__TEMPORAL__HT = 2
|
||||
PACKET3_INDIRECT_BUFFER__TEMPORAL__LU = 3
|
||||
PACKET3_INDIRECT_BUFFER__CACHE_POLICY__LRU = 0
|
||||
PACKET3_INDIRECT_BUFFER__CACHE_POLICY__STREAM = 1
|
||||
PACKET3_INDIRECT_BUFFER__CACHE_POLICY__NOA = 2
|
||||
PACKET3_INDIRECT_BUFFER__CACHE_POLICY__BYPASS = 3
|
||||
PACKET3_COND_INDIRECT_BUFFER = 0x3F
|
||||
PACKET3_COPY_DATA = 0x40
|
||||
PACKET3_COPY_DATA__SRC_SEL = lambda x: ((((unsigned)(x)) & 0xF) << 0) # type: ignore
|
||||
PACKET3_COPY_DATA__DST_SEL = lambda x: ((((unsigned)(x)) & 0xF) << 8) # type: ignore
|
||||
PACKET3_COPY_DATA__SRC_CACHE_POLICY = lambda x: ((((unsigned)(x)) & 0x3) << 13) # type: ignore
|
||||
PACKET3_COPY_DATA__SRC_TEMPORAL = lambda x: ((((unsigned)(x)) & 0x3) << 13) # type: ignore
|
||||
PACKET3_COPY_DATA__COUNT_SEL = lambda x: ((((unsigned)(x)) & 0x1) << 16) # type: ignore
|
||||
PACKET3_COPY_DATA__WR_CONFIRM = lambda x: ((((unsigned)(x)) & 0x1) << 20) # type: ignore
|
||||
PACKET3_COPY_DATA__DST_CACHE_POLICY = lambda x: ((((unsigned)(x)) & 0x3) << 25) # type: ignore
|
||||
PACKET3_COPY_DATA__PQ_EXE_STATUS = lambda x: ((((unsigned)(x)) & 0x1) << 29) # type: ignore
|
||||
PACKET3_COPY_DATA__SRC_REG_OFFSET = lambda x: ((((unsigned)(x)) & 0x3FFFF) << 0) # type: ignore
|
||||
PACKET3_COPY_DATA__SRC_32B_ADDR_LO = lambda x: ((((unsigned)(x)) & 0x3FFFFFFF) << 2) # type: ignore
|
||||
PACKET3_COPY_DATA__SRC_64B_ADDR_LO = lambda x: ((((unsigned)(x)) & 0x1FFFFFFF) << 3) # type: ignore
|
||||
PACKET3_COPY_DATA__SRC_GDS_ADDR_LO = lambda x: ((((unsigned)(x)) & 0xFFFF) << 0) # type: ignore
|
||||
PACKET3_COPY_DATA__IMM_DATA = lambda x: ((unsigned)(x)) # type: ignore
|
||||
PACKET3_COPY_DATA__SRC_MEMTC_ADDR_HI = lambda x: ((unsigned)(x)) # type: ignore
|
||||
PACKET3_COPY_DATA__SRC_IMM_DATA = lambda x: ((unsigned)(x)) # type: ignore
|
||||
PACKET3_COPY_DATA__DST_REG_OFFSET = lambda x: ((((unsigned)(x)) & 0x3FFFF) << 0) # type: ignore
|
||||
PACKET3_COPY_DATA__DST_32B_ADDR_LO = lambda x: ((((unsigned)(x)) & 0x3FFFFFFF) << 2) # type: ignore
|
||||
PACKET3_COPY_DATA__DST_64B_ADDR_LO = lambda x: ((((unsigned)(x)) & 0x1FFFFFFF) << 3) # type: ignore
|
||||
PACKET3_COPY_DATA__DST_GDS_ADDR_LO = lambda x: ((((unsigned)(x)) & 0xFFFF) << 0) # type: ignore
|
||||
PACKET3_COPY_DATA__DST_ADDR_HI = lambda x: ((unsigned)(x)) # type: ignore
|
||||
PACKET3_COPY_DATA__MODE = lambda x: ((((unsigned)(x)) & 0x1) << 21) # type: ignore
|
||||
PACKET3_COPY_DATA__AID_ID = lambda x: ((((unsigned)(x)) & 0x3) << 23) # type: ignore
|
||||
PACKET3_COPY_DATA__DST_TEMPORAL = lambda x: ((((unsigned)(x)) & 0x3) << 25) # type: ignore
|
||||
PACKET3_COPY_DATA__SRC_REG_OFFSET_LO = lambda x: ((unsigned)(x)) # type: ignore
|
||||
PACKET3_COPY_DATA__SRC_REG_OFFSET_HI = lambda x: ((((unsigned)(x)) & 0xFF) << 0) # type: ignore
|
||||
PACKET3_COPY_DATA__DST_REG_OFFSET_LO = lambda x: ((unsigned)(x)) # type: ignore
|
||||
PACKET3_COPY_DATA__DST_REG_OFFSET_HI = lambda x: ((((unsigned)(x)) & 0xFF) << 0) # type: ignore
|
||||
PACKET3_COPY_DATA__SRC_SEL__MEM_MAPPED_REGISTER = 0
|
||||
PACKET3_COPY_DATA__SRC_SEL__TC_L2_OBSOLETE = 1
|
||||
PACKET3_COPY_DATA__SRC_SEL__TC_L2 = 2
|
||||
PACKET3_COPY_DATA__SRC_SEL__GDS = 3
|
||||
PACKET3_COPY_DATA__SRC_SEL__PERFCOUNTERS = 4
|
||||
PACKET3_COPY_DATA__SRC_SEL__IMMEDIATE_DATA = 5
|
||||
PACKET3_COPY_DATA__SRC_SEL__ATOMIC_RETURN_DATA = 6
|
||||
PACKET3_COPY_DATA__SRC_SEL__GDS_ATOMIC_RETURN_DATA0 = 7
|
||||
PACKET3_COPY_DATA__SRC_SEL__GDS_ATOMIC_RETURN_DATA1 = 8
|
||||
PACKET3_COPY_DATA__SRC_SEL__GPU_CLOCK_COUNT = 9
|
||||
PACKET3_COPY_DATA__SRC_SEL__SYSTEM_CLOCK_COUNT = 10
|
||||
PACKET3_COPY_DATA__DST_SEL__MEM_MAPPED_REGISTER = 0
|
||||
PACKET3_COPY_DATA__DST_SEL__TC_L2 = 2
|
||||
PACKET3_COPY_DATA__DST_SEL__GDS = 3
|
||||
PACKET3_COPY_DATA__DST_SEL__PERFCOUNTERS = 4
|
||||
PACKET3_COPY_DATA__DST_SEL__TC_L2_OBSOLETE = 5
|
||||
PACKET3_COPY_DATA__DST_SEL__MEM_MAPPED_REG_DC = 6
|
||||
PACKET3_COPY_DATA__SRC_TEMPORAL__RT = 0
|
||||
PACKET3_COPY_DATA__SRC_TEMPORAL__NT = 1
|
||||
PACKET3_COPY_DATA__SRC_TEMPORAL__HT = 2
|
||||
PACKET3_COPY_DATA__SRC_TEMPORAL__LU = 3
|
||||
PACKET3_COPY_DATA__SRC_CACHE_POLICY__LRU = 0
|
||||
PACKET3_COPY_DATA__SRC_CACHE_POLICY__STREAM = 1
|
||||
PACKET3_COPY_DATA__SRC_CACHE_POLICY__NOA = 2
|
||||
PACKET3_COPY_DATA__SRC_CACHE_POLICY__BYPASS = 3
|
||||
PACKET3_COPY_DATA__COUNT_SEL__32_BITS_OF_DATA = 0
|
||||
PACKET3_COPY_DATA__COUNT_SEL__64_BITS_OF_DATA = 1
|
||||
PACKET3_COPY_DATA__WR_CONFIRM__DO_NOT_WAIT_FOR_CONFIRMATION = 0
|
||||
PACKET3_COPY_DATA__WR_CONFIRM__WAIT_FOR_CONFIRMATION = 1
|
||||
PACKET3_COPY_DATA__MODE__PF_VF_DISABLED = 0
|
||||
PACKET3_COPY_DATA__MODE__PF_VF_ENABLED = 1
|
||||
PACKET3_COPY_DATA__DST_TEMPORAL__RT = 0
|
||||
PACKET3_COPY_DATA__DST_TEMPORAL__NT = 1
|
||||
PACKET3_COPY_DATA__DST_TEMPORAL__HT = 2
|
||||
PACKET3_COPY_DATA__DST_TEMPORAL__LU = 3
|
||||
PACKET3_COPY_DATA__DST_CACHE_POLICY__LRU = 0
|
||||
PACKET3_COPY_DATA__DST_CACHE_POLICY__STREAM = 1
|
||||
PACKET3_COPY_DATA__DST_CACHE_POLICY__NOA = 2
|
||||
PACKET3_COPY_DATA__DST_CACHE_POLICY__BYPASS = 3
|
||||
PACKET3_COPY_DATA__PQ_EXE_STATUS__DEFAULT = 0
|
||||
PACKET3_COPY_DATA__PQ_EXE_STATUS__PHASE_UPDATE = 1
|
||||
PACKET3_CP_DMA = 0x41
|
||||
PACKET3_PFP_SYNC_ME = 0x42
|
||||
PACKET3_SURFACE_SYNC = 0x43
|
||||
PACKET3_ME_INITIALIZE = 0x44
|
||||
PACKET3_COND_WRITE = 0x45
|
||||
PACKET3_EVENT_WRITE = 0x46
|
||||
EVENT_TYPE = lambda x: ((x) << 0) # type: ignore
|
||||
EVENT_INDEX = lambda x: ((x) << 8) # type: ignore
|
||||
PACKET3_EVENT_WRITE__EVENT_TYPE = lambda x: ((((unsigned)(x)) & 0x3F) << 0) # type: ignore
|
||||
PACKET3_EVENT_WRITE__EVENT_INDEX = lambda x: ((((unsigned)(x)) & 0xF) << 8) # type: ignore
|
||||
PACKET3_EVENT_WRITE__SAMP_PLST_CNTR_MODE = lambda x: ((((unsigned)(x)) & 0x3) << 29) # type: ignore
|
||||
PACKET3_EVENT_WRITE__OFFLOAD_ENABLE = lambda x: ((((unsigned)(x)) & 0x1) << 0) # type: ignore
|
||||
PACKET3_EVENT_WRITE__ADDRESS_LO = lambda x: ((((unsigned)(x)) & 0x1FFFFFFF) << 3) # type: ignore
|
||||
PACKET3_EVENT_WRITE__ADDRESS_HI = lambda x: ((unsigned)(x)) # type: ignore
|
||||
PACKET3_EVENT_WRITE__EVENT_INDEX__OTHER = 0
|
||||
PACKET3_EVENT_WRITE__EVENT_INDEX__SAMPLE_PIPELINESTAT = 2
|
||||
PACKET3_EVENT_WRITE__EVENT_INDEX__CS_PARTIAL_FLUSH = 4
|
||||
PACKET3_EVENT_WRITE__EVENT_INDEX__SAMPLE_STREAMOUTSTATS = 8
|
||||
PACKET3_EVENT_WRITE__EVENT_INDEX__SAMPLE_STREAMOUTSTATS1 = 9
|
||||
PACKET3_EVENT_WRITE__EVENT_INDEX__SAMPLE_STREAMOUTSTATS2 = 10
|
||||
PACKET3_EVENT_WRITE__EVENT_INDEX__SAMPLE_STREAMOUTSTATS3 = 11
|
||||
PACKET3_EVENT_WRITE__SAMP_PLST_CNTR_MODE__LEGACY_MODE = 0
|
||||
PACKET3_EVENT_WRITE__SAMP_PLST_CNTR_MODE__MIXED_MODE1 = 1
|
||||
PACKET3_EVENT_WRITE__SAMP_PLST_CNTR_MODE__NEW_MODE = 2
|
||||
PACKET3_EVENT_WRITE__SAMP_PLST_CNTR_MODE__MIXED_MODE3 = 3
|
||||
PACKET3_EVENT_WRITE_EOP = 0x47
|
||||
PACKET3_EVENT_WRITE_EOS = 0x48
|
||||
PACKET3_RELEASE_MEM = 0x49
|
||||
PACKET3_RELEASE_MEM_EVENT_TYPE = lambda x: ((x) << 0) # type: ignore
|
||||
PACKET3_RELEASE_MEM_EVENT_INDEX = lambda x: ((x) << 8) # type: ignore
|
||||
PACKET3_RELEASE_MEM_GCR_GLM_WB = (1 << 12)
|
||||
PACKET3_RELEASE_MEM_GCR_GLM_INV = (1 << 13)
|
||||
PACKET3_RELEASE_MEM_GCR_GLV_INV = (1 << 14)
|
||||
PACKET3_RELEASE_MEM_GCR_GL1_INV = (1 << 15)
|
||||
PACKET3_RELEASE_MEM_GCR_GL2_US = (1 << 16)
|
||||
PACKET3_RELEASE_MEM_GCR_GL2_RANGE = (1 << 17)
|
||||
PACKET3_RELEASE_MEM_GCR_GL2_DISCARD = (1 << 19)
|
||||
PACKET3_RELEASE_MEM_GCR_GL2_INV = (1 << 20)
|
||||
PACKET3_RELEASE_MEM_GCR_GL2_WB = (1 << 21)
|
||||
PACKET3_RELEASE_MEM_GCR_SEQ = (1 << 22)
|
||||
PACKET3_RELEASE_MEM_CACHE_POLICY = lambda x: ((x) << 25) # type: ignore
|
||||
PACKET3_RELEASE_MEM_EXECUTE = (1 << 28)
|
||||
PACKET3_RELEASE_MEM_DATA_SEL = lambda x: ((x) << 29) # type: ignore
|
||||
PACKET3_RELEASE_MEM_INT_SEL = lambda x: ((x) << 24) # type: ignore
|
||||
PACKET3_RELEASE_MEM_DST_SEL = lambda x: ((x) << 16) # type: ignore
|
||||
PACKET3_PREAMBLE_CNTL = 0x4A
|
||||
PACKET3_PREAMBLE_BEGIN_CLEAR_STATE = (2 << 28)
|
||||
PACKET3_PREAMBLE_END_CLEAR_STATE = (3 << 28)
|
||||
PACKET3_DMA_DATA = 0x50
|
||||
PACKET3_DMA_DATA_ENGINE = lambda x: ((x) << 0) # type: ignore
|
||||
PACKET3_DMA_DATA_SRC_CACHE_POLICY = lambda x: ((x) << 13) # type: ignore
|
||||
PACKET3_DMA_DATA_DST_SEL = lambda x: ((x) << 20) # type: ignore
|
||||
PACKET3_DMA_DATA_DST_CACHE_POLICY = lambda x: ((x) << 25) # type: ignore
|
||||
PACKET3_DMA_DATA_SRC_SEL = lambda x: ((x) << 29) # type: ignore
|
||||
PACKET3_DMA_DATA_CP_SYNC = (1 << 31)
|
||||
PACKET3_DMA_DATA_CMD_SAS = (1 << 26)
|
||||
PACKET3_DMA_DATA_CMD_DAS = (1 << 27)
|
||||
PACKET3_DMA_DATA_CMD_SAIC = (1 << 28)
|
||||
PACKET3_DMA_DATA_CMD_DAIC = (1 << 29)
|
||||
PACKET3_DMA_DATA_CMD_RAW_WAIT = (1 << 30)
|
||||
PACKET3_CONTEXT_REG_RMW = 0x51
|
||||
PACKET3_GFX_CNTX_UPDATE = 0x52
|
||||
PACKET3_BLK_CNTX_UPDATE = 0x53
|
||||
PACKET3_INCR_UPDT_STATE = 0x55
|
||||
PACKET3_ACQUIRE_MEM = 0x58
|
||||
PACKET3_ACQUIRE_MEM_GCR_CNTL_GLI_INV = lambda x: ((x) << 0) # type: ignore
|
||||
PACKET3_ACQUIRE_MEM_GCR_CNTL_GL1_RANGE = lambda x: ((x) << 2) # type: ignore
|
||||
PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_WB = lambda x: ((x) << 4) # type: ignore
|
||||
PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_INV = lambda x: ((x) << 5) # type: ignore
|
||||
PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_WB = lambda x: ((x) << 6) # type: ignore
|
||||
PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_INV = lambda x: ((x) << 7) # type: ignore
|
||||
PACKET3_ACQUIRE_MEM_GCR_CNTL_GLV_INV = lambda x: ((x) << 8) # type: ignore
|
||||
PACKET3_ACQUIRE_MEM_GCR_CNTL_GL1_INV = lambda x: ((x) << 9) # type: ignore
|
||||
PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_US = lambda x: ((x) << 10) # type: ignore
|
||||
PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_RANGE = lambda x: ((x) << 11) # type: ignore
|
||||
PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_DISCARD = lambda x: ((x) << 13) # type: ignore
|
||||
PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_INV = lambda x: ((x) << 14) # type: ignore
|
||||
PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_WB = lambda x: ((x) << 15) # type: ignore
|
||||
PACKET3_ACQUIRE_MEM_GCR_CNTL_SEQ = lambda x: ((x) << 16) # type: ignore
|
||||
PACKET3_ACQUIRE_MEM_GCR_RANGE_IS_PA = (1 << 18)
|
||||
PACKET3_ACQUIRE_MEM__COHER_SIZE = lambda x: ((unsigned)(x)) # type: ignore
|
||||
PACKET3_ACQUIRE_MEM__COHER_SIZE_HI = lambda x: ((((unsigned)(x)) & 0xFF) << 0) # type: ignore
|
||||
PACKET3_ACQUIRE_MEM__COHER_BASE_LO = lambda x: ((unsigned)(x)) # type: ignore
|
||||
PACKET3_ACQUIRE_MEM__COHER_BASE_HI = lambda x: ((((unsigned)(x)) & 0xFFFFFF) << 0) # type: ignore
|
||||
PACKET3_ACQUIRE_MEM__POLL_INTERVAL = lambda x: ((((unsigned)(x)) & 0xFFFF) << 0) # type: ignore
|
||||
PACKET3_ACQUIRE_MEM__GCR_CNTL = lambda x: ((((unsigned)(x)) & 0x7FFFF) << 0) # type: ignore
|
||||
PACKET3_REWIND = 0x59
|
||||
PACKET3_INTERRUPT = 0x5A
|
||||
PACKET3_GEN_PDEPTE = 0x5B
|
||||
PACKET3_INDIRECT_BUFFER_PASID = 0x5C
|
||||
PACKET3_PRIME_UTCL2 = 0x5D
|
||||
PACKET3_LOAD_UCONFIG_REG = 0x5E
|
||||
PACKET3_LOAD_SH_REG = 0x5F
|
||||
PACKET3_LOAD_CONFIG_REG = 0x60
|
||||
PACKET3_LOAD_CONTEXT_REG = 0x61
|
||||
PACKET3_LOAD_COMPUTE_STATE = 0x62
|
||||
PACKET3_LOAD_SH_REG_INDEX = 0x63
|
||||
PACKET3_SET_CONFIG_REG = 0x68
|
||||
PACKET3_SET_CONFIG_REG_START = 0x00002000
|
||||
PACKET3_SET_CONFIG_REG_END = 0x00002c00
|
||||
PACKET3_SET_CONTEXT_REG = 0x69
|
||||
PACKET3_SET_CONTEXT_REG_START = 0x0000a000
|
||||
PACKET3_SET_CONTEXT_REG_END = 0x0000a400
|
||||
PACKET3_SET_CONTEXT_REG_INDEX = 0x6A
|
||||
PACKET3_SET_VGPR_REG_DI_MULTI = 0x71
|
||||
PACKET3_SET_SH_REG_DI = 0x72
|
||||
PACKET3_SET_CONTEXT_REG_INDIRECT = 0x73
|
||||
PACKET3_SET_SH_REG_DI_MULTI = 0x74
|
||||
PACKET3_GFX_PIPE_LOCK = 0x75
|
||||
PACKET3_SET_SH_REG = 0x76
|
||||
PACKET3_SET_SH_REG_START = 0x00002c00
|
||||
PACKET3_SET_SH_REG_END = 0x00003000
|
||||
PACKET3_SET_SH_REG__REG_OFFSET = lambda x: ((((unsigned)(x)) & 0xFFFF) << 0) # type: ignore
|
||||
PACKET3_SET_SH_REG__VMID_SHIFT = lambda x: ((((unsigned)(x)) & 0x1F) << 23) # type: ignore
|
||||
PACKET3_SET_SH_REG__INDEX = lambda x: ((((unsigned)(x)) & 0xF) << 28) # type: ignore
|
||||
PACKET3_SET_SH_REG__INDEX__DEFAULT = 0
|
||||
PACKET3_SET_SH_REG__INDEX__INSERT_VMID = 1
|
||||
PACKET3_SET_SH_REG_OFFSET = 0x77
|
||||
PACKET3_SET_QUEUE_REG = 0x78
|
||||
PACKET3_SET_UCONFIG_REG = 0x79
|
||||
PACKET3_SET_UCONFIG_REG_START = 0x0000c000
|
||||
PACKET3_SET_UCONFIG_REG_END = 0x0000c400
|
||||
PACKET3_SET_UCONFIG_REG__REG_OFFSET = lambda x: ((((unsigned)(x)) & 0xFFFF) << 0) # type: ignore
|
||||
PACKET3_SET_UCONFIG_REG_INDEX = 0x7A
|
||||
PACKET3_FORWARD_HEADER = 0x7C
|
||||
PACKET3_SCRATCH_RAM_WRITE = 0x7D
|
||||
PACKET3_SCRATCH_RAM_READ = 0x7E
|
||||
PACKET3_LOAD_CONST_RAM = 0x80
|
||||
PACKET3_WRITE_CONST_RAM = 0x81
|
||||
PACKET3_DUMP_CONST_RAM = 0x83
|
||||
PACKET3_INCREMENT_CE_COUNTER = 0x84
|
||||
PACKET3_INCREMENT_DE_COUNTER = 0x85
|
||||
PACKET3_WAIT_ON_CE_COUNTER = 0x86
|
||||
PACKET3_WAIT_ON_DE_COUNTER_DIFF = 0x88
|
||||
PACKET3_SWITCH_BUFFER = 0x8B
|
||||
PACKET3_DISPATCH_DRAW_PREAMBLE = 0x8C
|
||||
PACKET3_DISPATCH_DRAW_PREAMBLE_ACE = 0x8C
|
||||
PACKET3_DISPATCH_DRAW = 0x8D
|
||||
PACKET3_DISPATCH_DRAW_ACE = 0x8D
|
||||
PACKET3_GET_LOD_STATS = 0x8E
|
||||
PACKET3_DRAW_MULTI_PREAMBLE = 0x8F
|
||||
PACKET3_FRAME_CONTROL = 0x90
|
||||
FRAME_TMZ = (1 << 0)
|
||||
FRAME_CMD = lambda x: ((x) << 28) # type: ignore
|
||||
PACKET3_INDEX_ATTRIBUTES_INDIRECT = 0x91
|
||||
PACKET3_WAIT_REG_MEM64 = 0x93
|
||||
PACKET3_COND_PREEMPT = 0x94
|
||||
PACKET3_HDP_FLUSH = 0x95
|
||||
PACKET3_COPY_DATA_RB = 0x96
|
||||
PACKET3_INVALIDATE_TLBS = 0x98
|
||||
PACKET3_INVALIDATE_TLBS_DST_SEL = lambda x: ((x) << 0) # type: ignore
|
||||
PACKET3_INVALIDATE_TLBS_ALL_HUB = lambda x: ((x) << 4) # type: ignore
|
||||
PACKET3_INVALIDATE_TLBS_PASID = lambda x: ((x) << 5) # type: ignore
|
||||
PACKET3_INVALIDATE_TLBS_FLUSH_TYPE = lambda x: ((x) << 29) # type: ignore
|
||||
PACKET3_AQL_PACKET = 0x99
|
||||
PACKET3_DMA_DATA_FILL_MULTI = 0x9A
|
||||
PACKET3_SET_SH_REG_INDEX = 0x9B
|
||||
PACKET3_DRAW_INDIRECT_COUNT_MULTI = 0x9C
|
||||
PACKET3_DRAW_INDEX_INDIRECT_COUNT_MULTI = 0x9D
|
||||
PACKET3_DUMP_CONST_RAM_OFFSET = 0x9E
|
||||
PACKET3_LOAD_CONTEXT_REG_INDEX = 0x9F
|
||||
PACKET3_SET_RESOURCES = 0xA0
|
||||
PACKET3_SET_RESOURCES_VMID_MASK = lambda x: ((x) << 0) # type: ignore
|
||||
PACKET3_SET_RESOURCES_UNMAP_LATENTY = lambda x: ((x) << 16) # type: ignore
|
||||
PACKET3_SET_RESOURCES_QUEUE_TYPE = lambda x: ((x) << 29) # type: ignore
|
||||
PACKET3_MAP_PROCESS = 0xA1
|
||||
PACKET3_MAP_QUEUES = 0xA2
|
||||
PACKET3_MAP_QUEUES_QUEUE_SEL = lambda x: ((x) << 4) # type: ignore
|
||||
PACKET3_MAP_QUEUES_VMID = lambda x: ((x) << 8) # type: ignore
|
||||
PACKET3_MAP_QUEUES_QUEUE = lambda x: ((x) << 13) # type: ignore
|
||||
PACKET3_MAP_QUEUES_PIPE = lambda x: ((x) << 16) # type: ignore
|
||||
PACKET3_MAP_QUEUES_ME = lambda x: ((x) << 18) # type: ignore
|
||||
PACKET3_MAP_QUEUES_QUEUE_TYPE = lambda x: ((x) << 21) # type: ignore
|
||||
PACKET3_MAP_QUEUES_ALLOC_FORMAT = lambda x: ((x) << 24) # type: ignore
|
||||
PACKET3_MAP_QUEUES_ENGINE_SEL = lambda x: ((x) << 26) # type: ignore
|
||||
PACKET3_MAP_QUEUES_NUM_QUEUES = lambda x: ((x) << 29) # type: ignore
|
||||
PACKET3_MAP_QUEUES_CHECK_DISABLE = lambda x: ((x) << 1) # type: ignore
|
||||
PACKET3_MAP_QUEUES_DOORBELL_OFFSET = lambda x: ((x) << 2) # type: ignore
|
||||
PACKET3_UNMAP_QUEUES = 0xA3
|
||||
PACKET3_UNMAP_QUEUES_ACTION = lambda x: ((x) << 0) # type: ignore
|
||||
PACKET3_UNMAP_QUEUES_QUEUE_SEL = lambda x: ((x) << 4) # type: ignore
|
||||
PACKET3_UNMAP_QUEUES_ENGINE_SEL = lambda x: ((x) << 26) # type: ignore
|
||||
PACKET3_UNMAP_QUEUES_NUM_QUEUES = lambda x: ((x) << 29) # type: ignore
|
||||
PACKET3_UNMAP_QUEUES_PASID = lambda x: ((x) << 0) # type: ignore
|
||||
PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0 = lambda x: ((x) << 2) # type: ignore
|
||||
PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET1 = lambda x: ((x) << 2) # type: ignore
|
||||
PACKET3_UNMAP_QUEUES_RB_WPTR = lambda x: ((x) << 0) # type: ignore
|
||||
PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET2 = lambda x: ((x) << 2) # type: ignore
|
||||
PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET3 = lambda x: ((x) << 2) # type: ignore
|
||||
PACKET3_QUERY_STATUS = 0xA4
|
||||
PACKET3_QUERY_STATUS_CONTEXT_ID = lambda x: ((x) << 0) # type: ignore
|
||||
PACKET3_QUERY_STATUS_INTERRUPT_SEL = lambda x: ((x) << 28) # type: ignore
|
||||
PACKET3_QUERY_STATUS_COMMAND = lambda x: ((x) << 30) # type: ignore
|
||||
PACKET3_QUERY_STATUS_PASID = lambda x: ((x) << 0) # type: ignore
|
||||
PACKET3_QUERY_STATUS_DOORBELL_OFFSET = lambda x: ((x) << 2) # type: ignore
|
||||
PACKET3_QUERY_STATUS_ENG_SEL = lambda x: ((x) << 25) # type: ignore
|
||||
PACKET3_RUN_LIST = 0xA5
|
||||
PACKET3_MAP_PROCESS_VM = 0xA6
|
||||
PACKET3_RUN_CLEANER_SHADER = 0xD2
|
||||
PACKET3_SET_Q_PREEMPTION_MODE = 0xF0
|
||||
PACKET3_SET_Q_PREEMPTION_MODE_IB_VMID = lambda x: ((x) << 0) # type: ignore
|
||||
PACKET3_SET_Q_PREEMPTION_MODE_INIT_SHADOW_MEM = (1 << 0)
|
||||
412
tinygrad_repo/tinygrad/runtime/autogen/am/pm4_soc15.py
Normal file
412
tinygrad_repo/tinygrad/runtime/autogen/am/pm4_soc15.py
Normal file
@@ -0,0 +1,412 @@
|
||||
# mypy: disable-error-code="empty-body"
|
||||
from __future__ import annotations
|
||||
import ctypes
|
||||
from typing import Literal, TypeAlias
|
||||
from tinygrad.runtime.support.c import _IO, _IOW, _IOR, _IOWR
|
||||
from tinygrad.runtime.support import c
|
||||
class union_PM4_MES_TYPE_3_HEADER(c.Struct): pass
|
||||
enum_mes_set_resources_queue_type_enum: dict[int, str] = {(queue_type__mes_set_resources__kernel_interface_queue_kiq:=0): 'queue_type__mes_set_resources__kernel_interface_queue_kiq', (queue_type__mes_set_resources__hsa_interface_queue_hiq:=1): 'queue_type__mes_set_resources__hsa_interface_queue_hiq', (queue_type__mes_set_resources__hsa_debug_interface_queue:=4): 'queue_type__mes_set_resources__hsa_debug_interface_queue'}
|
||||
class struct_pm4_mes_set_resources(c.Struct): pass
|
||||
class struct_pm4_mes_runlist(c.Struct): pass
|
||||
class struct_pm4_mes_map_process(c.Struct): pass
|
||||
class struct_PM4_MES_MAP_PROCESS_VM(c.Struct): pass
|
||||
enum_mes_map_queues_queue_sel_enum: dict[int, str] = {(queue_sel__mes_map_queues__map_to_specified_queue_slots_vi:=0): 'queue_sel__mes_map_queues__map_to_specified_queue_slots_vi', (queue_sel__mes_map_queues__map_to_hws_determined_queue_slots_vi:=1): 'queue_sel__mes_map_queues__map_to_hws_determined_queue_slots_vi'}
|
||||
enum_mes_map_queues_queue_type_enum: dict[int, str] = {(queue_type__mes_map_queues__normal_compute_vi:=0): 'queue_type__mes_map_queues__normal_compute_vi', (queue_type__mes_map_queues__debug_interface_queue_vi:=1): 'queue_type__mes_map_queues__debug_interface_queue_vi', (queue_type__mes_map_queues__normal_latency_static_queue_vi:=2): 'queue_type__mes_map_queues__normal_latency_static_queue_vi', (queue_type__mes_map_queues__low_latency_static_queue_vi:=3): 'queue_type__mes_map_queues__low_latency_static_queue_vi'}
|
||||
enum_mes_map_queues_engine_sel_enum: dict[int, str] = {(engine_sel__mes_map_queues__compute_vi:=0): 'engine_sel__mes_map_queues__compute_vi', (engine_sel__mes_map_queues__sdma0_vi:=2): 'engine_sel__mes_map_queues__sdma0_vi', (engine_sel__mes_map_queues__sdma1_vi:=3): 'engine_sel__mes_map_queues__sdma1_vi'}
|
||||
enum_mes_map_queues_extended_engine_sel_enum: dict[int, str] = {(extended_engine_sel__mes_map_queues__legacy_engine_sel:=0): 'extended_engine_sel__mes_map_queues__legacy_engine_sel', (extended_engine_sel__mes_map_queues__sdma0_to_7_sel:=1): 'extended_engine_sel__mes_map_queues__sdma0_to_7_sel', (extended_engine_sel__mes_map_queues__sdma8_to_15_sel:=2): 'extended_engine_sel__mes_map_queues__sdma8_to_15_sel'}
|
||||
class struct_pm4_mes_map_queues(c.Struct): pass
|
||||
enum_mes_query_status_interrupt_sel_enum: dict[int, str] = {(interrupt_sel__mes_query_status__completion_status:=0): 'interrupt_sel__mes_query_status__completion_status', (interrupt_sel__mes_query_status__process_status:=1): 'interrupt_sel__mes_query_status__process_status', (interrupt_sel__mes_query_status__queue_status:=2): 'interrupt_sel__mes_query_status__queue_status'}
|
||||
enum_mes_query_status_command_enum: dict[int, str] = {(command__mes_query_status__interrupt_only:=0): 'command__mes_query_status__interrupt_only', (command__mes_query_status__fence_only_immediate:=1): 'command__mes_query_status__fence_only_immediate', (command__mes_query_status__fence_only_after_write_ack:=2): 'command__mes_query_status__fence_only_after_write_ack', (command__mes_query_status__fence_wait_for_write_ack_send_interrupt:=3): 'command__mes_query_status__fence_wait_for_write_ack_send_interrupt'}
|
||||
enum_mes_query_status_engine_sel_enum: dict[int, str] = {(engine_sel__mes_query_status__compute:=0): 'engine_sel__mes_query_status__compute', (engine_sel__mes_query_status__sdma0_queue:=2): 'engine_sel__mes_query_status__sdma0_queue', (engine_sel__mes_query_status__sdma1_queue:=3): 'engine_sel__mes_query_status__sdma1_queue'}
|
||||
class struct_pm4_mes_query_status(c.Struct): pass
|
||||
enum_mes_unmap_queues_action_enum: dict[int, str] = {(action__mes_unmap_queues__preempt_queues:=0): 'action__mes_unmap_queues__preempt_queues', (action__mes_unmap_queues__reset_queues:=1): 'action__mes_unmap_queues__reset_queues', (action__mes_unmap_queues__disable_process_queues:=2): 'action__mes_unmap_queues__disable_process_queues', (action__mes_unmap_queues__reserved:=3): 'action__mes_unmap_queues__reserved'}
|
||||
enum_mes_unmap_queues_queue_sel_enum: dict[int, str] = {(queue_sel__mes_unmap_queues__perform_request_on_specified_queues:=0): 'queue_sel__mes_unmap_queues__perform_request_on_specified_queues', (queue_sel__mes_unmap_queues__perform_request_on_pasid_queues:=1): 'queue_sel__mes_unmap_queues__perform_request_on_pasid_queues', (queue_sel__mes_unmap_queues__unmap_all_queues:=2): 'queue_sel__mes_unmap_queues__unmap_all_queues', (queue_sel__mes_unmap_queues__unmap_all_non_static_queues:=3): 'queue_sel__mes_unmap_queues__unmap_all_non_static_queues'}
|
||||
enum_mes_unmap_queues_engine_sel_enum: dict[int, str] = {(engine_sel__mes_unmap_queues__compute:=0): 'engine_sel__mes_unmap_queues__compute', (engine_sel__mes_unmap_queues__sdma0:=2): 'engine_sel__mes_unmap_queues__sdma0', (engine_sel__mes_unmap_queues__sdmal:=3): 'engine_sel__mes_unmap_queues__sdmal'}
|
||||
enum_mes_unmap_queues_extended_engine_sel_enum: dict[int, str] = {(extended_engine_sel__mes_unmap_queues__legacy_engine_sel:=0): 'extended_engine_sel__mes_unmap_queues__legacy_engine_sel', (extended_engine_sel__mes_unmap_queues__sdma0_to_7_sel:=1): 'extended_engine_sel__mes_unmap_queues__sdma0_to_7_sel'}
|
||||
class struct_pm4_mes_unmap_queues(c.Struct): pass
|
||||
enum_mec_release_mem_event_index_enum: dict[int, str] = {(event_index__mec_release_mem__end_of_pipe:=5): 'event_index__mec_release_mem__end_of_pipe', (event_index__mec_release_mem__shader_done:=6): 'event_index__mec_release_mem__shader_done'}
|
||||
enum_mec_release_mem_cache_policy_enum: dict[int, str] = {(cache_policy__mec_release_mem__lru:=0): 'cache_policy__mec_release_mem__lru', (cache_policy__mec_release_mem__stream:=1): 'cache_policy__mec_release_mem__stream'}
|
||||
enum_mec_release_mem_pq_exe_status_enum: dict[int, str] = {(pq_exe_status__mec_release_mem__default:=0): 'pq_exe_status__mec_release_mem__default', (pq_exe_status__mec_release_mem__phase_update:=1): 'pq_exe_status__mec_release_mem__phase_update'}
|
||||
enum_mec_release_mem_dst_sel_enum: dict[int, str] = {(dst_sel__mec_release_mem__memory_controller:=0): 'dst_sel__mec_release_mem__memory_controller', (dst_sel__mec_release_mem__tc_l2:=1): 'dst_sel__mec_release_mem__tc_l2', (dst_sel__mec_release_mem__queue_write_pointer_register:=2): 'dst_sel__mec_release_mem__queue_write_pointer_register', (dst_sel__mec_release_mem__queue_write_pointer_poll_mask_bit:=3): 'dst_sel__mec_release_mem__queue_write_pointer_poll_mask_bit'}
|
||||
enum_mec_release_mem_int_sel_enum: dict[int, str] = {(int_sel__mec_release_mem__none:=0): 'int_sel__mec_release_mem__none', (int_sel__mec_release_mem__send_interrupt_only:=1): 'int_sel__mec_release_mem__send_interrupt_only', (int_sel__mec_release_mem__send_interrupt_after_write_confirm:=2): 'int_sel__mec_release_mem__send_interrupt_after_write_confirm', (int_sel__mec_release_mem__send_data_after_write_confirm:=3): 'int_sel__mec_release_mem__send_data_after_write_confirm', (int_sel__mec_release_mem__unconditionally_send_int_ctxid:=4): 'int_sel__mec_release_mem__unconditionally_send_int_ctxid', (int_sel__mec_release_mem__conditionally_send_int_ctxid_based_on_32_bit_compare:=5): 'int_sel__mec_release_mem__conditionally_send_int_ctxid_based_on_32_bit_compare', (int_sel__mec_release_mem__conditionally_send_int_ctxid_based_on_64_bit_compare:=6): 'int_sel__mec_release_mem__conditionally_send_int_ctxid_based_on_64_bit_compare'}
|
||||
enum_mec_release_mem_data_sel_enum: dict[int, str] = {(data_sel__mec_release_mem__none:=0): 'data_sel__mec_release_mem__none', (data_sel__mec_release_mem__send_32_bit_low:=1): 'data_sel__mec_release_mem__send_32_bit_low', (data_sel__mec_release_mem__send_64_bit_data:=2): 'data_sel__mec_release_mem__send_64_bit_data', (data_sel__mec_release_mem__send_gpu_clock_counter:=3): 'data_sel__mec_release_mem__send_gpu_clock_counter', (data_sel__mec_release_mem__send_cp_perfcounter_hi_lo:=4): 'data_sel__mec_release_mem__send_cp_perfcounter_hi_lo', (data_sel__mec_release_mem__store_gds_data_to_memory:=5): 'data_sel__mec_release_mem__store_gds_data_to_memory'}
|
||||
class struct_pm4_mec_release_mem(c.Struct): pass
|
||||
enum_WRITE_DATA_dst_sel_enum: dict[int, str] = {(dst_sel___write_data__mem_mapped_register:=0): 'dst_sel___write_data__mem_mapped_register', (dst_sel___write_data__tc_l2:=2): 'dst_sel___write_data__tc_l2', (dst_sel___write_data__gds:=3): 'dst_sel___write_data__gds', (dst_sel___write_data__memory:=5): 'dst_sel___write_data__memory', (dst_sel___write_data__memory_mapped_adc_persistent_state:=6): 'dst_sel___write_data__memory_mapped_adc_persistent_state'}
|
||||
enum_WRITE_DATA_addr_incr_enum: dict[int, str] = {(addr_incr___write_data__increment_address:=0): 'addr_incr___write_data__increment_address', (addr_incr___write_data__do_not_increment_address:=1): 'addr_incr___write_data__do_not_increment_address'}
|
||||
enum_WRITE_DATA_wr_confirm_enum: dict[int, str] = {(wr_confirm___write_data__do_not_wait_for_write_confirmation:=0): 'wr_confirm___write_data__do_not_wait_for_write_confirmation', (wr_confirm___write_data__wait_for_write_confirmation:=1): 'wr_confirm___write_data__wait_for_write_confirmation'}
|
||||
enum_WRITE_DATA_cache_policy_enum: dict[int, str] = {(cache_policy___write_data__lru:=0): 'cache_policy___write_data__lru', (cache_policy___write_data__stream:=1): 'cache_policy___write_data__stream'}
|
||||
class struct_pm4_mec_write_data_mmio(c.Struct): pass
|
||||
_anonenum0: dict[int, str] = {(CACHE_FLUSH_AND_INV_TS_EVENT:=20): 'CACHE_FLUSH_AND_INV_TS_EVENT'}
|
||||
GFX9_NUM_GFX_RINGS = 1
|
||||
GFX9_NUM_COMPUTE_RINGS = 8
|
||||
PACKET_TYPE0 = 0
|
||||
PACKET_TYPE1 = 1
|
||||
PACKET_TYPE2 = 2
|
||||
PACKET_TYPE3 = 3
|
||||
CP_PACKET_GET_TYPE = lambda h: (((h) >> 30) & 3) # type: ignore
|
||||
CP_PACKET_GET_COUNT = lambda h: (((h) >> 16) & 0x3FFF) # type: ignore
|
||||
CP_PACKET0_GET_REG = lambda h: ((h) & 0xFFFF) # type: ignore
|
||||
CP_PACKET3_GET_OPCODE = lambda h: (((h) >> 8) & 0xFF) # type: ignore
|
||||
PACKET0 = lambda reg,n: ((PACKET_TYPE0 << 30) | ((reg) & 0xFFFF) | ((n) & 0x3FFF) << 16) # type: ignore
|
||||
CP_PACKET2 = 0x80000000
|
||||
PACKET2_PAD_SHIFT = 0
|
||||
PACKET2_PAD_MASK = (0x3fffffff << 0)
|
||||
PACKET2 = lambda v: (CP_PACKET2 | REG_SET(PACKET2_PAD, (v))) # type: ignore
|
||||
PACKET3 = lambda op,n: ((PACKET_TYPE3 << 30) | (((op) & 0xFF) << 8) | ((n) & 0x3FFF) << 16) # type: ignore
|
||||
PACKET3_COMPUTE = lambda op,n: (PACKET3(op, n) | 1 << 1) # type: ignore
|
||||
PACKETJ_CONDITION_CHECK0 = 0
|
||||
PACKETJ_CONDITION_CHECK1 = 1
|
||||
PACKETJ_CONDITION_CHECK2 = 2
|
||||
PACKETJ_CONDITION_CHECK3 = 3
|
||||
PACKETJ_CONDITION_CHECK4 = 4
|
||||
PACKETJ_CONDITION_CHECK5 = 5
|
||||
PACKETJ_CONDITION_CHECK6 = 6
|
||||
PACKETJ_CONDITION_CHECK7 = 7
|
||||
PACKETJ_TYPE0 = 0
|
||||
PACKETJ_TYPE1 = 1
|
||||
PACKETJ_TYPE2 = 2
|
||||
PACKETJ_TYPE3 = 3
|
||||
PACKETJ_TYPE4 = 4
|
||||
PACKETJ_TYPE5 = 5
|
||||
PACKETJ_TYPE6 = 6
|
||||
PACKETJ_TYPE7 = 7
|
||||
PACKETJ = lambda reg,r,cond,type: ((reg & 0x3FFFF) | ((r & 0x3F) << 18) | ((cond & 0xF) << 24) | ((type & 0xF) << 28)) # type: ignore
|
||||
CP_PACKETJ_NOP = 0x60000000
|
||||
CP_PACKETJ_GET_REG = lambda x: ((x) & 0x3FFFF) # type: ignore
|
||||
CP_PACKETJ_GET_RES = lambda x: (((x) >> 18) & 0x3F) # type: ignore
|
||||
CP_PACKETJ_GET_COND = lambda x: (((x) >> 24) & 0xF) # type: ignore
|
||||
CP_PACKETJ_GET_TYPE = lambda x: (((x) >> 28) & 0xF) # type: ignore
|
||||
PACKET3_NOP = 0x10
|
||||
PACKET3_SET_BASE = 0x11
|
||||
PACKET3_BASE_INDEX = lambda x: ((x) << 0) # type: ignore
|
||||
CE_PARTITION_BASE = 3
|
||||
PACKET3_CLEAR_STATE = 0x12
|
||||
PACKET3_INDEX_BUFFER_SIZE = 0x13
|
||||
PACKET3_DISPATCH_DIRECT = 0x15
|
||||
PACKET3_DISPATCH_INDIRECT = 0x16
|
||||
PACKET3_ATOMIC_GDS = 0x1D
|
||||
PACKET3_ATOMIC_MEM = 0x1E
|
||||
PACKET3_ATOMIC_MEM__ATOMIC = lambda x: ((((unsigned)(x)) & 0x3F) << 0) # type: ignore
|
||||
PACKET3_ATOMIC_MEM__COMMAND = lambda x: ((((unsigned)(x)) & 0xF) << 8) # type: ignore
|
||||
PACKET3_ATOMIC_MEM__CACHE_POLICY = lambda x: ((((unsigned)(x)) & 0x3) << 25) # type: ignore
|
||||
PACKET3_ATOMIC_MEM__ADDR_LO = lambda x: (((unsigned)(x)) << 0) # type: ignore
|
||||
PACKET3_ATOMIC_MEM__ADDR_HI = lambda x: (((unsigned)(x)) << 0) # type: ignore
|
||||
PACKET3_ATOMIC_MEM__SRC_DATA_LO = lambda x: (((unsigned)(x)) << 0) # type: ignore
|
||||
PACKET3_ATOMIC_MEM__SRC_DATA_HI = lambda x: (((unsigned)(x)) << 0) # type: ignore
|
||||
PACKET3_ATOMIC_MEM__CMP_DATA_LO = lambda x: (((unsigned)(x)) << 0) # type: ignore
|
||||
PACKET3_ATOMIC_MEM__CMP_DATA_HI = lambda x: (((unsigned)(x)) << 0) # type: ignore
|
||||
PACKET3_ATOMIC_MEM__LOOP_INTERVAL = lambda x: ((((unsigned)(x)) & 0x1FFF) << 0) # type: ignore
|
||||
PACKET3_ATOMIC_MEM__COMMAND__SINGLE_PASS_ATOMIC = 0
|
||||
PACKET3_ATOMIC_MEM__COMMAND__LOOP_UNTIL_COMPARE_SATISFIED = 1
|
||||
PACKET3_OCCLUSION_QUERY = 0x1F
|
||||
PACKET3_SET_PREDICATION = 0x20
|
||||
PACKET3_REG_RMW = 0x21
|
||||
PACKET3_COND_EXEC = 0x22
|
||||
PACKET3_PRED_EXEC = 0x23
|
||||
PACKET3_PRED_EXEC__EXEC_COUNT = lambda x: ((((unsigned)(x)) & 0x3FFF) << 0) # type: ignore
|
||||
PACKET3_PRED_EXEC__VIRTUAL_XCC_ID_SELECT = lambda x: ((((unsigned)(x)) & 0xFF) << 24) # type: ignore
|
||||
PACKET3_DRAW_INDIRECT = 0x24
|
||||
PACKET3_DRAW_INDEX_INDIRECT = 0x25
|
||||
PACKET3_INDEX_BASE = 0x26
|
||||
PACKET3_DRAW_INDEX_2 = 0x27
|
||||
PACKET3_CONTEXT_CONTROL = 0x28
|
||||
PACKET3_INDEX_TYPE = 0x2A
|
||||
PACKET3_DRAW_INDIRECT_MULTI = 0x2C
|
||||
PACKET3_DRAW_INDEX_AUTO = 0x2D
|
||||
PACKET3_NUM_INSTANCES = 0x2F
|
||||
PACKET3_DRAW_INDEX_MULTI_AUTO = 0x30
|
||||
PACKET3_INDIRECT_BUFFER_CONST = 0x33
|
||||
PACKET3_STRMOUT_BUFFER_UPDATE = 0x34
|
||||
PACKET3_DRAW_INDEX_OFFSET_2 = 0x35
|
||||
PACKET3_DRAW_PREAMBLE = 0x36
|
||||
PACKET3_WRITE_DATA = 0x37
|
||||
WRITE_DATA_DST_SEL = lambda x: ((x) << 8) # type: ignore
|
||||
WR_ONE_ADDR = (1 << 16)
|
||||
WR_CONFIRM = (1 << 20)
|
||||
WRITE_DATA_CACHE_POLICY = lambda x: ((x) << 25) # type: ignore
|
||||
WRITE_DATA_ENGINE_SEL = lambda x: ((x) << 30) # type: ignore
|
||||
PACKET3_WRITE_DATA__DST_SEL = lambda x: ((((unsigned)(x)) & 0xF) << 8) # type: ignore
|
||||
PACKET3_WRITE_DATA__ADDR_INCR = lambda x: ((((unsigned)(x)) & 0x1) << 16) # type: ignore
|
||||
PACKET3_WRITE_DATA__RESUME_VF_MI300 = lambda x: ((((unsigned)(x)) & 0x1) << 19) # type: ignore
|
||||
PACKET3_WRITE_DATA__WR_CONFIRM = lambda x: ((((unsigned)(x)) & 0x1) << 20) # type: ignore
|
||||
PACKET3_WRITE_DATA__CACHE_POLICY = lambda x: ((((unsigned)(x)) & 0x3) << 25) # type: ignore
|
||||
PACKET3_WRITE_DATA__DST_MMREG_ADDR = lambda x: ((((unsigned)(x)) & 0x3FFFF) << 0) # type: ignore
|
||||
PACKET3_WRITE_DATA__DST_GDS_ADDR = lambda x: ((((unsigned)(x)) & 0xFFFF) << 0) # type: ignore
|
||||
PACKET3_WRITE_DATA__DST_MEM_ADDR_LO = lambda x: ((((unsigned)(x)) & 0x3FFFFFFF) << 2) # type: ignore
|
||||
PACKET3_WRITE_DATA__DST_MEM_ADDR_HI = lambda x: ((unsigned)(x)) # type: ignore
|
||||
PACKET3_WRITE_DATA__DST_SEL__MEM_MAPPED_REGISTER = 0
|
||||
PACKET3_WRITE_DATA__DST_SEL__TC_L2 = 2
|
||||
PACKET3_WRITE_DATA__DST_SEL__GDS = 3
|
||||
PACKET3_WRITE_DATA__DST_SEL__MEMORY = 5
|
||||
PACKET3_WRITE_DATA__DST_SEL__MEMORY_MAPPED_ADC_PERSISTENT_STATE = 6
|
||||
PACKET3_WRITE_DATA__ADDR_INCR__INCREMENT_ADDRESS = 0
|
||||
PACKET3_WRITE_DATA__ADDR_INCR__DO_NOT_INCREMENT_ADDRESS = 1
|
||||
PACKET3_WRITE_DATA__WR_CONFIRM__DO_NOT_WAIT_FOR_WRITE_CONFIRMATION = 0
|
||||
PACKET3_WRITE_DATA__WR_CONFIRM__WAIT_FOR_WRITE_CONFIRMATION = 1
|
||||
PACKET3_WRITE_DATA__CACHE_POLICY__LRU = 0
|
||||
PACKET3_WRITE_DATA__CACHE_POLICY__STREAM = 1
|
||||
PACKET3_WRITE_DATA__CACHE_POLICY__NOA = 2
|
||||
PACKET3_WRITE_DATA__CACHE_POLICY__BYPASS = 3
|
||||
PACKET3_DRAW_INDEX_INDIRECT_MULTI = 0x38
|
||||
PACKET3_MEM_SEMAPHORE = 0x39
|
||||
PACKET3_SEM_USE_MAILBOX = (0x1 << 16)
|
||||
PACKET3_SEM_SEL_SIGNAL_TYPE = (0x1 << 20)
|
||||
PACKET3_SEM_SEL_SIGNAL = (0x6 << 29)
|
||||
PACKET3_SEM_SEL_WAIT = (0x7 << 29)
|
||||
PACKET3_WAIT_REG_MEM = 0x3C
|
||||
WAIT_REG_MEM_FUNCTION = lambda x: ((x) << 0) # type: ignore
|
||||
WAIT_REG_MEM_MEM_SPACE = lambda x: ((x) << 4) # type: ignore
|
||||
WAIT_REG_MEM_OPERATION = lambda x: ((x) << 6) # type: ignore
|
||||
WAIT_REG_MEM_ENGINE = lambda x: ((x) << 8) # type: ignore
|
||||
PACKET3_WAIT_REG_MEM__FUNCTION = lambda x: ((((unsigned)(x)) & 0x7) << 0) # type: ignore
|
||||
PACKET3_WAIT_REG_MEM__MEM_SPACE = lambda x: ((((unsigned)(x)) & 0x3) << 4) # type: ignore
|
||||
PACKET3_WAIT_REG_MEM__OPERATION = lambda x: ((((unsigned)(x)) & 0x3) << 6) # type: ignore
|
||||
PACKET3_WAIT_REG_MEM__MES_INTR_PIPE = lambda x: ((((unsigned)(x)) & 0x3) << 22) # type: ignore
|
||||
PACKET3_WAIT_REG_MEM__MES_ACTION = lambda x: ((((unsigned)(x)) & 0x1) << 24) # type: ignore
|
||||
PACKET3_WAIT_REG_MEM__CACHE_POLICY = lambda x: ((((unsigned)(x)) & 0x3) << 25) # type: ignore
|
||||
PACKET3_WAIT_REG_MEM__MEM_POLL_ADDR_LO = lambda x: ((((unsigned)(x)) & 0x3FFFFFFF) << 2) # type: ignore
|
||||
PACKET3_WAIT_REG_MEM__REG_POLL_ADDR = lambda x: ((((unsigned)(x)) & 0x3FFFF) << 0) # type: ignore
|
||||
PACKET3_WAIT_REG_MEM__REG_WRITE_ADDR1 = lambda x: ((((unsigned)(x)) & 0x3FFFF) << 0) # type: ignore
|
||||
PACKET3_WAIT_REG_MEM__MEM_POLL_ADDR_HI = lambda x: ((unsigned)(x)) # type: ignore
|
||||
PACKET3_WAIT_REG_MEM__REG_WRITE_ADDR2 = lambda x: ((((unsigned)(x)) & 0x3FFFF) << 0) # type: ignore
|
||||
PACKET3_WAIT_REG_MEM__REFERENCE = lambda x: ((unsigned)(x)) # type: ignore
|
||||
PACKET3_WAIT_REG_MEM__MASK = lambda x: ((unsigned)(x)) # type: ignore
|
||||
PACKET3_WAIT_REG_MEM__POLL_INTERVAL = lambda x: ((((unsigned)(x)) & 0xFFFF) << 0) # type: ignore
|
||||
PACKET3_WAIT_REG_MEM__OPTIMIZE_ACE_OFFLOAD_MODE = lambda x: ((((unsigned)(x)) & 0x1) << 31) # type: ignore
|
||||
PACKET3_WAIT_REG_MEM__FUNCTION__ALWAYS_PASS = 0
|
||||
PACKET3_WAIT_REG_MEM__FUNCTION__LESS_THAN_REF_VALUE = 1
|
||||
PACKET3_WAIT_REG_MEM__FUNCTION__LESS_THAN_EQUAL_TO_THE_REF_VALUE = 2
|
||||
PACKET3_WAIT_REG_MEM__FUNCTION__EQUAL_TO_THE_REFERENCE_VALUE = 3
|
||||
PACKET3_WAIT_REG_MEM__FUNCTION__NOT_EQUAL_REFERENCE_VALUE = 4
|
||||
PACKET3_WAIT_REG_MEM__FUNCTION__GREATER_THAN_OR_EQUAL_REFERENCE_VALUE = 5
|
||||
PACKET3_WAIT_REG_MEM__FUNCTION__GREATER_THAN_REFERENCE_VALUE = 6
|
||||
PACKET3_WAIT_REG_MEM__MEM_SPACE__REGISTER_SPACE = 0
|
||||
PACKET3_WAIT_REG_MEM__MEM_SPACE__MEMORY_SPACE = 1
|
||||
PACKET3_WAIT_REG_MEM__OPERATION__WAIT_REG_MEM = 0
|
||||
PACKET3_WAIT_REG_MEM__OPERATION__WR_WAIT_WR_REG = 1
|
||||
PACKET3_WAIT_REG_MEM__OPERATION__WAIT_MEM_PREEMPTABLE = 3
|
||||
PACKET3_INDIRECT_BUFFER = 0x3F
|
||||
INDIRECT_BUFFER_VALID = (1 << 23)
|
||||
INDIRECT_BUFFER_CACHE_POLICY = lambda x: ((x) << 28) # type: ignore
|
||||
INDIRECT_BUFFER_PRE_ENB = lambda x: ((x) << 21) # type: ignore
|
||||
INDIRECT_BUFFER_PRE_RESUME = lambda x: ((x) << 30) # type: ignore
|
||||
PACKET3_INDIRECT_BUFFER__IB_BASE_LO = lambda x: ((((unsigned)(x)) & 0x3FFFFFFF) << 2) # type: ignore
|
||||
PACKET3_INDIRECT_BUFFER__IB_BASE_HI = lambda x: ((unsigned)(x)) # type: ignore
|
||||
PACKET3_INDIRECT_BUFFER__IB_SIZE = lambda x: ((((unsigned)(x)) & 0xFFFFF) << 0) # type: ignore
|
||||
PACKET3_INDIRECT_BUFFER__CHAIN = lambda x: ((((unsigned)(x)) & 0x1) << 20) # type: ignore
|
||||
PACKET3_INDIRECT_BUFFER__OFFLOAD_POLLING = lambda x: ((((unsigned)(x)) & 0x1) << 21) # type: ignore
|
||||
PACKET3_INDIRECT_BUFFER__VALID = lambda x: ((((unsigned)(x)) & 0x1) << 23) # type: ignore
|
||||
PACKET3_INDIRECT_BUFFER__VMID = lambda x: ((((unsigned)(x)) & 0xF) << 24) # type: ignore
|
||||
PACKET3_INDIRECT_BUFFER__CACHE_POLICY = lambda x: ((((unsigned)(x)) & 0x3) << 28) # type: ignore
|
||||
PACKET3_INDIRECT_BUFFER__PRIV = lambda x: ((((unsigned)(x)) & 0x1) << 31) # type: ignore
|
||||
PACKET3_INDIRECT_BUFFER__CACHE_POLICY__LRU = 0
|
||||
PACKET3_INDIRECT_BUFFER__CACHE_POLICY__STREAM = 1
|
||||
PACKET3_COPY_DATA = 0x40
|
||||
PACKET3_COPY_DATA__SRC_SEL = lambda x: ((((unsigned)(x)) & 0xF) << 0) # type: ignore
|
||||
PACKET3_COPY_DATA__DST_SEL = lambda x: ((((unsigned)(x)) & 0xF) << 8) # type: ignore
|
||||
PACKET3_COPY_DATA__SRC_CACHE_POLICY = lambda x: ((((unsigned)(x)) & 0x3) << 13) # type: ignore
|
||||
PACKET3_COPY_DATA__COUNT_SEL = lambda x: ((((unsigned)(x)) & 0x1) << 16) # type: ignore
|
||||
PACKET3_COPY_DATA__WR_CONFIRM = lambda x: ((((unsigned)(x)) & 0x1) << 20) # type: ignore
|
||||
PACKET3_COPY_DATA__DST_CACHE_POLICY = lambda x: ((((unsigned)(x)) & 0x3) << 25) # type: ignore
|
||||
PACKET3_COPY_DATA__PQ_EXE_STATUS = lambda x: ((((unsigned)(x)) & 0x1) << 29) # type: ignore
|
||||
PACKET3_COPY_DATA__SRC_REG_OFFSET = lambda x: ((((unsigned)(x)) & 0x3FFFF) << 0) # type: ignore
|
||||
PACKET3_COPY_DATA__SRC_32B_ADDR_LO = lambda x: ((((unsigned)(x)) & 0x3FFFFFFF) << 2) # type: ignore
|
||||
PACKET3_COPY_DATA__SRC_64B_ADDR_LO = lambda x: ((((unsigned)(x)) & 0x1FFFFFFF) << 3) # type: ignore
|
||||
PACKET3_COPY_DATA__SRC_GDS_ADDR_LO = lambda x: ((((unsigned)(x)) & 0xFFFF) << 0) # type: ignore
|
||||
PACKET3_COPY_DATA__IMM_DATA = lambda x: ((unsigned)(x)) # type: ignore
|
||||
PACKET3_COPY_DATA__SRC_MEMTC_ADDR_HI = lambda x: ((unsigned)(x)) # type: ignore
|
||||
PACKET3_COPY_DATA__SRC_IMM_DATA = lambda x: ((unsigned)(x)) # type: ignore
|
||||
PACKET3_COPY_DATA__DST_REG_OFFSET = lambda x: ((((unsigned)(x)) & 0x3FFFF) << 0) # type: ignore
|
||||
PACKET3_COPY_DATA__DST_32B_ADDR_LO = lambda x: ((((unsigned)(x)) & 0x3FFFFFFF) << 2) # type: ignore
|
||||
PACKET3_COPY_DATA__DST_64B_ADDR_LO = lambda x: ((((unsigned)(x)) & 0x1FFFFFFF) << 3) # type: ignore
|
||||
PACKET3_COPY_DATA__DST_GDS_ADDR_LO = lambda x: ((((unsigned)(x)) & 0xFFFF) << 0) # type: ignore
|
||||
PACKET3_COPY_DATA__DST_ADDR_HI = lambda x: ((unsigned)(x)) # type: ignore
|
||||
PACKET3_COPY_DATA__SRC_SEL__MEM_MAPPED_REGISTER = 0
|
||||
PACKET3_COPY_DATA__SRC_SEL__MEMORY = 1
|
||||
PACKET3_COPY_DATA__SRC_SEL__TC_L2 = 2
|
||||
PACKET3_COPY_DATA__SRC_SEL__GDS = 3
|
||||
PACKET3_COPY_DATA__SRC_SEL__PERFCOUNTERS = 4
|
||||
PACKET3_COPY_DATA__SRC_SEL__IMMEDIATE_DATA = 5
|
||||
PACKET3_COPY_DATA__SRC_SEL__ATOMIC_RETURN_DATA = 6
|
||||
PACKET3_COPY_DATA__SRC_SEL__GDS_ATOMIC_RETURN_DATA0 = 7
|
||||
PACKET3_COPY_DATA__SRC_SEL__GDS_ATOMIC_RETURN_DATA1 = 8
|
||||
PACKET3_COPY_DATA__SRC_SEL__GPU_CLOCK_COUNT = 9
|
||||
PACKET3_COPY_DATA__DST_SEL__MEM_MAPPED_REGISTER = 0
|
||||
PACKET3_COPY_DATA__DST_SEL__TC_L2 = 2
|
||||
PACKET3_COPY_DATA__DST_SEL__GDS = 3
|
||||
PACKET3_COPY_DATA__DST_SEL__PERFCOUNTERS = 4
|
||||
PACKET3_COPY_DATA__DST_SEL__MEMORY = 5
|
||||
PACKET3_COPY_DATA__DST_SEL__MEM_MAPPED_REG_DC = 6
|
||||
PACKET3_COPY_DATA__SRC_CACHE_POLICY__LRU = 0
|
||||
PACKET3_COPY_DATA__SRC_CACHE_POLICY__STREAM = 1
|
||||
PACKET3_COPY_DATA__COUNT_SEL__32_BITS_OF_DATA = 0
|
||||
PACKET3_COPY_DATA__COUNT_SEL__64_BITS_OF_DATA = 1
|
||||
PACKET3_COPY_DATA__WR_CONFIRM__DO_NOT_WAIT_FOR_CONFIRMATION = 0
|
||||
PACKET3_COPY_DATA__WR_CONFIRM__WAIT_FOR_CONFIRMATION = 1
|
||||
PACKET3_COPY_DATA__DST_CACHE_POLICY__LRU = 0
|
||||
PACKET3_COPY_DATA__DST_CACHE_POLICY__STREAM = 1
|
||||
PACKET3_COPY_DATA__PQ_EXE_STATUS__DEFAULT = 0
|
||||
PACKET3_COPY_DATA__PQ_EXE_STATUS__PHASE_UPDATE = 1
|
||||
PACKET3_PFP_SYNC_ME = 0x42
|
||||
PACKET3_COND_WRITE = 0x45
|
||||
PACKET3_EVENT_WRITE = 0x46
|
||||
EVENT_TYPE = lambda x: ((x) << 0) # type: ignore
|
||||
EVENT_INDEX = lambda x: ((x) << 8) # type: ignore
|
||||
PACKET3_EVENT_WRITE__EVENT_TYPE = lambda x: ((((unsigned)(x)) & 0x3F) << 0) # type: ignore
|
||||
PACKET3_EVENT_WRITE__EVENT_INDEX = lambda x: ((((unsigned)(x)) & 0xF) << 8) # type: ignore
|
||||
PACKET3_EVENT_WRITE__OFFLOAD_ENABLE = lambda x: ((((unsigned)(x)) & 0x1) << 31) # type: ignore
|
||||
PACKET3_EVENT_WRITE__SAMP_PLST_CNTR_MODE = lambda x: ((((unsigned)(x)) & 0x3) << 29) # type: ignore
|
||||
PACKET3_EVENT_WRITE__ADDRESS_LO = lambda x: ((((unsigned)(x)) & 0x1FFFFFFF) << 3) # type: ignore
|
||||
PACKET3_EVENT_WRITE__ADDRESS_HI = lambda x: (((unsigned)(x)) << 0) # type: ignore
|
||||
PACKET3_EVENT_WRITE__EVENT_INDEX__OTHER = 0
|
||||
PACKET3_EVENT_WRITE__EVENT_INDEX__SAMPLE_PIPELINESTATS = 2
|
||||
PACKET3_EVENT_WRITE__EVENT_INDEX__CS_PARTIAL_FLUSH = 4
|
||||
PACKET3_RELEASE_MEM = 0x49
|
||||
EVENT_TYPE = lambda x: ((x) << 0) # type: ignore
|
||||
EVENT_INDEX = lambda x: ((x) << 8) # type: ignore
|
||||
EOP_TCL1_VOL_ACTION_EN = (1 << 12)
|
||||
EOP_TC_VOL_ACTION_EN = (1 << 13)
|
||||
EOP_TC_WB_ACTION_EN = (1 << 15)
|
||||
EOP_TCL1_ACTION_EN = (1 << 16)
|
||||
EOP_TC_ACTION_EN = (1 << 17)
|
||||
EOP_TC_NC_ACTION_EN = (1 << 19)
|
||||
EOP_TC_MD_ACTION_EN = (1 << 21)
|
||||
EOP_EXEC = (1 << 28)
|
||||
DATA_SEL = lambda x: ((x) << 29) # type: ignore
|
||||
INT_SEL = lambda x: ((x) << 24) # type: ignore
|
||||
DST_SEL = lambda x: ((x) << 16) # type: ignore
|
||||
PACKET3_PREAMBLE_CNTL = 0x4A
|
||||
PACKET3_PREAMBLE_BEGIN_CLEAR_STATE = (2 << 28)
|
||||
PACKET3_PREAMBLE_END_CLEAR_STATE = (3 << 28)
|
||||
PACKET3_DMA_DATA = 0x50
|
||||
PACKET3_DMA_DATA_ENGINE = lambda x: ((x) << 0) # type: ignore
|
||||
PACKET3_DMA_DATA_SRC_CACHE_POLICY = lambda x: ((x) << 13) # type: ignore
|
||||
PACKET3_DMA_DATA_DST_SEL = lambda x: ((x) << 20) # type: ignore
|
||||
PACKET3_DMA_DATA_DST_CACHE_POLICY = lambda x: ((x) << 25) # type: ignore
|
||||
PACKET3_DMA_DATA_SRC_SEL = lambda x: ((x) << 29) # type: ignore
|
||||
PACKET3_DMA_DATA_CP_SYNC = (1 << 31)
|
||||
PACKET3_DMA_DATA_CMD_SAS = (1 << 26)
|
||||
PACKET3_DMA_DATA_CMD_DAS = (1 << 27)
|
||||
PACKET3_DMA_DATA_CMD_SAIC = (1 << 28)
|
||||
PACKET3_DMA_DATA_CMD_DAIC = (1 << 29)
|
||||
PACKET3_DMA_DATA_CMD_RAW_WAIT = (1 << 30)
|
||||
PACKET3_ACQUIRE_MEM = 0x58
|
||||
PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_NC_ACTION_ENA = lambda x: ((x) << 3) # type: ignore
|
||||
PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_WC_ACTION_ENA = lambda x: ((x) << 4) # type: ignore
|
||||
PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_INV_METADATA_ACTION_ENA = lambda x: ((x) << 5) # type: ignore
|
||||
PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TCL1_VOL_ACTION_ENA = lambda x: ((x) << 15) # type: ignore
|
||||
PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_WB_ACTION_ENA = lambda x: ((x) << 18) # type: ignore
|
||||
PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TCL1_ACTION_ENA = lambda x: ((x) << 22) # type: ignore
|
||||
PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_ACTION_ENA = lambda x: ((x) << 23) # type: ignore
|
||||
PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_CB_ACTION_ENA = lambda x: ((x) << 25) # type: ignore
|
||||
PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_DB_ACTION_ENA = lambda x: ((x) << 26) # type: ignore
|
||||
PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_SH_KCACHE_ACTION_ENA = lambda x: ((x) << 27) # type: ignore
|
||||
PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_SH_KCACHE_VOL_ACTION_ENA = lambda x: ((x) << 28) # type: ignore
|
||||
PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_SH_ICACHE_ACTION_ENA = lambda x: ((x) << 29) # type: ignore
|
||||
PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_SH_KCACHE_WB_ACTION_ENA = lambda x: ((x) << 30) # type: ignore
|
||||
PACKET3_REWIND = 0x59
|
||||
PACKET3_ACQUIRE_MEM__COHER_SIZE = lambda x: ((unsigned)(x)) # type: ignore
|
||||
PACKET3_ACQUIRE_MEM__COHER_SIZE_HI = lambda x: ((((unsigned)(x)) & 0xFF) << 0) # type: ignore
|
||||
PACKET3_ACQUIRE_MEM__COHER_SIZE_HI_VG10 = lambda x: ((((unsigned)(x)) & 0xFFFFFF) << 0) # type: ignore
|
||||
PACKET3_ACQUIRE_MEM__COHER_BASE_LO = lambda x: ((unsigned)(x)) # type: ignore
|
||||
PACKET3_ACQUIRE_MEM__COHER_BASE_HI = lambda x: ((((unsigned)(x)) & 0xFFFFFF) << 0) # type: ignore
|
||||
PACKET3_ACQUIRE_MEM__POLL_INTERVAL = lambda x: ((((unsigned)(x)) & 0xFFFF) << 0) # type: ignore
|
||||
PACKET3_ACQUIRE_MEM__GCR_CNTL = lambda x: ((((unsigned)(x)) & 0x7FF) << 0) # type: ignore
|
||||
PACKET3_LOAD_UCONFIG_REG = 0x5E
|
||||
PACKET3_LOAD_SH_REG = 0x5F
|
||||
PACKET3_LOAD_CONFIG_REG = 0x60
|
||||
PACKET3_LOAD_CONTEXT_REG = 0x61
|
||||
PACKET3_SET_CONFIG_REG = 0x68
|
||||
PACKET3_SET_CONFIG_REG_START = 0x00002000
|
||||
PACKET3_SET_CONFIG_REG_END = 0x00002c00
|
||||
PACKET3_SET_CONTEXT_REG = 0x69
|
||||
PACKET3_SET_CONTEXT_REG_START = 0x0000a000
|
||||
PACKET3_SET_CONTEXT_REG_END = 0x0000a400
|
||||
PACKET3_SET_CONTEXT_REG_INDIRECT = 0x73
|
||||
PACKET3_SET_SH_REG = 0x76
|
||||
PACKET3_SET_SH_REG_START = 0x00002c00
|
||||
PACKET3_SET_SH_REG_END = 0x00003000
|
||||
PACKET3_SET_SH_REG__REG_OFFSET = lambda x: ((((unsigned)(x)) & 0xFFFF) << 0) # type: ignore
|
||||
PACKET3_SET_SH_REG__VMID_SHIFT = lambda x: ((((unsigned)(x)) & 0x1F) << 23) # type: ignore
|
||||
PACKET3_SET_SH_REG__INDEX = lambda x: ((((unsigned)(x)) & 0xF) << 28) # type: ignore
|
||||
PACKET3_SET_SH_REG_OFFSET = 0x77
|
||||
PACKET3_SET_QUEUE_REG = 0x78
|
||||
PACKET3_SET_UCONFIG_REG = 0x79
|
||||
PACKET3_SET_UCONFIG_REG_START = 0x0000c000
|
||||
PACKET3_SET_UCONFIG_REG_END = 0x0000c400
|
||||
PACKET3_SET_UCONFIG_REG_INDEX_TYPE = (2 << 28)
|
||||
PACKET3_SET_UCONFIG_REG__REG_OFFSET = lambda x: ((((unsigned)(x)) & 0xFFFF) << 0) # type: ignore
|
||||
PACKET3_SCRATCH_RAM_WRITE = 0x7D
|
||||
PACKET3_SCRATCH_RAM_READ = 0x7E
|
||||
PACKET3_LOAD_CONST_RAM = 0x80
|
||||
PACKET3_WRITE_CONST_RAM = 0x81
|
||||
PACKET3_DUMP_CONST_RAM = 0x83
|
||||
PACKET3_INCREMENT_CE_COUNTER = 0x84
|
||||
PACKET3_INCREMENT_DE_COUNTER = 0x85
|
||||
PACKET3_WAIT_ON_CE_COUNTER = 0x86
|
||||
PACKET3_WAIT_ON_DE_COUNTER_DIFF = 0x88
|
||||
PACKET3_SWITCH_BUFFER = 0x8B
|
||||
PACKET3_FRAME_CONTROL = 0x90
|
||||
FRAME_TMZ = (1 << 0)
|
||||
FRAME_CMD = lambda x: ((x) << 28) # type: ignore
|
||||
PACKET3_INVALIDATE_TLBS = 0x98
|
||||
PACKET3_INVALIDATE_TLBS_DST_SEL = lambda x: ((x) << 0) # type: ignore
|
||||
PACKET3_INVALIDATE_TLBS_ALL_HUB = lambda x: ((x) << 4) # type: ignore
|
||||
PACKET3_INVALIDATE_TLBS_PASID = lambda x: ((x) << 5) # type: ignore
|
||||
PACKET3_INVALIDATE_TLBS_FLUSH_TYPE = lambda x: ((x) << 29) # type: ignore
|
||||
PACKET3_SET_RESOURCES = 0xA0
|
||||
PACKET3_SET_RESOURCES_VMID_MASK = lambda x: ((x) << 0) # type: ignore
|
||||
PACKET3_SET_RESOURCES_UNMAP_LATENTY = lambda x: ((x) << 16) # type: ignore
|
||||
PACKET3_SET_RESOURCES_QUEUE_TYPE = lambda x: ((x) << 29) # type: ignore
|
||||
PACKET3_MAP_QUEUES = 0xA2
|
||||
PACKET3_MAP_QUEUES_QUEUE_SEL = lambda x: ((x) << 4) # type: ignore
|
||||
PACKET3_MAP_QUEUES_VMID = lambda x: ((x) << 8) # type: ignore
|
||||
PACKET3_MAP_QUEUES_QUEUE = lambda x: ((x) << 13) # type: ignore
|
||||
PACKET3_MAP_QUEUES_PIPE = lambda x: ((x) << 16) # type: ignore
|
||||
PACKET3_MAP_QUEUES_ME = lambda x: ((x) << 18) # type: ignore
|
||||
PACKET3_MAP_QUEUES_QUEUE_TYPE = lambda x: ((x) << 21) # type: ignore
|
||||
PACKET3_MAP_QUEUES_ALLOC_FORMAT = lambda x: ((x) << 24) # type: ignore
|
||||
PACKET3_MAP_QUEUES_ENGINE_SEL = lambda x: ((x) << 26) # type: ignore
|
||||
PACKET3_MAP_QUEUES_NUM_QUEUES = lambda x: ((x) << 29) # type: ignore
|
||||
PACKET3_MAP_QUEUES_CHECK_DISABLE = lambda x: ((x) << 1) # type: ignore
|
||||
PACKET3_MAP_QUEUES_DOORBELL_OFFSET = lambda x: ((x) << 2) # type: ignore
|
||||
PACKET3_UNMAP_QUEUES = 0xA3
|
||||
PACKET3_UNMAP_QUEUES_ACTION = lambda x: ((x) << 0) # type: ignore
|
||||
PACKET3_UNMAP_QUEUES_QUEUE_SEL = lambda x: ((x) << 4) # type: ignore
|
||||
PACKET3_UNMAP_QUEUES_ENGINE_SEL = lambda x: ((x) << 26) # type: ignore
|
||||
PACKET3_UNMAP_QUEUES_NUM_QUEUES = lambda x: ((x) << 29) # type: ignore
|
||||
PACKET3_UNMAP_QUEUES_PASID = lambda x: ((x) << 0) # type: ignore
|
||||
PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0 = lambda x: ((x) << 2) # type: ignore
|
||||
PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET1 = lambda x: ((x) << 2) # type: ignore
|
||||
PACKET3_UNMAP_QUEUES_RB_WPTR = lambda x: ((x) << 0) # type: ignore
|
||||
PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET2 = lambda x: ((x) << 2) # type: ignore
|
||||
PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET3 = lambda x: ((x) << 2) # type: ignore
|
||||
PACKET3_QUERY_STATUS = 0xA4
|
||||
PACKET3_QUERY_STATUS_CONTEXT_ID = lambda x: ((x) << 0) # type: ignore
|
||||
PACKET3_QUERY_STATUS_INTERRUPT_SEL = lambda x: ((x) << 28) # type: ignore
|
||||
PACKET3_QUERY_STATUS_COMMAND = lambda x: ((x) << 30) # type: ignore
|
||||
PACKET3_QUERY_STATUS_PASID = lambda x: ((x) << 0) # type: ignore
|
||||
PACKET3_QUERY_STATUS_DOORBELL_OFFSET = lambda x: ((x) << 2) # type: ignore
|
||||
PACKET3_QUERY_STATUS_ENG_SEL = lambda x: ((x) << 25) # type: ignore
|
||||
PACKET3_RUN_CLEANER_SHADER_9_0 = 0xD7
|
||||
PACKET3_RUN_CLEANER_SHADER = 0xD2
|
||||
VCE_CMD_NO_OP = 0x00000000
|
||||
VCE_CMD_END = 0x00000001
|
||||
VCE_CMD_IB = 0x00000002
|
||||
VCE_CMD_FENCE = 0x00000003
|
||||
VCE_CMD_TRAP = 0x00000004
|
||||
VCE_CMD_IB_AUTO = 0x00000005
|
||||
VCE_CMD_SEMAPHORE = 0x00000006
|
||||
VCE_CMD_IB_VM = 0x00000102
|
||||
VCE_CMD_WAIT_GE = 0x00000106
|
||||
VCE_CMD_UPDATE_PTB = 0x00000107
|
||||
VCE_CMD_FLUSH_TLB = 0x00000108
|
||||
VCE_CMD_REG_WRITE = 0x00000109
|
||||
VCE_CMD_REG_WAIT = 0x0000010a
|
||||
HEVC_ENC_CMD_NO_OP = 0x00000000
|
||||
HEVC_ENC_CMD_END = 0x00000001
|
||||
HEVC_ENC_CMD_FENCE = 0x00000003
|
||||
HEVC_ENC_CMD_TRAP = 0x00000004
|
||||
HEVC_ENC_CMD_IB_VM = 0x00000102
|
||||
HEVC_ENC_CMD_REG_WRITE = 0x00000109
|
||||
HEVC_ENC_CMD_REG_WAIT = 0x0000010a
|
||||
3350
tinygrad_repo/tinygrad/runtime/autogen/am/pmc.py
Normal file
3350
tinygrad_repo/tinygrad/runtime/autogen/am/pmc.py
Normal file
File diff suppressed because it is too large
Load Diff
10160
tinygrad_repo/tinygrad/runtime/autogen/am/regs.py
Normal file
10160
tinygrad_repo/tinygrad/runtime/autogen/am/regs.py
Normal file
File diff suppressed because it is too large
Load Diff
2434
tinygrad_repo/tinygrad/runtime/autogen/am/sdma_4_0_0.py
Normal file
2434
tinygrad_repo/tinygrad/runtime/autogen/am/sdma_4_0_0.py
Normal file
File diff suppressed because it is too large
Load Diff
3386
tinygrad_repo/tinygrad/runtime/autogen/am/sdma_5_0_0.py
Normal file
3386
tinygrad_repo/tinygrad/runtime/autogen/am/sdma_5_0_0.py
Normal file
File diff suppressed because it is too large
Load Diff
3882
tinygrad_repo/tinygrad/runtime/autogen/am/sdma_6_0_0.py
Normal file
3882
tinygrad_repo/tinygrad/runtime/autogen/am/sdma_6_0_0.py
Normal file
File diff suppressed because it is too large
Load Diff
1225
tinygrad_repo/tinygrad/runtime/autogen/am/smu_13_0_0.py
Normal file
1225
tinygrad_repo/tinygrad/runtime/autogen/am/smu_13_0_0.py
Normal file
File diff suppressed because one or more lines are too long
532
tinygrad_repo/tinygrad/runtime/autogen/am/smu_13_0_12.py
Normal file
532
tinygrad_repo/tinygrad/runtime/autogen/am/smu_13_0_12.py
Normal file
@@ -0,0 +1,532 @@
|
||||
# mypy: disable-error-code="empty-body"
|
||||
from __future__ import annotations
|
||||
import ctypes
|
||||
from typing import Literal, TypeAlias
|
||||
from tinygrad.runtime.support.c import _IO, _IOW, _IOR, _IOWR
|
||||
from tinygrad.runtime.support import c
|
||||
PPSMC_Result: TypeAlias = ctypes.c_uint32
|
||||
PPSMC_MSG: TypeAlias = ctypes.c_uint32
|
||||
FEATURE_LIST_e: dict[int, str] = {(FEATURE_DATA_CALCULATION:=0): 'FEATURE_DATA_CALCULATION', (FEATURE_DPM_FCLK:=1): 'FEATURE_DPM_FCLK', (FEATURE_DPM_GFXCLK:=2): 'FEATURE_DPM_GFXCLK', (FEATURE_DPM_LCLK:=3): 'FEATURE_DPM_LCLK', (FEATURE_DPM_SOCCLK:=4): 'FEATURE_DPM_SOCCLK', (FEATURE_DPM_UCLK:=5): 'FEATURE_DPM_UCLK', (FEATURE_DPM_VCN:=6): 'FEATURE_DPM_VCN', (FEATURE_DPM_XGMI:=7): 'FEATURE_DPM_XGMI', (FEATURE_DS_FCLK:=8): 'FEATURE_DS_FCLK', (FEATURE_DS_GFXCLK:=9): 'FEATURE_DS_GFXCLK', (FEATURE_DS_LCLK:=10): 'FEATURE_DS_LCLK', (FEATURE_DS_MP0CLK:=11): 'FEATURE_DS_MP0CLK', (FEATURE_DS_MP1CLK:=12): 'FEATURE_DS_MP1CLK', (FEATURE_DS_MPIOCLK:=13): 'FEATURE_DS_MPIOCLK', (FEATURE_DS_SOCCLK:=14): 'FEATURE_DS_SOCCLK', (FEATURE_DS_VCN:=15): 'FEATURE_DS_VCN', (FEATURE_APCC_DFLL:=16): 'FEATURE_APCC_DFLL', (FEATURE_APCC_PLUS:=17): 'FEATURE_APCC_PLUS', (FEATURE_PPT:=18): 'FEATURE_PPT', (FEATURE_TDC:=19): 'FEATURE_TDC', (FEATURE_THERMAL:=20): 'FEATURE_THERMAL', (FEATURE_SOC_PCC:=21): 'FEATURE_SOC_PCC', (FEATURE_PROCHOT:=22): 'FEATURE_PROCHOT', (FEATURE_FDD_AID_HBM:=23): 'FEATURE_FDD_AID_HBM', (FEATURE_FDD_AID_SOC:=24): 'FEATURE_FDD_AID_SOC', (FEATURE_FDD_XCD_EDC:=25): 'FEATURE_FDD_XCD_EDC', (FEATURE_FDD_XCD_XVMIN:=26): 'FEATURE_FDD_XCD_XVMIN', (FEATURE_FW_CTF:=27): 'FEATURE_FW_CTF', (FEATURE_SMU_CG:=28): 'FEATURE_SMU_CG', (FEATURE_PSI7:=29): 'FEATURE_PSI7', (FEATURE_XGMI_PER_LINK_PWR_DOWN:=30): 'FEATURE_XGMI_PER_LINK_PWR_DOWN', (FEATURE_SOC_DC_RTC:=31): 'FEATURE_SOC_DC_RTC', (FEATURE_GFX_DC_RTC:=32): 'FEATURE_GFX_DC_RTC', (FEATURE_DVM_MIN_PSM:=33): 'FEATURE_DVM_MIN_PSM', (FEATURE_PRC:=34): 'FEATURE_PRC', (FEATURE_PSM_SQ_THROTTLER:=35): 'FEATURE_PSM_SQ_THROTTLER', (FEATURE_PIT:=36): 'FEATURE_PIT', (FEATURE_DVO:=37): 'FEATURE_DVO', (FEATURE_XVMINORPSM_CLKSTOP_DS:=38): 'FEATURE_XVMINORPSM_CLKSTOP_DS', (FEATURE_GLOBAL_DPM:=39): 'FEATURE_GLOBAL_DPM', (FEATURE_HROM_EN:=40): 'FEATURE_HROM_EN', (NUM_FEATURES:=41): 'NUM_FEATURES'}
|
||||
PCIE_LINK_SPEED_INDEX_TABLE_e: dict[int, str] = {(PCIE_LINK_SPEED_INDEX_TABLE_RESERVED:=0): 'PCIE_LINK_SPEED_INDEX_TABLE_RESERVED', (PCIE_LINK_SPEED_INDEX_TABLE_GEN1:=1): 'PCIE_LINK_SPEED_INDEX_TABLE_GEN1', (PCIE_LINK_SPEED_INDEX_TABLE_GEN2:=2): 'PCIE_LINK_SPEED_INDEX_TABLE_GEN2', (PCIE_LINK_SPEED_INDEX_TABLE_GEN3:=3): 'PCIE_LINK_SPEED_INDEX_TABLE_GEN3', (PCIE_LINK_SPEED_INDEX_TABLE_GEN4:=4): 'PCIE_LINK_SPEED_INDEX_TABLE_GEN4', (PCIE_LINK_SPEED_INDEX_TABLE_GEN5:=5): 'PCIE_LINK_SPEED_INDEX_TABLE_GEN5', (PCIE_LINK_SPEED_INDEX_TABLE_COUNT:=6): 'PCIE_LINK_SPEED_INDEX_TABLE_COUNT'}
|
||||
GFX_GUARDBAND_OFFSET_e: dict[int, str] = {(GFX_GUARDBAND_OFFSET_0:=0): 'GFX_GUARDBAND_OFFSET_0', (GFX_GUARDBAND_OFFSET_1:=1): 'GFX_GUARDBAND_OFFSET_1', (GFX_GUARDBAND_OFFSET_2:=2): 'GFX_GUARDBAND_OFFSET_2', (GFX_GUARDBAND_OFFSET_3:=3): 'GFX_GUARDBAND_OFFSET_3', (GFX_GUARDBAND_OFFSET_4:=4): 'GFX_GUARDBAND_OFFSET_4', (GFX_GUARDBAND_OFFSET_5:=5): 'GFX_GUARDBAND_OFFSET_5', (GFX_GUARDBAND_OFFSET_6:=6): 'GFX_GUARDBAND_OFFSET_6', (GFX_GUARDBAND_OFFSET_7:=7): 'GFX_GUARDBAND_OFFSET_7', (GFX_GUARDBAND_OFFSET_COUNT:=8): 'GFX_GUARDBAND_OFFSET_COUNT'}
|
||||
GFX_DVM_MARGIN_e: dict[int, str] = {(GFX_DVM_MARGINHI_0:=0): 'GFX_DVM_MARGINHI_0', (GFX_DVM_MARGINHI_1:=1): 'GFX_DVM_MARGINHI_1', (GFX_DVM_MARGINHI_2:=2): 'GFX_DVM_MARGINHI_2', (GFX_DVM_MARGINHI_3:=3): 'GFX_DVM_MARGINHI_3', (GFX_DVM_MARGINHI_4:=4): 'GFX_DVM_MARGINHI_4', (GFX_DVM_MARGINHI_5:=5): 'GFX_DVM_MARGINHI_5', (GFX_DVM_MARGINHI_6:=6): 'GFX_DVM_MARGINHI_6', (GFX_DVM_MARGINHI_7:=7): 'GFX_DVM_MARGINHI_7', (GFX_DVM_MARGINLO_0:=8): 'GFX_DVM_MARGINLO_0', (GFX_DVM_MARGINLO_1:=9): 'GFX_DVM_MARGINLO_1', (GFX_DVM_MARGINLO_2:=10): 'GFX_DVM_MARGINLO_2', (GFX_DVM_MARGINLO_3:=11): 'GFX_DVM_MARGINLO_3', (GFX_DVM_MARGINLO_4:=12): 'GFX_DVM_MARGINLO_4', (GFX_DVM_MARGINLO_5:=13): 'GFX_DVM_MARGINLO_5', (GFX_DVM_MARGINLO_6:=14): 'GFX_DVM_MARGINLO_6', (GFX_DVM_MARGINLO_7:=15): 'GFX_DVM_MARGINLO_7', (GFX_DVM_MARGIN_COUNT:=16): 'GFX_DVM_MARGIN_COUNT'}
|
||||
SYSTEM_TEMP_e: dict[int, str] = {(SYSTEM_TEMP_UBB_FPGA:=0): 'SYSTEM_TEMP_UBB_FPGA', (SYSTEM_TEMP_UBB_FRONT:=1): 'SYSTEM_TEMP_UBB_FRONT', (SYSTEM_TEMP_UBB_BACK:=2): 'SYSTEM_TEMP_UBB_BACK', (SYSTEM_TEMP_UBB_OAM7:=3): 'SYSTEM_TEMP_UBB_OAM7', (SYSTEM_TEMP_UBB_IBC:=4): 'SYSTEM_TEMP_UBB_IBC', (SYSTEM_TEMP_UBB_UFPGA:=5): 'SYSTEM_TEMP_UBB_UFPGA', (SYSTEM_TEMP_UBB_OAM1:=6): 'SYSTEM_TEMP_UBB_OAM1', (SYSTEM_TEMP_OAM_0_1_HSC:=7): 'SYSTEM_TEMP_OAM_0_1_HSC', (SYSTEM_TEMP_OAM_2_3_HSC:=8): 'SYSTEM_TEMP_OAM_2_3_HSC', (SYSTEM_TEMP_OAM_4_5_HSC:=9): 'SYSTEM_TEMP_OAM_4_5_HSC', (SYSTEM_TEMP_OAM_6_7_HSC:=10): 'SYSTEM_TEMP_OAM_6_7_HSC', (SYSTEM_TEMP_UBB_FPGA_0V72_VR:=11): 'SYSTEM_TEMP_UBB_FPGA_0V72_VR', (SYSTEM_TEMP_UBB_FPGA_3V3_VR:=12): 'SYSTEM_TEMP_UBB_FPGA_3V3_VR', (SYSTEM_TEMP_RETIMER_0_1_2_3_1V2_VR:=13): 'SYSTEM_TEMP_RETIMER_0_1_2_3_1V2_VR', (SYSTEM_TEMP_RETIMER_4_5_6_7_1V2_VR:=14): 'SYSTEM_TEMP_RETIMER_4_5_6_7_1V2_VR', (SYSTEM_TEMP_RETIMER_0_1_0V9_VR:=15): 'SYSTEM_TEMP_RETIMER_0_1_0V9_VR', (SYSTEM_TEMP_RETIMER_4_5_0V9_VR:=16): 'SYSTEM_TEMP_RETIMER_4_5_0V9_VR', (SYSTEM_TEMP_RETIMER_2_3_0V9_VR:=17): 'SYSTEM_TEMP_RETIMER_2_3_0V9_VR', (SYSTEM_TEMP_RETIMER_6_7_0V9_VR:=18): 'SYSTEM_TEMP_RETIMER_6_7_0V9_VR', (SYSTEM_TEMP_OAM_0_1_2_3_3V3_VR:=19): 'SYSTEM_TEMP_OAM_0_1_2_3_3V3_VR', (SYSTEM_TEMP_OAM_4_5_6_7_3V3_VR:=20): 'SYSTEM_TEMP_OAM_4_5_6_7_3V3_VR', (SYSTEM_TEMP_IBC_HSC:=21): 'SYSTEM_TEMP_IBC_HSC', (SYSTEM_TEMP_IBC:=22): 'SYSTEM_TEMP_IBC', (SYSTEM_TEMP_MAX_ENTRIES:=32): 'SYSTEM_TEMP_MAX_ENTRIES'}
|
||||
NODE_TEMP_e: dict[int, str] = {(NODE_TEMP_RETIMER:=0): 'NODE_TEMP_RETIMER', (NODE_TEMP_IBC_TEMP:=1): 'NODE_TEMP_IBC_TEMP', (NODE_TEMP_IBC_2_TEMP:=2): 'NODE_TEMP_IBC_2_TEMP', (NODE_TEMP_VDD18_VR_TEMP:=3): 'NODE_TEMP_VDD18_VR_TEMP', (NODE_TEMP_04_HBM_B_VR_TEMP:=4): 'NODE_TEMP_04_HBM_B_VR_TEMP', (NODE_TEMP_04_HBM_D_VR_TEMP:=5): 'NODE_TEMP_04_HBM_D_VR_TEMP', (NODE_TEMP_MAX_TEMP_ENTRIES:=12): 'NODE_TEMP_MAX_TEMP_ENTRIES'}
|
||||
SVI_TEMP_e: dict[int, str] = {(SVI_VDDCR_VDD0_TEMP:=0): 'SVI_VDDCR_VDD0_TEMP', (SVI_VDDCR_VDD1_TEMP:=1): 'SVI_VDDCR_VDD1_TEMP', (SVI_VDDCR_VDD2_TEMP:=2): 'SVI_VDDCR_VDD2_TEMP', (SVI_VDDCR_VDD3_TEMP:=3): 'SVI_VDDCR_VDD3_TEMP', (SVI_VDDCR_SOC_A_TEMP:=4): 'SVI_VDDCR_SOC_A_TEMP', (SVI_VDDCR_SOC_C_TEMP:=5): 'SVI_VDDCR_SOC_C_TEMP', (SVI_VDDCR_SOCIO_A_TEMP:=6): 'SVI_VDDCR_SOCIO_A_TEMP', (SVI_VDDCR_SOCIO_C_TEMP:=7): 'SVI_VDDCR_SOCIO_C_TEMP', (SVI_VDD_085_HBM_TEMP:=8): 'SVI_VDD_085_HBM_TEMP', (SVI_VDDCR_11_HBM_B_TEMP:=9): 'SVI_VDDCR_11_HBM_B_TEMP', (SVI_VDDCR_11_HBM_D_TEMP:=10): 'SVI_VDDCR_11_HBM_D_TEMP', (SVI_VDD_USR_TEMP:=11): 'SVI_VDD_USR_TEMP', (SVI_VDDIO_11_E32_TEMP:=12): 'SVI_VDDIO_11_E32_TEMP', (SVI_MAX_TEMP_ENTRIES:=13): 'SVI_MAX_TEMP_ENTRIES'}
|
||||
@c.record
|
||||
class MetricsTable_t(c.Struct):
|
||||
SIZE = 1284
|
||||
AccumulationCounter: int
|
||||
MaxSocketTemperature: int
|
||||
MaxVrTemperature: int
|
||||
MaxHbmTemperature: int
|
||||
MaxSocketTemperatureAcc: int
|
||||
MaxVrTemperatureAcc: int
|
||||
MaxHbmTemperatureAcc: int
|
||||
SocketPowerLimit: int
|
||||
SocketPower: int
|
||||
Timestamp: int
|
||||
SocketEnergyAcc: int
|
||||
XcdEnergyAcc: int
|
||||
AidEnergyAcc: int
|
||||
HbmEnergyAcc: int
|
||||
GfxclkFrequencyLimit: int
|
||||
FclkFrequency: int
|
||||
UclkFrequency: int
|
||||
SocclkFrequency: c.Array[ctypes.c_uint32, Literal[4]]
|
||||
VclkFrequency: c.Array[ctypes.c_uint32, Literal[4]]
|
||||
DclkFrequency: c.Array[ctypes.c_uint32, Literal[4]]
|
||||
LclkFrequency: c.Array[ctypes.c_uint32, Literal[4]]
|
||||
GfxclkFrequencyAcc: c.Array[ctypes.c_uint64, Literal[8]]
|
||||
MaxLclkDpmRange: int
|
||||
MinLclkDpmRange: int
|
||||
XgmiWidth: int
|
||||
XgmiBitrate: int
|
||||
XgmiReadBandwidthAcc: c.Array[ctypes.c_uint64, Literal[8]]
|
||||
XgmiWriteBandwidthAcc: c.Array[ctypes.c_uint64, Literal[8]]
|
||||
SocketGfxBusy: int
|
||||
DramBandwidthUtilization: int
|
||||
SocketGfxBusyAcc: int
|
||||
DramBandwidthAcc: int
|
||||
MaxDramBandwidth: int
|
||||
DramBandwidthUtilizationAcc: int
|
||||
PcieBandwidthAcc: c.Array[ctypes.c_uint64, Literal[4]]
|
||||
ProchotResidencyAcc: int
|
||||
PptResidencyAcc: int
|
||||
SocketThmResidencyAcc: int
|
||||
VrThmResidencyAcc: int
|
||||
HbmThmResidencyAcc: int
|
||||
GfxLockXCDMak: int
|
||||
GfxclkFrequency: c.Array[ctypes.c_uint32, Literal[8]]
|
||||
XgmiReadDataSizeAcc: c.Array[ctypes.c_uint64, Literal[8]]
|
||||
XgmiWriteDataSizeAcc: c.Array[ctypes.c_uint64, Literal[8]]
|
||||
PcieBandwidth: c.Array[ctypes.c_uint32, Literal[4]]
|
||||
PCIeL0ToRecoveryCountAcc: int
|
||||
PCIenReplayAAcc: int
|
||||
PCIenReplayARolloverCountAcc: int
|
||||
PCIeNAKSentCountAcc: int
|
||||
PCIeNAKReceivedCountAcc: int
|
||||
VcnBusy: c.Array[ctypes.c_uint32, Literal[4]]
|
||||
JpegBusy: c.Array[ctypes.c_uint32, Literal[40]]
|
||||
PCIeLinkSpeed: int
|
||||
PCIeLinkWidth: int
|
||||
GfxBusy: c.Array[ctypes.c_uint32, Literal[8]]
|
||||
GfxBusyAcc: c.Array[ctypes.c_uint64, Literal[8]]
|
||||
PCIeOtherEndRecoveryAcc: int
|
||||
GfxclkBelowHostLimitPptAcc: c.Array[ctypes.c_uint64, Literal[8]]
|
||||
GfxclkBelowHostLimitThmAcc: c.Array[ctypes.c_uint64, Literal[8]]
|
||||
GfxclkBelowHostLimitTotalAcc: c.Array[ctypes.c_uint64, Literal[8]]
|
||||
GfxclkLowUtilizationAcc: c.Array[ctypes.c_uint64, Literal[8]]
|
||||
AidTemperature: c.Array[ctypes.c_uint32, Literal[4]]
|
||||
XcdTemperature: c.Array[ctypes.c_uint32, Literal[8]]
|
||||
HbmTemperature: c.Array[ctypes.c_uint32, Literal[8]]
|
||||
uint64_t: TypeAlias = ctypes.c_uint64
|
||||
uint32_t: TypeAlias = ctypes.c_uint32
|
||||
MetricsTable_t.register_fields([('AccumulationCounter', uint64_t, 0), ('MaxSocketTemperature', uint32_t, 8), ('MaxVrTemperature', uint32_t, 12), ('MaxHbmTemperature', uint32_t, 16), ('MaxSocketTemperatureAcc', uint64_t, 20), ('MaxVrTemperatureAcc', uint64_t, 28), ('MaxHbmTemperatureAcc', uint64_t, 36), ('SocketPowerLimit', uint32_t, 44), ('SocketPower', uint32_t, 48), ('Timestamp', uint64_t, 52), ('SocketEnergyAcc', uint64_t, 60), ('XcdEnergyAcc', uint64_t, 68), ('AidEnergyAcc', uint64_t, 76), ('HbmEnergyAcc', uint64_t, 84), ('GfxclkFrequencyLimit', uint32_t, 92), ('FclkFrequency', uint32_t, 96), ('UclkFrequency', uint32_t, 100), ('SocclkFrequency', c.Array[uint32_t, Literal[4]], 104), ('VclkFrequency', c.Array[uint32_t, Literal[4]], 120), ('DclkFrequency', c.Array[uint32_t, Literal[4]], 136), ('LclkFrequency', c.Array[uint32_t, Literal[4]], 152), ('GfxclkFrequencyAcc', c.Array[uint64_t, Literal[8]], 168), ('MaxLclkDpmRange', uint32_t, 232), ('MinLclkDpmRange', uint32_t, 236), ('XgmiWidth', uint32_t, 240), ('XgmiBitrate', uint32_t, 244), ('XgmiReadBandwidthAcc', c.Array[uint64_t, Literal[8]], 248), ('XgmiWriteBandwidthAcc', c.Array[uint64_t, Literal[8]], 312), ('SocketGfxBusy', uint32_t, 376), ('DramBandwidthUtilization', uint32_t, 380), ('SocketGfxBusyAcc', uint64_t, 384), ('DramBandwidthAcc', uint64_t, 392), ('MaxDramBandwidth', uint32_t, 400), ('DramBandwidthUtilizationAcc', uint64_t, 404), ('PcieBandwidthAcc', c.Array[uint64_t, Literal[4]], 412), ('ProchotResidencyAcc', uint32_t, 444), ('PptResidencyAcc', uint32_t, 448), ('SocketThmResidencyAcc', uint32_t, 452), ('VrThmResidencyAcc', uint32_t, 456), ('HbmThmResidencyAcc', uint32_t, 460), ('GfxLockXCDMak', uint32_t, 464), ('GfxclkFrequency', c.Array[uint32_t, Literal[8]], 468), ('XgmiReadDataSizeAcc', c.Array[uint64_t, Literal[8]], 500), ('XgmiWriteDataSizeAcc', c.Array[uint64_t, Literal[8]], 564), ('PcieBandwidth', c.Array[uint32_t, Literal[4]], 628), ('PCIeL0ToRecoveryCountAcc', uint32_t, 644), ('PCIenReplayAAcc', uint32_t, 648), ('PCIenReplayARolloverCountAcc', uint32_t, 652), ('PCIeNAKSentCountAcc', uint32_t, 656), ('PCIeNAKReceivedCountAcc', uint32_t, 660), ('VcnBusy', c.Array[uint32_t, Literal[4]], 664), ('JpegBusy', c.Array[uint32_t, Literal[40]], 680), ('PCIeLinkSpeed', uint32_t, 840), ('PCIeLinkWidth', uint32_t, 844), ('GfxBusy', c.Array[uint32_t, Literal[8]], 848), ('GfxBusyAcc', c.Array[uint64_t, Literal[8]], 880), ('PCIeOtherEndRecoveryAcc', uint32_t, 944), ('GfxclkBelowHostLimitPptAcc', c.Array[uint64_t, Literal[8]], 948), ('GfxclkBelowHostLimitThmAcc', c.Array[uint64_t, Literal[8]], 1012), ('GfxclkBelowHostLimitTotalAcc', c.Array[uint64_t, Literal[8]], 1076), ('GfxclkLowUtilizationAcc', c.Array[uint64_t, Literal[8]], 1140), ('AidTemperature', c.Array[uint32_t, Literal[4]], 1204), ('XcdTemperature', c.Array[uint32_t, Literal[8]], 1220), ('HbmTemperature', c.Array[uint32_t, Literal[8]], 1252)])
|
||||
@c.record
|
||||
class SystemMetricsTable_t(c.Struct):
|
||||
SIZE = 152
|
||||
AccumulationCounter: int
|
||||
LabelVersion: int
|
||||
NodeIdentifier: int
|
||||
SystemTemperatures: c.Array[ctypes.c_int16, Literal[32]]
|
||||
NodeTemperatures: c.Array[ctypes.c_int16, Literal[12]]
|
||||
VrTemperatures: c.Array[ctypes.c_int16, Literal[13]]
|
||||
spare: c.Array[ctypes.c_int16, Literal[7]]
|
||||
NodePowerLimit: int
|
||||
NodePower: int
|
||||
GlobalPPTResidencyAcc: int
|
||||
uint16_t: TypeAlias = ctypes.c_uint16
|
||||
int16_t: TypeAlias = ctypes.c_int16
|
||||
SystemMetricsTable_t.register_fields([('AccumulationCounter', uint64_t, 0), ('LabelVersion', uint16_t, 8), ('NodeIdentifier', uint16_t, 10), ('SystemTemperatures', c.Array[int16_t, Literal[32]], 12), ('NodeTemperatures', c.Array[int16_t, Literal[12]], 76), ('VrTemperatures', c.Array[int16_t, Literal[13]], 100), ('spare', c.Array[int16_t, Literal[7]], 126), ('NodePowerLimit', uint32_t, 140), ('NodePower', uint32_t, 144), ('GlobalPPTResidencyAcc', uint32_t, 148)])
|
||||
@c.record
|
||||
class VfMetricsTable_t(c.Struct):
|
||||
SIZE = 56
|
||||
AccumulationCounter: int
|
||||
InstGfxclk_TargFreq: int
|
||||
AccGfxclk_TargFreq: int
|
||||
AccGfxRsmuDpm_Busy: int
|
||||
AccGfxclkBelowHostLimitPpt: int
|
||||
AccGfxclkBelowHostLimitThm: int
|
||||
AccGfxclkBelowHostLimitTotal: int
|
||||
AccGfxclkLowUtilization: int
|
||||
VfMetricsTable_t.register_fields([('AccumulationCounter', uint32_t, 0), ('InstGfxclk_TargFreq', uint32_t, 4), ('AccGfxclk_TargFreq', uint64_t, 8), ('AccGfxRsmuDpm_Busy', uint64_t, 16), ('AccGfxclkBelowHostLimitPpt', uint64_t, 24), ('AccGfxclkBelowHostLimitThm', uint64_t, 32), ('AccGfxclkBelowHostLimitTotal', uint64_t, 40), ('AccGfxclkLowUtilization', uint64_t, 48)])
|
||||
@c.record
|
||||
class FRUProductInfo_t(c.Struct):
|
||||
SIZE = 168
|
||||
ModelNumber: c.Array[ctypes.c_ubyte, Literal[20]]
|
||||
Name: c.Array[ctypes.c_ubyte, Literal[64]]
|
||||
Serial: c.Array[ctypes.c_ubyte, Literal[20]]
|
||||
ManufacturerName: c.Array[ctypes.c_ubyte, Literal[32]]
|
||||
FruId: c.Array[ctypes.c_ubyte, Literal[32]]
|
||||
uint8_t: TypeAlias = ctypes.c_ubyte
|
||||
FRUProductInfo_t.register_fields([('ModelNumber', c.Array[uint8_t, Literal[20]], 0), ('Name', c.Array[uint8_t, Literal[64]], 20), ('Serial', c.Array[uint8_t, Literal[20]], 84), ('ManufacturerName', c.Array[uint8_t, Literal[32]], 104), ('FruId', c.Array[uint8_t, Literal[32]], 136)])
|
||||
@c.record
|
||||
class StaticMetricsTable_t(c.Struct):
|
||||
SIZE = 408
|
||||
ProductInfo: FRUProductInfo_t
|
||||
MaxSocketPowerLimit: int
|
||||
MaxGfxclkFrequency: int
|
||||
MinGfxclkFrequency: int
|
||||
FclkFrequencyTable: c.Array[ctypes.c_uint32, Literal[4]]
|
||||
UclkFrequencyTable: c.Array[ctypes.c_uint32, Literal[4]]
|
||||
SocclkFrequencyTable: c.Array[ctypes.c_uint32, Literal[4]]
|
||||
VclkFrequencyTable: c.Array[ctypes.c_uint32, Literal[4]]
|
||||
DclkFrequencyTable: c.Array[ctypes.c_uint32, Literal[4]]
|
||||
LclkFrequencyTable: c.Array[ctypes.c_uint32, Literal[4]]
|
||||
PublicSerialNumber_AID: c.Array[ctypes.c_uint64, Literal[4]]
|
||||
PublicSerialNumber_XCD: c.Array[ctypes.c_uint64, Literal[8]]
|
||||
MaxXgmiWidth: int
|
||||
MaxXgmiBitrate: int
|
||||
InputTelemetryVoltageInmV: int
|
||||
pldmVersion: c.Array[ctypes.c_uint32, Literal[2]]
|
||||
MaxNodePowerLimit: int
|
||||
PPT1Max: int
|
||||
PPT1Min: int
|
||||
PPT1Default: int
|
||||
StaticMetricsTable_t.register_fields([('ProductInfo', FRUProductInfo_t, 0), ('MaxSocketPowerLimit', uint32_t, 168), ('MaxGfxclkFrequency', uint32_t, 172), ('MinGfxclkFrequency', uint32_t, 176), ('FclkFrequencyTable', c.Array[uint32_t, Literal[4]], 180), ('UclkFrequencyTable', c.Array[uint32_t, Literal[4]], 196), ('SocclkFrequencyTable', c.Array[uint32_t, Literal[4]], 212), ('VclkFrequencyTable', c.Array[uint32_t, Literal[4]], 228), ('DclkFrequencyTable', c.Array[uint32_t, Literal[4]], 244), ('LclkFrequencyTable', c.Array[uint32_t, Literal[4]], 260), ('PublicSerialNumber_AID', c.Array[uint64_t, Literal[4]], 276), ('PublicSerialNumber_XCD', c.Array[uint64_t, Literal[8]], 308), ('MaxXgmiWidth', uint32_t, 372), ('MaxXgmiBitrate', uint32_t, 376), ('InputTelemetryVoltageInmV', uint32_t, 380), ('pldmVersion', c.Array[uint32_t, Literal[2]], 384), ('MaxNodePowerLimit', uint32_t, 392), ('PPT1Max', uint32_t, 396), ('PPT1Min', uint32_t, 400), ('PPT1Default', uint32_t, 404)])
|
||||
I2cControllerPort_e: dict[int, str] = {(I2C_CONTROLLER_PORT_0:=0): 'I2C_CONTROLLER_PORT_0', (I2C_CONTROLLER_PORT_1:=1): 'I2C_CONTROLLER_PORT_1', (I2C_CONTROLLER_PORT_COUNT:=2): 'I2C_CONTROLLER_PORT_COUNT'}
|
||||
I2cSpeed_e: dict[int, str] = {(UNSUPPORTED_1:=0): 'UNSUPPORTED_1', (I2C_SPEED_STANDARD_100K:=1): 'I2C_SPEED_STANDARD_100K', (I2C_SPEED_FAST_400K:=2): 'I2C_SPEED_FAST_400K', (I2C_SPEED_FAST_PLUS_1M:=3): 'I2C_SPEED_FAST_PLUS_1M', (UNSUPPORTED_2:=4): 'UNSUPPORTED_2', (UNSUPPORTED_3:=5): 'UNSUPPORTED_3', (I2C_SPEED_COUNT:=6): 'I2C_SPEED_COUNT'}
|
||||
I2cCmdType_e: dict[int, str] = {(I2C_CMD_READ:=0): 'I2C_CMD_READ', (I2C_CMD_WRITE:=1): 'I2C_CMD_WRITE', (I2C_CMD_COUNT:=2): 'I2C_CMD_COUNT'}
|
||||
ERR_CODE_e: dict[int, str] = {(CODE_DAGB0:=0): 'CODE_DAGB0', (CODE_EA0:=5): 'CODE_EA0', (CODE_UTCL2_ROUTER:=10): 'CODE_UTCL2_ROUTER', (CODE_VML2:=11): 'CODE_VML2', (CODE_VML2_WALKER:=12): 'CODE_VML2_WALKER', (CODE_MMCANE:=13): 'CODE_MMCANE', (CODE_VIDD:=14): 'CODE_VIDD', (CODE_VIDV:=15): 'CODE_VIDV', (CODE_JPEG0S:=16): 'CODE_JPEG0S', (CODE_JPEG0D:=17): 'CODE_JPEG0D', (CODE_JPEG1S:=18): 'CODE_JPEG1S', (CODE_JPEG1D:=19): 'CODE_JPEG1D', (CODE_JPEG2S:=20): 'CODE_JPEG2S', (CODE_JPEG2D:=21): 'CODE_JPEG2D', (CODE_JPEG3S:=22): 'CODE_JPEG3S', (CODE_JPEG3D:=23): 'CODE_JPEG3D', (CODE_JPEG4S:=24): 'CODE_JPEG4S', (CODE_JPEG4D:=25): 'CODE_JPEG4D', (CODE_JPEG5S:=26): 'CODE_JPEG5S', (CODE_JPEG5D:=27): 'CODE_JPEG5D', (CODE_JPEG6S:=28): 'CODE_JPEG6S', (CODE_JPEG6D:=29): 'CODE_JPEG6D', (CODE_JPEG7S:=30): 'CODE_JPEG7S', (CODE_JPEG7D:=31): 'CODE_JPEG7D', (CODE_MMSCHD:=32): 'CODE_MMSCHD', (CODE_SDMA0:=33): 'CODE_SDMA0', (CODE_SDMA1:=34): 'CODE_SDMA1', (CODE_SDMA2:=35): 'CODE_SDMA2', (CODE_SDMA3:=36): 'CODE_SDMA3', (CODE_HDP:=37): 'CODE_HDP', (CODE_ATHUB:=38): 'CODE_ATHUB', (CODE_IH:=39): 'CODE_IH', (CODE_XHUB_POISON:=40): 'CODE_XHUB_POISON', (CODE_SMN_SLVERR:=40): 'CODE_SMN_SLVERR', (CODE_WDT:=41): 'CODE_WDT', (CODE_UNKNOWN:=42): 'CODE_UNKNOWN', (CODE_COUNT:=43): 'CODE_COUNT'}
|
||||
GC_ERROR_CODE_e: dict[int, str] = {(SH_FED_CODE:=0): 'SH_FED_CODE', (GCEA_CODE:=1): 'GCEA_CODE', (SQ_CODE:=2): 'SQ_CODE', (LDS_CODE:=3): 'LDS_CODE', (GDS_CODE:=4): 'GDS_CODE', (SP0_CODE:=5): 'SP0_CODE', (SP1_CODE:=6): 'SP1_CODE', (TCC_CODE:=7): 'TCC_CODE', (TCA_CODE:=8): 'TCA_CODE', (TCX_CODE:=9): 'TCX_CODE', (CPC_CODE:=10): 'CPC_CODE', (CPF_CODE:=11): 'CPF_CODE', (CPG_CODE:=12): 'CPG_CODE', (SPI_CODE:=13): 'SPI_CODE', (RLC_CODE:=14): 'RLC_CODE', (SQC_CODE:=15): 'SQC_CODE', (TA_CODE:=16): 'TA_CODE', (TD_CODE:=17): 'TD_CODE', (TCP_CODE:=18): 'TCP_CODE', (TCI_CODE:=19): 'TCI_CODE', (GC_ROUTER_CODE:=20): 'GC_ROUTER_CODE', (VML2_CODE:=21): 'VML2_CODE', (VML2_WALKER_CODE:=22): 'VML2_WALKER_CODE', (ATCL2_CODE:=23): 'ATCL2_CODE', (GC_CANE_CODE:=24): 'GC_CANE_CODE', (MP5_CODE_SMN_SLVERR:=40): 'MP5_CODE_SMN_SLVERR', (MP5_CODE_UNKNOWN:=42): 'MP5_CODE_UNKNOWN'}
|
||||
@c.record
|
||||
class SwI2cCmd_t(c.Struct):
|
||||
SIZE = 2
|
||||
ReadWriteData: int
|
||||
CmdConfig: int
|
||||
SwI2cCmd_t.register_fields([('ReadWriteData', uint8_t, 0), ('CmdConfig', uint8_t, 1)])
|
||||
@c.record
|
||||
class SwI2cRequest_t(c.Struct):
|
||||
SIZE = 52
|
||||
I2CcontrollerPort: int
|
||||
I2CSpeed: int
|
||||
SlaveAddress: int
|
||||
NumCmds: int
|
||||
SwI2cCmds: c.Array[SwI2cCmd_t, Literal[24]]
|
||||
SwI2cRequest_t.register_fields([('I2CcontrollerPort', uint8_t, 0), ('I2CSpeed', uint8_t, 1), ('SlaveAddress', uint8_t, 2), ('NumCmds', uint8_t, 3), ('SwI2cCmds', c.Array[SwI2cCmd_t, Literal[24]], 4)])
|
||||
@c.record
|
||||
class SwI2cRequestExternal_t(c.Struct):
|
||||
SIZE = 116
|
||||
SwI2cRequest: SwI2cRequest_t
|
||||
Spare: c.Array[ctypes.c_uint32, Literal[8]]
|
||||
MmHubPadding: c.Array[ctypes.c_uint32, Literal[8]]
|
||||
SwI2cRequestExternal_t.register_fields([('SwI2cRequest', SwI2cRequest_t, 0), ('Spare', c.Array[uint32_t, Literal[8]], 52), ('MmHubPadding', c.Array[uint32_t, Literal[8]], 84)])
|
||||
PPCLK_e: dict[int, str] = {(PPCLK_VCLK:=0): 'PPCLK_VCLK', (PPCLK_DCLK:=1): 'PPCLK_DCLK', (PPCLK_SOCCLK:=2): 'PPCLK_SOCCLK', (PPCLK_UCLK:=3): 'PPCLK_UCLK', (PPCLK_FCLK:=4): 'PPCLK_FCLK', (PPCLK_LCLK:=5): 'PPCLK_LCLK', (PPCLK_COUNT:=6): 'PPCLK_COUNT'}
|
||||
GpioIntPolarity_e: dict[int, str] = {(GPIO_INT_POLARITY_ACTIVE_LOW:=0): 'GPIO_INT_POLARITY_ACTIVE_LOW', (GPIO_INT_POLARITY_ACTIVE_HIGH:=1): 'GPIO_INT_POLARITY_ACTIVE_HIGH'}
|
||||
UCLK_DPM_MODE_e: dict[int, str] = {(UCLK_DPM_MODE_BANDWIDTH:=0): 'UCLK_DPM_MODE_BANDWIDTH', (UCLK_DPM_MODE_LATENCY:=1): 'UCLK_DPM_MODE_LATENCY'}
|
||||
@c.record
|
||||
class AvfsDebugTableAid_t(c.Struct):
|
||||
SIZE = 360
|
||||
avgPsmCount: c.Array[ctypes.c_uint16, Literal[30]]
|
||||
minPsmCount: c.Array[ctypes.c_uint16, Literal[30]]
|
||||
avgPsmVoltage: c.Array[ctypes.c_float, Literal[30]]
|
||||
minPsmVoltage: c.Array[ctypes.c_float, Literal[30]]
|
||||
AvfsDebugTableAid_t.register_fields([('avgPsmCount', c.Array[uint16_t, Literal[30]], 0), ('minPsmCount', c.Array[uint16_t, Literal[30]], 60), ('avgPsmVoltage', c.Array[ctypes.c_float, Literal[30]], 120), ('minPsmVoltage', c.Array[ctypes.c_float, Literal[30]], 240)])
|
||||
@c.record
|
||||
class AvfsDebugTableXcd_t(c.Struct):
|
||||
SIZE = 360
|
||||
avgPsmCount: c.Array[ctypes.c_uint16, Literal[30]]
|
||||
minPsmCount: c.Array[ctypes.c_uint16, Literal[30]]
|
||||
avgPsmVoltage: c.Array[ctypes.c_float, Literal[30]]
|
||||
minPsmVoltage: c.Array[ctypes.c_float, Literal[30]]
|
||||
AvfsDebugTableXcd_t.register_fields([('avgPsmCount', c.Array[uint16_t, Literal[30]], 0), ('minPsmCount', c.Array[uint16_t, Literal[30]], 60), ('avgPsmVoltage', c.Array[ctypes.c_float, Literal[30]], 120), ('minPsmVoltage', c.Array[ctypes.c_float, Literal[30]], 240)])
|
||||
@c.record
|
||||
class struct_smu_hw_power_state(c.Struct):
|
||||
SIZE = 4
|
||||
magic: int
|
||||
struct_smu_hw_power_state.register_fields([('magic', ctypes.c_uint32, 0)])
|
||||
class struct_smu_power_state(c.Struct): pass
|
||||
enum_smu_state_ui_label: dict[int, str] = {(SMU_STATE_UI_LABEL_NONE:=0): 'SMU_STATE_UI_LABEL_NONE', (SMU_STATE_UI_LABEL_BATTERY:=1): 'SMU_STATE_UI_LABEL_BATTERY', (SMU_STATE_UI_TABEL_MIDDLE_LOW:=2): 'SMU_STATE_UI_TABEL_MIDDLE_LOW', (SMU_STATE_UI_LABEL_BALLANCED:=3): 'SMU_STATE_UI_LABEL_BALLANCED', (SMU_STATE_UI_LABEL_MIDDLE_HIGHT:=4): 'SMU_STATE_UI_LABEL_MIDDLE_HIGHT', (SMU_STATE_UI_LABEL_PERFORMANCE:=5): 'SMU_STATE_UI_LABEL_PERFORMANCE', (SMU_STATE_UI_LABEL_BACO:=6): 'SMU_STATE_UI_LABEL_BACO'}
|
||||
enum_smu_state_classification_flag: dict[int, str] = {(SMU_STATE_CLASSIFICATION_FLAG_BOOT:=1): 'SMU_STATE_CLASSIFICATION_FLAG_BOOT', (SMU_STATE_CLASSIFICATION_FLAG_THERMAL:=2): 'SMU_STATE_CLASSIFICATION_FLAG_THERMAL', (SMU_STATE_CLASSIFICATIN_FLAG_LIMITED_POWER_SOURCE:=4): 'SMU_STATE_CLASSIFICATIN_FLAG_LIMITED_POWER_SOURCE', (SMU_STATE_CLASSIFICATION_FLAG_RESET:=8): 'SMU_STATE_CLASSIFICATION_FLAG_RESET', (SMU_STATE_CLASSIFICATION_FLAG_FORCED:=16): 'SMU_STATE_CLASSIFICATION_FLAG_FORCED', (SMU_STATE_CLASSIFICATION_FLAG_USER_3D_PERFORMANCE:=32): 'SMU_STATE_CLASSIFICATION_FLAG_USER_3D_PERFORMANCE', (SMU_STATE_CLASSIFICATION_FLAG_USER_2D_PERFORMANCE:=64): 'SMU_STATE_CLASSIFICATION_FLAG_USER_2D_PERFORMANCE', (SMU_STATE_CLASSIFICATION_FLAG_3D_PERFORMANCE:=128): 'SMU_STATE_CLASSIFICATION_FLAG_3D_PERFORMANCE', (SMU_STATE_CLASSIFICATION_FLAG_AC_OVERDIRVER_TEMPLATE:=256): 'SMU_STATE_CLASSIFICATION_FLAG_AC_OVERDIRVER_TEMPLATE', (SMU_STATE_CLASSIFICATION_FLAG_UVD:=512): 'SMU_STATE_CLASSIFICATION_FLAG_UVD', (SMU_STATE_CLASSIFICATION_FLAG_3D_PERFORMANCE_LOW:=1024): 'SMU_STATE_CLASSIFICATION_FLAG_3D_PERFORMANCE_LOW', (SMU_STATE_CLASSIFICATION_FLAG_ACPI:=2048): 'SMU_STATE_CLASSIFICATION_FLAG_ACPI', (SMU_STATE_CLASSIFICATION_FLAG_HD2:=4096): 'SMU_STATE_CLASSIFICATION_FLAG_HD2', (SMU_STATE_CLASSIFICATION_FLAG_UVD_HD:=8192): 'SMU_STATE_CLASSIFICATION_FLAG_UVD_HD', (SMU_STATE_CLASSIFICATION_FLAG_UVD_SD:=16384): 'SMU_STATE_CLASSIFICATION_FLAG_UVD_SD', (SMU_STATE_CLASSIFICATION_FLAG_USER_DC_PERFORMANCE:=32768): 'SMU_STATE_CLASSIFICATION_FLAG_USER_DC_PERFORMANCE', (SMU_STATE_CLASSIFICATION_FLAG_DC_OVERDIRVER_TEMPLATE:=65536): 'SMU_STATE_CLASSIFICATION_FLAG_DC_OVERDIRVER_TEMPLATE', (SMU_STATE_CLASSIFICATION_FLAG_BACO:=131072): 'SMU_STATE_CLASSIFICATION_FLAG_BACO', (SMU_STATE_CLASSIFICATIN_FLAG_LIMITED_POWER_SOURCE2:=262144): 'SMU_STATE_CLASSIFICATIN_FLAG_LIMITED_POWER_SOURCE2', (SMU_STATE_CLASSIFICATION_FLAG_ULV:=524288): 'SMU_STATE_CLASSIFICATION_FLAG_ULV', (SMU_STATE_CLASSIFICATION_FLAG_UVD_MVC:=1048576): 'SMU_STATE_CLASSIFICATION_FLAG_UVD_MVC'}
|
||||
@c.record
|
||||
class struct_smu_state_classification_block(c.Struct):
|
||||
SIZE = 16
|
||||
ui_label: int
|
||||
flags: int
|
||||
bios_index: int
|
||||
temporary_state: bool
|
||||
to_be_deleted: bool
|
||||
struct_smu_state_classification_block.register_fields([('ui_label', ctypes.c_uint32, 0), ('flags', ctypes.c_uint32, 4), ('bios_index', ctypes.c_int32, 8), ('temporary_state', ctypes.c_bool, 12), ('to_be_deleted', ctypes.c_bool, 13)])
|
||||
@c.record
|
||||
class struct_smu_state_pcie_block(c.Struct):
|
||||
SIZE = 4
|
||||
lanes: int
|
||||
struct_smu_state_pcie_block.register_fields([('lanes', ctypes.c_uint32, 0)])
|
||||
enum_smu_refreshrate_source: dict[int, str] = {(SMU_REFRESHRATE_SOURCE_EDID:=0): 'SMU_REFRESHRATE_SOURCE_EDID', (SMU_REFRESHRATE_SOURCE_EXPLICIT:=1): 'SMU_REFRESHRATE_SOURCE_EXPLICIT'}
|
||||
@c.record
|
||||
class struct_smu_state_display_block(c.Struct):
|
||||
SIZE = 20
|
||||
disable_frame_modulation: bool
|
||||
limit_refreshrate: bool
|
||||
refreshrate_source: int
|
||||
explicit_refreshrate: int
|
||||
edid_refreshrate_index: int
|
||||
enable_vari_bright: bool
|
||||
struct_smu_state_display_block.register_fields([('disable_frame_modulation', ctypes.c_bool, 0), ('limit_refreshrate', ctypes.c_bool, 1), ('refreshrate_source', ctypes.c_uint32, 4), ('explicit_refreshrate', ctypes.c_int32, 8), ('edid_refreshrate_index', ctypes.c_int32, 12), ('enable_vari_bright', ctypes.c_bool, 16)])
|
||||
@c.record
|
||||
class struct_smu_state_memory_block(c.Struct):
|
||||
SIZE = 5
|
||||
dll_off: bool
|
||||
m3arb: int
|
||||
unused: c.Array[ctypes.c_ubyte, Literal[3]]
|
||||
struct_smu_state_memory_block.register_fields([('dll_off', ctypes.c_bool, 0), ('m3arb', uint8_t, 1), ('unused', c.Array[uint8_t, Literal[3]], 2)])
|
||||
@c.record
|
||||
class struct_smu_state_software_algorithm_block(c.Struct):
|
||||
SIZE = 2
|
||||
disable_load_balancing: bool
|
||||
enable_sleep_for_timestamps: bool
|
||||
struct_smu_state_software_algorithm_block.register_fields([('disable_load_balancing', ctypes.c_bool, 0), ('enable_sleep_for_timestamps', ctypes.c_bool, 1)])
|
||||
@c.record
|
||||
class struct_smu_temperature_range(c.Struct):
|
||||
SIZE = 44
|
||||
min: int
|
||||
max: int
|
||||
edge_emergency_max: int
|
||||
hotspot_min: int
|
||||
hotspot_crit_max: int
|
||||
hotspot_emergency_max: int
|
||||
mem_min: int
|
||||
mem_crit_max: int
|
||||
mem_emergency_max: int
|
||||
software_shutdown_temp: int
|
||||
software_shutdown_temp_offset: int
|
||||
struct_smu_temperature_range.register_fields([('min', ctypes.c_int32, 0), ('max', ctypes.c_int32, 4), ('edge_emergency_max', ctypes.c_int32, 8), ('hotspot_min', ctypes.c_int32, 12), ('hotspot_crit_max', ctypes.c_int32, 16), ('hotspot_emergency_max', ctypes.c_int32, 20), ('mem_min', ctypes.c_int32, 24), ('mem_crit_max', ctypes.c_int32, 28), ('mem_emergency_max', ctypes.c_int32, 32), ('software_shutdown_temp', ctypes.c_int32, 36), ('software_shutdown_temp_offset', ctypes.c_int32, 40)])
|
||||
@c.record
|
||||
class struct_smu_state_validation_block(c.Struct):
|
||||
SIZE = 3
|
||||
single_display_only: bool
|
||||
disallow_on_dc: bool
|
||||
supported_power_levels: int
|
||||
struct_smu_state_validation_block.register_fields([('single_display_only', ctypes.c_bool, 0), ('disallow_on_dc', ctypes.c_bool, 1), ('supported_power_levels', uint8_t, 2)])
|
||||
@c.record
|
||||
class struct_smu_uvd_clocks(c.Struct):
|
||||
SIZE = 8
|
||||
vclk: int
|
||||
dclk: int
|
||||
struct_smu_uvd_clocks.register_fields([('vclk', uint32_t, 0), ('dclk', uint32_t, 4)])
|
||||
enum_smu_power_src_type: dict[int, str] = {(SMU_POWER_SOURCE_AC:=0): 'SMU_POWER_SOURCE_AC', (SMU_POWER_SOURCE_DC:=1): 'SMU_POWER_SOURCE_DC', (SMU_POWER_SOURCE_COUNT:=2): 'SMU_POWER_SOURCE_COUNT'}
|
||||
enum_smu_ppt_limit_type: dict[int, str] = {(SMU_DEFAULT_PPT_LIMIT:=0): 'SMU_DEFAULT_PPT_LIMIT', (SMU_FAST_PPT_LIMIT:=1): 'SMU_FAST_PPT_LIMIT'}
|
||||
enum_smu_ppt_limit_level: dict[int, str] = {(SMU_PPT_LIMIT_MIN:=-1): 'SMU_PPT_LIMIT_MIN', (SMU_PPT_LIMIT_CURRENT:=0): 'SMU_PPT_LIMIT_CURRENT', (SMU_PPT_LIMIT_DEFAULT:=1): 'SMU_PPT_LIMIT_DEFAULT', (SMU_PPT_LIMIT_MAX:=2): 'SMU_PPT_LIMIT_MAX'}
|
||||
enum_smu_memory_pool_size: dict[int, str] = {(SMU_MEMORY_POOL_SIZE_ZERO:=0): 'SMU_MEMORY_POOL_SIZE_ZERO', (SMU_MEMORY_POOL_SIZE_256_MB:=268435456): 'SMU_MEMORY_POOL_SIZE_256_MB', (SMU_MEMORY_POOL_SIZE_512_MB:=536870912): 'SMU_MEMORY_POOL_SIZE_512_MB', (SMU_MEMORY_POOL_SIZE_1_GB:=1073741824): 'SMU_MEMORY_POOL_SIZE_1_GB', (SMU_MEMORY_POOL_SIZE_2_GB:=2147483648): 'SMU_MEMORY_POOL_SIZE_2_GB'}
|
||||
enum_smu_clk_type: dict[int, str] = {(SMU_GFXCLK:=0): 'SMU_GFXCLK', (SMU_VCLK:=1): 'SMU_VCLK', (SMU_DCLK:=2): 'SMU_DCLK', (SMU_VCLK1:=3): 'SMU_VCLK1', (SMU_DCLK1:=4): 'SMU_DCLK1', (SMU_ECLK:=5): 'SMU_ECLK', (SMU_SOCCLK:=6): 'SMU_SOCCLK', (SMU_UCLK:=7): 'SMU_UCLK', (SMU_DCEFCLK:=8): 'SMU_DCEFCLK', (SMU_DISPCLK:=9): 'SMU_DISPCLK', (SMU_PIXCLK:=10): 'SMU_PIXCLK', (SMU_PHYCLK:=11): 'SMU_PHYCLK', (SMU_FCLK:=12): 'SMU_FCLK', (SMU_SCLK:=13): 'SMU_SCLK', (SMU_MCLK:=14): 'SMU_MCLK', (SMU_PCIE:=15): 'SMU_PCIE', (SMU_LCLK:=16): 'SMU_LCLK', (SMU_OD_CCLK:=17): 'SMU_OD_CCLK', (SMU_OD_SCLK:=18): 'SMU_OD_SCLK', (SMU_OD_MCLK:=19): 'SMU_OD_MCLK', (SMU_OD_VDDC_CURVE:=20): 'SMU_OD_VDDC_CURVE', (SMU_OD_RANGE:=21): 'SMU_OD_RANGE', (SMU_OD_VDDGFX_OFFSET:=22): 'SMU_OD_VDDGFX_OFFSET', (SMU_OD_FAN_CURVE:=23): 'SMU_OD_FAN_CURVE', (SMU_OD_ACOUSTIC_LIMIT:=24): 'SMU_OD_ACOUSTIC_LIMIT', (SMU_OD_ACOUSTIC_TARGET:=25): 'SMU_OD_ACOUSTIC_TARGET', (SMU_OD_FAN_TARGET_TEMPERATURE:=26): 'SMU_OD_FAN_TARGET_TEMPERATURE', (SMU_OD_FAN_MINIMUM_PWM:=27): 'SMU_OD_FAN_MINIMUM_PWM', (SMU_CLK_COUNT:=28): 'SMU_CLK_COUNT'}
|
||||
@c.record
|
||||
class struct_smu_user_dpm_profile(c.Struct):
|
||||
SIZE = 140
|
||||
fan_mode: int
|
||||
power_limit: int
|
||||
fan_speed_pwm: int
|
||||
fan_speed_rpm: int
|
||||
flags: int
|
||||
user_od: int
|
||||
clk_mask: c.Array[ctypes.c_uint32, Literal[28]]
|
||||
clk_dependency: int
|
||||
struct_smu_user_dpm_profile.register_fields([('fan_mode', uint32_t, 0), ('power_limit', uint32_t, 4), ('fan_speed_pwm', uint32_t, 8), ('fan_speed_rpm', uint32_t, 12), ('flags', uint32_t, 16), ('user_od', uint32_t, 20), ('clk_mask', c.Array[uint32_t, Literal[28]], 24), ('clk_dependency', uint32_t, 136)])
|
||||
@c.record
|
||||
class struct_smu_table(c.Struct):
|
||||
SIZE = 48
|
||||
size: int
|
||||
align: int
|
||||
domain: int
|
||||
mc_address: int
|
||||
cpu_addr: ctypes.c_void_p
|
||||
bo: c.POINTER[struct_amdgpu_bo]
|
||||
version: int
|
||||
class struct_amdgpu_bo(c.Struct): pass
|
||||
struct_smu_table.register_fields([('size', uint64_t, 0), ('align', uint32_t, 8), ('domain', uint8_t, 12), ('mc_address', uint64_t, 16), ('cpu_addr', ctypes.c_void_p, 24), ('bo', c.POINTER[struct_amdgpu_bo], 32), ('version', uint32_t, 40)])
|
||||
enum_smu_perf_level_designation: dict[int, str] = {(PERF_LEVEL_ACTIVITY:=0): 'PERF_LEVEL_ACTIVITY', (PERF_LEVEL_POWER_CONTAINMENT:=1): 'PERF_LEVEL_POWER_CONTAINMENT'}
|
||||
@c.record
|
||||
class struct_smu_performance_level(c.Struct):
|
||||
SIZE = 24
|
||||
core_clock: int
|
||||
memory_clock: int
|
||||
vddc: int
|
||||
vddci: int
|
||||
non_local_mem_freq: int
|
||||
non_local_mem_width: int
|
||||
struct_smu_performance_level.register_fields([('core_clock', uint32_t, 0), ('memory_clock', uint32_t, 4), ('vddc', uint32_t, 8), ('vddci', uint32_t, 12), ('non_local_mem_freq', uint32_t, 16), ('non_local_mem_width', uint32_t, 20)])
|
||||
@c.record
|
||||
class struct_smu_clock_info(c.Struct):
|
||||
SIZE = 24
|
||||
min_mem_clk: int
|
||||
max_mem_clk: int
|
||||
min_eng_clk: int
|
||||
max_eng_clk: int
|
||||
min_bus_bandwidth: int
|
||||
max_bus_bandwidth: int
|
||||
struct_smu_clock_info.register_fields([('min_mem_clk', uint32_t, 0), ('max_mem_clk', uint32_t, 4), ('min_eng_clk', uint32_t, 8), ('max_eng_clk', uint32_t, 12), ('min_bus_bandwidth', uint32_t, 16), ('max_bus_bandwidth', uint32_t, 20)])
|
||||
@c.record
|
||||
class struct_smu_bios_boot_up_values(c.Struct):
|
||||
SIZE = 68
|
||||
revision: int
|
||||
gfxclk: int
|
||||
uclk: int
|
||||
socclk: int
|
||||
dcefclk: int
|
||||
eclk: int
|
||||
vclk: int
|
||||
dclk: int
|
||||
vddc: int
|
||||
vddci: int
|
||||
mvddc: int
|
||||
vdd_gfx: int
|
||||
cooling_id: int
|
||||
pp_table_id: int
|
||||
format_revision: int
|
||||
content_revision: int
|
||||
fclk: int
|
||||
lclk: int
|
||||
firmware_caps: int
|
||||
struct_smu_bios_boot_up_values.register_fields([('revision', uint32_t, 0), ('gfxclk', uint32_t, 4), ('uclk', uint32_t, 8), ('socclk', uint32_t, 12), ('dcefclk', uint32_t, 16), ('eclk', uint32_t, 20), ('vclk', uint32_t, 24), ('dclk', uint32_t, 28), ('vddc', uint16_t, 32), ('vddci', uint16_t, 34), ('mvddc', uint16_t, 36), ('vdd_gfx', uint16_t, 38), ('cooling_id', uint8_t, 40), ('pp_table_id', uint32_t, 44), ('format_revision', uint32_t, 48), ('content_revision', uint32_t, 52), ('fclk', uint32_t, 56), ('lclk', uint32_t, 60), ('firmware_caps', uint32_t, 64)])
|
||||
enum_smu_table_id: dict[int, str] = {(SMU_TABLE_PPTABLE:=0): 'SMU_TABLE_PPTABLE', (SMU_TABLE_WATERMARKS:=1): 'SMU_TABLE_WATERMARKS', (SMU_TABLE_CUSTOM_DPM:=2): 'SMU_TABLE_CUSTOM_DPM', (SMU_TABLE_DPMCLOCKS:=3): 'SMU_TABLE_DPMCLOCKS', (SMU_TABLE_AVFS:=4): 'SMU_TABLE_AVFS', (SMU_TABLE_AVFS_PSM_DEBUG:=5): 'SMU_TABLE_AVFS_PSM_DEBUG', (SMU_TABLE_AVFS_FUSE_OVERRIDE:=6): 'SMU_TABLE_AVFS_FUSE_OVERRIDE', (SMU_TABLE_PMSTATUSLOG:=7): 'SMU_TABLE_PMSTATUSLOG', (SMU_TABLE_SMU_METRICS:=8): 'SMU_TABLE_SMU_METRICS', (SMU_TABLE_DRIVER_SMU_CONFIG:=9): 'SMU_TABLE_DRIVER_SMU_CONFIG', (SMU_TABLE_ACTIVITY_MONITOR_COEFF:=10): 'SMU_TABLE_ACTIVITY_MONITOR_COEFF', (SMU_TABLE_OVERDRIVE:=11): 'SMU_TABLE_OVERDRIVE', (SMU_TABLE_I2C_COMMANDS:=12): 'SMU_TABLE_I2C_COMMANDS', (SMU_TABLE_PACE:=13): 'SMU_TABLE_PACE', (SMU_TABLE_ECCINFO:=14): 'SMU_TABLE_ECCINFO', (SMU_TABLE_COMBO_PPTABLE:=15): 'SMU_TABLE_COMBO_PPTABLE', (SMU_TABLE_WIFIBAND:=16): 'SMU_TABLE_WIFIBAND', (SMU_TABLE_COUNT:=17): 'SMU_TABLE_COUNT'}
|
||||
PPSMC_Result_OK = 0x1
|
||||
PPSMC_Result_Failed = 0xFF
|
||||
PPSMC_Result_UnknownCmd = 0xFE
|
||||
PPSMC_Result_CmdRejectedPrereq = 0xFD
|
||||
PPSMC_Result_CmdRejectedBusy = 0xFC
|
||||
PPSMC_MSG_TestMessage = 0x1
|
||||
PPSMC_MSG_GetSmuVersion = 0x2
|
||||
PPSMC_MSG_GfxDriverReset = 0x3
|
||||
PPSMC_MSG_GetDriverIfVersion = 0x4
|
||||
PPSMC_MSG_EnableAllSmuFeatures = 0x5
|
||||
PPSMC_MSG_DisableAllSmuFeatures = 0x6
|
||||
PPSMC_MSG_RequestI2cTransaction = 0x7
|
||||
PPSMC_MSG_GetMetricsVersion = 0x8
|
||||
PPSMC_MSG_GetMetricsTable = 0x9
|
||||
PPSMC_MSG_GetEccInfoTable = 0xA
|
||||
PPSMC_MSG_GetEnabledSmuFeaturesLow = 0xB
|
||||
PPSMC_MSG_GetEnabledSmuFeaturesHigh = 0xC
|
||||
PPSMC_MSG_SetDriverDramAddrHigh = 0xD
|
||||
PPSMC_MSG_SetDriverDramAddrLow = 0xE
|
||||
PPSMC_MSG_SetToolsDramAddrHigh = 0xF
|
||||
PPSMC_MSG_SetToolsDramAddrLow = 0x10
|
||||
PPSMC_MSG_SetSystemVirtualDramAddrHigh = 0x11
|
||||
PPSMC_MSG_SetSystemVirtualDramAddrLow = 0x12
|
||||
PPSMC_MSG_SetSoftMinByFreq = 0x13
|
||||
PPSMC_MSG_SetSoftMaxByFreq = 0x14
|
||||
PPSMC_MSG_GetMinDpmFreq = 0x15
|
||||
PPSMC_MSG_GetMaxDpmFreq = 0x16
|
||||
PPSMC_MSG_GetDpmFreqByIndex = 0x17
|
||||
PPSMC_MSG_SetPptLimit = 0x18
|
||||
PPSMC_MSG_GetPptLimit = 0x19
|
||||
PPSMC_MSG_DramLogSetDramAddrHigh = 0x1A
|
||||
PPSMC_MSG_DramLogSetDramAddrLow = 0x1B
|
||||
PPSMC_MSG_DramLogSetDramSize = 0x1C
|
||||
PPSMC_MSG_GetDebugData = 0x1D
|
||||
PPSMC_MSG_HeavySBR = 0x1E
|
||||
PPSMC_MSG_SetNumBadHbmPagesRetired = 0x1F
|
||||
PPSMC_MSG_DFCstateControl = 0x20
|
||||
PPSMC_MSG_GetGmiPwrDnHyst = 0x21
|
||||
PPSMC_MSG_SetGmiPwrDnHyst = 0x22
|
||||
PPSMC_MSG_GmiPwrDnControl = 0x23
|
||||
PPSMC_MSG_EnterGfxoff = 0x24
|
||||
PPSMC_MSG_ExitGfxoff = 0x25
|
||||
PPSMC_MSG_EnableDeterminism = 0x26
|
||||
PPSMC_MSG_DisableDeterminism = 0x27
|
||||
PPSMC_MSG_DumpSTBtoDram = 0x28
|
||||
PPSMC_MSG_STBtoDramLogSetDramAddrHigh = 0x29
|
||||
PPSMC_MSG_STBtoDramLogSetDramAddrLow = 0x2A
|
||||
PPSMC_MSG_STBtoDramLogSetDramSize = 0x2B
|
||||
PPSMC_MSG_SetSystemVirtualSTBtoDramAddrHigh = 0x2C
|
||||
PPSMC_MSG_SetSystemVirtualSTBtoDramAddrLow = 0x2D
|
||||
PPSMC_MSG_GfxDriverResetRecovery = 0x2E
|
||||
PPSMC_MSG_TriggerVFFLR = 0x2F
|
||||
PPSMC_MSG_SetSoftMinGfxClk = 0x30
|
||||
PPSMC_MSG_SetSoftMaxGfxClk = 0x31
|
||||
PPSMC_MSG_GetMinGfxDpmFreq = 0x32
|
||||
PPSMC_MSG_GetMaxGfxDpmFreq = 0x33
|
||||
PPSMC_MSG_PrepareForDriverUnload = 0x34
|
||||
PPSMC_MSG_ReadThrottlerLimit = 0x35
|
||||
PPSMC_MSG_QueryValidMcaCount = 0x36
|
||||
PPSMC_MSG_McaBankDumpDW = 0x37
|
||||
PPSMC_MSG_GetCTFLimit = 0x38
|
||||
PPSMC_MSG_ClearMcaOnRead = 0x39
|
||||
PPSMC_MSG_QueryValidMcaCeCount = 0x3A
|
||||
PPSMC_MSG_McaBankCeDumpDW = 0x3B
|
||||
PPSMC_MSG_SelectPLPDMode = 0x40
|
||||
PPSMC_MSG_PmLogReadSample = 0x41
|
||||
PPSMC_MSG_PmLogGetTableVersion = 0x42
|
||||
PPSMC_MSG_RmaDueToBadPageThreshold = 0x43
|
||||
PPSMC_MSG_SetThrottlingPolicy = 0x44
|
||||
PPSMC_MSG_SetPhaseDetectCSBWThreshold = 0x45
|
||||
PPSMC_MSG_SetPhaseDetectFreqHigh = 0x46
|
||||
PPSMC_MSG_SetPhaseDetectFreqLow = 0x47
|
||||
PPSMC_MSG_SetPhaseDetectDownHysterisis = 0x48
|
||||
PPSMC_MSG_SetPhaseDetectAlphaX1e6 = 0x49
|
||||
PPSMC_MSG_SetPhaseDetectOnOff = 0x4A
|
||||
PPSMC_MSG_GetPhaseDetectResidency = 0x4B
|
||||
PPSMC_MSG_UpdatePccWaitDecMaxStr = 0x4C
|
||||
PPSMC_MSG_ResetSDMA = 0x4D
|
||||
PPSMC_MSG_GetRasTableVersion = 0x4E
|
||||
PPSMC_MSG_GetBadPageCount = 0x50
|
||||
PPSMC_MSG_GetBadPageMcaAddress = 0x51
|
||||
PPSMC_MSG_SetTimestamp = 0x53
|
||||
PPSMC_MSG_SetTimestampHi = 0x54
|
||||
PPSMC_MSG_GetTimestamp = 0x55
|
||||
PPSMC_MSG_GetBadPageIpIdLoHi = 0x57
|
||||
PPSMC_MSG_EraseRasTable = 0x58
|
||||
PPSMC_MSG_GetStaticMetricsTable = 0x59
|
||||
PPSMC_MSG_ResetVfArbitersByIndex = 0x5A
|
||||
PPSMC_MSG_GetSystemMetricsTable = 0x5C
|
||||
PPSMC_MSG_GetSystemMetricsVersion = 0x5D
|
||||
PPSMC_MSG_ResetVCN = 0x5E
|
||||
PPSMC_MSG_SetFastPptLimit = 0x5F
|
||||
PPSMC_MSG_GetFastPptLimit = 0x60
|
||||
PPSMC_Message_Count = 0x61
|
||||
PPSMC_RESET_TYPE_DRIVER_MODE_1_RESET = 0x1
|
||||
PPSMC_RESET_TYPE_DRIVER_MODE_2_RESET = 0x2
|
||||
PPSMC_RESET_TYPE_DRIVER_MODE_3_RESET = 0x3
|
||||
PPSMC_THROTTLING_LIMIT_TYPE_SOCKET = 0x1
|
||||
PPSMC_THROTTLING_LIMIT_TYPE_HBM = 0x2
|
||||
PPSMC_AID_THM_TYPE = 0x1
|
||||
PPSMC_CCD_THM_TYPE = 0x2
|
||||
PPSMC_XCD_THM_TYPE = 0x3
|
||||
PPSMC_HBM_THM_TYPE = 0x4
|
||||
PPSMC_PLPD_MODE_DEFAULT = 0x1
|
||||
PPSMC_PLPD_MODE_OPTIMIZED = 0x2
|
||||
NUM_VCLK_DPM_LEVELS = 4
|
||||
NUM_DCLK_DPM_LEVELS = 4
|
||||
NUM_SOCCLK_DPM_LEVELS = 4
|
||||
NUM_LCLK_DPM_LEVELS = 4
|
||||
NUM_UCLK_DPM_LEVELS = 4
|
||||
NUM_FCLK_DPM_LEVELS = 4
|
||||
NUM_XGMI_DPM_LEVELS = 2
|
||||
NUM_CXL_BITRATES = 4
|
||||
NUM_PCIE_BITRATES = 4
|
||||
NUM_XGMI_BITRATES = 4
|
||||
NUM_XGMI_WIDTHS = 3
|
||||
NUM_TDP_GROUPS = 4
|
||||
NUM_SOC_P2S_TABLES = 6
|
||||
NUM_GFX_P2S_TABLES = 8
|
||||
NUM_PSM_DIDT_THRESHOLDS = 3
|
||||
NUM_XVMIN_VMIN_THRESHOLDS = 3
|
||||
PRODUCT_MODEL_NUMBER_LEN = 20
|
||||
PRODUCT_NAME_LEN = 64
|
||||
PRODUCT_SERIAL_LEN = 20
|
||||
PRODUCT_MANUFACTURER_NAME_LEN = 32
|
||||
PRODUCT_FRU_ID_LEN = 32
|
||||
SMU_METRICS_TABLE_VERSION = 0x15
|
||||
SMU_SYSTEM_METRICS_TABLE_VERSION = 0x1
|
||||
SMU_VF_METRICS_TABLE_MASK = (1 << 31)
|
||||
SMU_VF_METRICS_TABLE_VERSION = (0x6 | SMU_VF_METRICS_TABLE_MASK)
|
||||
SMU13_0_6_DRIVER_IF_VERSION = 0x08042024
|
||||
NUM_I2C_CONTROLLERS = 8
|
||||
I2C_CONTROLLER_ENABLED = 1
|
||||
I2C_CONTROLLER_DISABLED = 0
|
||||
MAX_SW_I2C_COMMANDS = 24
|
||||
CMDCONFIG_STOP_BIT = 0
|
||||
CMDCONFIG_RESTART_BIT = 1
|
||||
CMDCONFIG_READWRITE_BIT = 2
|
||||
CMDCONFIG_STOP_MASK = (1 << CMDCONFIG_STOP_BIT)
|
||||
CMDCONFIG_RESTART_MASK = (1 << CMDCONFIG_RESTART_BIT)
|
||||
CMDCONFIG_READWRITE_MASK = (1 << CMDCONFIG_READWRITE_BIT)
|
||||
IH_INTERRUPT_ID_TO_DRIVER = 0xFE
|
||||
IH_INTERRUPT_CONTEXT_ID_THERMAL_THROTTLING = 0x7
|
||||
THROTTLER_PROCHOT_BIT = 0
|
||||
THROTTLER_PPT_BIT = 1
|
||||
THROTTLER_THERMAL_SOCKET_BIT = 2
|
||||
THROTTLER_THERMAL_VR_BIT = 3
|
||||
THROTTLER_THERMAL_HBM_BIT = 4
|
||||
ClearMcaOnRead_UE_FLAG_MASK = 0x1
|
||||
ClearMcaOnRead_CE_POLL_MASK = 0x2
|
||||
SMU_THERMAL_MINIMUM_ALERT_TEMP = 0
|
||||
SMU_THERMAL_MAXIMUM_ALERT_TEMP = 255
|
||||
SMU_TEMPERATURE_UNITS_PER_CENTIGRADES = 1000
|
||||
SMU_FW_NAME_LEN = 0x24
|
||||
SMU_DPM_USER_PROFILE_RESTORE = (1 << 0)
|
||||
SMU_CUSTOM_FAN_SPEED_RPM = (1 << 1)
|
||||
SMU_CUSTOM_FAN_SPEED_PWM = (1 << 2)
|
||||
SMU_THROTTLER_PPT0_BIT = 0
|
||||
SMU_THROTTLER_PPT1_BIT = 1
|
||||
SMU_THROTTLER_PPT2_BIT = 2
|
||||
SMU_THROTTLER_PPT3_BIT = 3
|
||||
SMU_THROTTLER_SPL_BIT = 4
|
||||
SMU_THROTTLER_FPPT_BIT = 5
|
||||
SMU_THROTTLER_SPPT_BIT = 6
|
||||
SMU_THROTTLER_SPPT_APU_BIT = 7
|
||||
SMU_THROTTLER_TDC_GFX_BIT = 16
|
||||
SMU_THROTTLER_TDC_SOC_BIT = 17
|
||||
SMU_THROTTLER_TDC_MEM_BIT = 18
|
||||
SMU_THROTTLER_TDC_VDD_BIT = 19
|
||||
SMU_THROTTLER_TDC_CVIP_BIT = 20
|
||||
SMU_THROTTLER_EDC_CPU_BIT = 21
|
||||
SMU_THROTTLER_EDC_GFX_BIT = 22
|
||||
SMU_THROTTLER_APCC_BIT = 23
|
||||
SMU_THROTTLER_TEMP_GPU_BIT = 32
|
||||
SMU_THROTTLER_TEMP_CORE_BIT = 33
|
||||
SMU_THROTTLER_TEMP_MEM_BIT = 34
|
||||
SMU_THROTTLER_TEMP_EDGE_BIT = 35
|
||||
SMU_THROTTLER_TEMP_HOTSPOT_BIT = 36
|
||||
SMU_THROTTLER_TEMP_SOC_BIT = 37
|
||||
SMU_THROTTLER_TEMP_VR_GFX_BIT = 38
|
||||
SMU_THROTTLER_TEMP_VR_SOC_BIT = 39
|
||||
SMU_THROTTLER_TEMP_VR_MEM0_BIT = 40
|
||||
SMU_THROTTLER_TEMP_VR_MEM1_BIT = 41
|
||||
SMU_THROTTLER_TEMP_LIQUID0_BIT = 42
|
||||
SMU_THROTTLER_TEMP_LIQUID1_BIT = 43
|
||||
SMU_THROTTLER_VRHOT0_BIT = 44
|
||||
SMU_THROTTLER_VRHOT1_BIT = 45
|
||||
SMU_THROTTLER_PROCHOT_CPU_BIT = 46
|
||||
SMU_THROTTLER_PROCHOT_GFX_BIT = 47
|
||||
SMU_THROTTLER_PPM_BIT = 56
|
||||
SMU_THROTTLER_FIT_BIT = 57
|
||||
617
tinygrad_repo/tinygrad/runtime/autogen/am/smu_13_0_6.py
Normal file
617
tinygrad_repo/tinygrad/runtime/autogen/am/smu_13_0_6.py
Normal file
@@ -0,0 +1,617 @@
|
||||
# mypy: disable-error-code="empty-body"
|
||||
from __future__ import annotations
|
||||
import ctypes
|
||||
from typing import Literal, TypeAlias
|
||||
from tinygrad.runtime.support.c import _IO, _IOW, _IOR, _IOWR
|
||||
from tinygrad.runtime.support import c
|
||||
PPSMC_Result: TypeAlias = ctypes.c_uint32
|
||||
PPSMC_MSG: TypeAlias = ctypes.c_uint32
|
||||
FEATURE_LIST_e: dict[int, str] = {(FEATURE_DATA_CALCULATION:=0): 'FEATURE_DATA_CALCULATION', (FEATURE_DPM_CCLK:=1): 'FEATURE_DPM_CCLK', (FEATURE_DPM_FCLK:=2): 'FEATURE_DPM_FCLK', (FEATURE_DPM_GFXCLK:=3): 'FEATURE_DPM_GFXCLK', (FEATURE_DPM_LCLK:=4): 'FEATURE_DPM_LCLK', (FEATURE_DPM_SOCCLK:=5): 'FEATURE_DPM_SOCCLK', (FEATURE_DPM_UCLK:=6): 'FEATURE_DPM_UCLK', (FEATURE_DPM_VCN:=7): 'FEATURE_DPM_VCN', (FEATURE_DPM_XGMI:=8): 'FEATURE_DPM_XGMI', (FEATURE_DS_FCLK:=9): 'FEATURE_DS_FCLK', (FEATURE_DS_GFXCLK:=10): 'FEATURE_DS_GFXCLK', (FEATURE_DS_LCLK:=11): 'FEATURE_DS_LCLK', (FEATURE_DS_MP0CLK:=12): 'FEATURE_DS_MP0CLK', (FEATURE_DS_MP1CLK:=13): 'FEATURE_DS_MP1CLK', (FEATURE_DS_MPIOCLK:=14): 'FEATURE_DS_MPIOCLK', (FEATURE_DS_SOCCLK:=15): 'FEATURE_DS_SOCCLK', (FEATURE_DS_VCN:=16): 'FEATURE_DS_VCN', (FEATURE_APCC_DFLL:=17): 'FEATURE_APCC_DFLL', (FEATURE_APCC_PLUS:=18): 'FEATURE_APCC_PLUS', (FEATURE_DF_CSTATE:=19): 'FEATURE_DF_CSTATE', (FEATURE_CC6:=20): 'FEATURE_CC6', (FEATURE_PC6:=21): 'FEATURE_PC6', (FEATURE_CPPC:=22): 'FEATURE_CPPC', (FEATURE_PPT:=23): 'FEATURE_PPT', (FEATURE_TDC:=24): 'FEATURE_TDC', (FEATURE_THERMAL:=25): 'FEATURE_THERMAL', (FEATURE_SOC_PCC:=26): 'FEATURE_SOC_PCC', (FEATURE_CCD_PCC:=27): 'FEATURE_CCD_PCC', (FEATURE_CCD_EDC:=28): 'FEATURE_CCD_EDC', (FEATURE_PROCHOT:=29): 'FEATURE_PROCHOT', (FEATURE_DVO_CCLK:=30): 'FEATURE_DVO_CCLK', (FEATURE_FDD_AID_HBM:=31): 'FEATURE_FDD_AID_HBM', (FEATURE_FDD_AID_SOC:=32): 'FEATURE_FDD_AID_SOC', (FEATURE_FDD_XCD_EDC:=33): 'FEATURE_FDD_XCD_EDC', (FEATURE_FDD_XCD_XVMIN:=34): 'FEATURE_FDD_XCD_XVMIN', (FEATURE_FW_CTF:=35): 'FEATURE_FW_CTF', (FEATURE_GFXOFF:=36): 'FEATURE_GFXOFF', (FEATURE_SMU_CG:=37): 'FEATURE_SMU_CG', (FEATURE_PSI7:=38): 'FEATURE_PSI7', (FEATURE_CSTATE_BOOST:=39): 'FEATURE_CSTATE_BOOST', (FEATURE_XGMI_PER_LINK_PWR_DOWN:=40): 'FEATURE_XGMI_PER_LINK_PWR_DOWN', (FEATURE_CXL_QOS:=41): 'FEATURE_CXL_QOS', (FEATURE_SOC_DC_RTC:=42): 'FEATURE_SOC_DC_RTC', (FEATURE_GFX_DC_RTC:=43): 'FEATURE_GFX_DC_RTC', (FEATURE_DVM_MIN_PSM:=44): 'FEATURE_DVM_MIN_PSM', (FEATURE_PRC:=45): 'FEATURE_PRC', (NUM_FEATURES:=46): 'NUM_FEATURES'}
|
||||
PCIE_LINK_SPEED_INDEX_TABLE_e: dict[int, str] = {(PCIE_LINK_SPEED_INDEX_TABLE_GEN1:=0): 'PCIE_LINK_SPEED_INDEX_TABLE_GEN1', (PCIE_LINK_SPEED_INDEX_TABLE_GEN2:=1): 'PCIE_LINK_SPEED_INDEX_TABLE_GEN2', (PCIE_LINK_SPEED_INDEX_TABLE_GEN3:=2): 'PCIE_LINK_SPEED_INDEX_TABLE_GEN3', (PCIE_LINK_SPEED_INDEX_TABLE_GEN4:=3): 'PCIE_LINK_SPEED_INDEX_TABLE_GEN4', (PCIE_LINK_SPEED_INDEX_TABLE_GEN4_ESM:=4): 'PCIE_LINK_SPEED_INDEX_TABLE_GEN4_ESM', (PCIE_LINK_SPEED_INDEX_TABLE_GEN5:=5): 'PCIE_LINK_SPEED_INDEX_TABLE_GEN5', (PCIE_LINK_SPEED_INDEX_TABLE_COUNT:=6): 'PCIE_LINK_SPEED_INDEX_TABLE_COUNT'}
|
||||
GFX_GUARDBAND_e: dict[int, str] = {(VOLTAGE_COLD_0:=0): 'VOLTAGE_COLD_0', (VOLTAGE_COLD_1:=1): 'VOLTAGE_COLD_1', (VOLTAGE_COLD_2:=2): 'VOLTAGE_COLD_2', (VOLTAGE_COLD_3:=3): 'VOLTAGE_COLD_3', (VOLTAGE_COLD_4:=4): 'VOLTAGE_COLD_4', (VOLTAGE_COLD_5:=5): 'VOLTAGE_COLD_5', (VOLTAGE_COLD_6:=6): 'VOLTAGE_COLD_6', (VOLTAGE_COLD_7:=7): 'VOLTAGE_COLD_7', (VOLTAGE_MID_0:=8): 'VOLTAGE_MID_0', (VOLTAGE_MID_1:=9): 'VOLTAGE_MID_1', (VOLTAGE_MID_2:=10): 'VOLTAGE_MID_2', (VOLTAGE_MID_3:=11): 'VOLTAGE_MID_3', (VOLTAGE_MID_4:=12): 'VOLTAGE_MID_4', (VOLTAGE_MID_5:=13): 'VOLTAGE_MID_5', (VOLTAGE_MID_6:=14): 'VOLTAGE_MID_6', (VOLTAGE_MID_7:=15): 'VOLTAGE_MID_7', (VOLTAGE_HOT_0:=16): 'VOLTAGE_HOT_0', (VOLTAGE_HOT_1:=17): 'VOLTAGE_HOT_1', (VOLTAGE_HOT_2:=18): 'VOLTAGE_HOT_2', (VOLTAGE_HOT_3:=19): 'VOLTAGE_HOT_3', (VOLTAGE_HOT_4:=20): 'VOLTAGE_HOT_4', (VOLTAGE_HOT_5:=21): 'VOLTAGE_HOT_5', (VOLTAGE_HOT_6:=22): 'VOLTAGE_HOT_6', (VOLTAGE_HOT_7:=23): 'VOLTAGE_HOT_7', (VOLTAGE_GUARDBAND_COUNT:=24): 'VOLTAGE_GUARDBAND_COUNT'}
|
||||
@c.record
|
||||
class MetricsTableV0_t(c.Struct):
|
||||
SIZE = 2268
|
||||
AccumulationCounter: int
|
||||
MaxSocketTemperature: int
|
||||
MaxVrTemperature: int
|
||||
MaxHbmTemperature: int
|
||||
MaxSocketTemperatureAcc: int
|
||||
MaxVrTemperatureAcc: int
|
||||
MaxHbmTemperatureAcc: int
|
||||
SocketPowerLimit: int
|
||||
MaxSocketPowerLimit: int
|
||||
SocketPower: int
|
||||
Timestamp: int
|
||||
SocketEnergyAcc: int
|
||||
CcdEnergyAcc: int
|
||||
XcdEnergyAcc: int
|
||||
AidEnergyAcc: int
|
||||
HbmEnergyAcc: int
|
||||
CclkFrequencyLimit: int
|
||||
GfxclkFrequencyLimit: int
|
||||
FclkFrequency: int
|
||||
UclkFrequency: int
|
||||
SocclkFrequency: c.Array[ctypes.c_uint32, Literal[4]]
|
||||
VclkFrequency: c.Array[ctypes.c_uint32, Literal[4]]
|
||||
DclkFrequency: c.Array[ctypes.c_uint32, Literal[4]]
|
||||
LclkFrequency: c.Array[ctypes.c_uint32, Literal[4]]
|
||||
GfxclkFrequencyAcc: c.Array[ctypes.c_uint64, Literal[8]]
|
||||
CclkFrequencyAcc: c.Array[ctypes.c_uint64, Literal[96]]
|
||||
MaxCclkFrequency: int
|
||||
MinCclkFrequency: int
|
||||
MaxGfxclkFrequency: int
|
||||
MinGfxclkFrequency: int
|
||||
FclkFrequencyTable: c.Array[ctypes.c_uint32, Literal[4]]
|
||||
UclkFrequencyTable: c.Array[ctypes.c_uint32, Literal[4]]
|
||||
SocclkFrequencyTable: c.Array[ctypes.c_uint32, Literal[4]]
|
||||
VclkFrequencyTable: c.Array[ctypes.c_uint32, Literal[4]]
|
||||
DclkFrequencyTable: c.Array[ctypes.c_uint32, Literal[4]]
|
||||
LclkFrequencyTable: c.Array[ctypes.c_uint32, Literal[4]]
|
||||
MaxLclkDpmRange: int
|
||||
MinLclkDpmRange: int
|
||||
XgmiWidth: int
|
||||
XgmiBitrate: int
|
||||
XgmiReadBandwidthAcc: c.Array[ctypes.c_uint64, Literal[8]]
|
||||
XgmiWriteBandwidthAcc: c.Array[ctypes.c_uint64, Literal[8]]
|
||||
SocketC0Residency: int
|
||||
SocketGfxBusy: int
|
||||
DramBandwidthUtilization: int
|
||||
SocketC0ResidencyAcc: int
|
||||
SocketGfxBusyAcc: int
|
||||
DramBandwidthAcc: int
|
||||
MaxDramBandwidth: int
|
||||
DramBandwidthUtilizationAcc: int
|
||||
PcieBandwidthAcc: c.Array[ctypes.c_uint64, Literal[4]]
|
||||
ProchotResidencyAcc: int
|
||||
PptResidencyAcc: int
|
||||
SocketThmResidencyAcc: int
|
||||
VrThmResidencyAcc: int
|
||||
HbmThmResidencyAcc: int
|
||||
GfxLockXCDMak: int
|
||||
GfxclkFrequency: c.Array[ctypes.c_uint32, Literal[8]]
|
||||
PublicSerialNumber_AID: c.Array[ctypes.c_uint64, Literal[4]]
|
||||
PublicSerialNumber_XCD: c.Array[ctypes.c_uint64, Literal[8]]
|
||||
PublicSerialNumber_CCD: c.Array[ctypes.c_uint64, Literal[12]]
|
||||
XgmiReadDataSizeAcc: c.Array[ctypes.c_uint64, Literal[8]]
|
||||
XgmiWriteDataSizeAcc: c.Array[ctypes.c_uint64, Literal[8]]
|
||||
PcieBandwidth: c.Array[ctypes.c_uint32, Literal[4]]
|
||||
PCIeL0ToRecoveryCountAcc: int
|
||||
PCIenReplayAAcc: int
|
||||
PCIenReplayARolloverCountAcc: int
|
||||
PCIeNAKSentCountAcc: int
|
||||
PCIeNAKReceivedCountAcc: int
|
||||
VcnBusy: c.Array[ctypes.c_uint32, Literal[4]]
|
||||
JpegBusy: c.Array[ctypes.c_uint32, Literal[32]]
|
||||
PCIeLinkSpeed: int
|
||||
PCIeLinkWidth: int
|
||||
GfxBusy: c.Array[ctypes.c_uint32, Literal[8]]
|
||||
GfxBusyAcc: c.Array[ctypes.c_uint64, Literal[8]]
|
||||
PCIeOtherEndRecoveryAcc: int
|
||||
GfxclkBelowHostLimitPptAcc: c.Array[ctypes.c_uint64, Literal[8]]
|
||||
GfxclkBelowHostLimitThmAcc: c.Array[ctypes.c_uint64, Literal[8]]
|
||||
GfxclkBelowHostLimitTotalAcc: c.Array[ctypes.c_uint64, Literal[8]]
|
||||
GfxclkLowUtilizationAcc: c.Array[ctypes.c_uint64, Literal[8]]
|
||||
uint32_t: TypeAlias = ctypes.c_uint32
|
||||
uint64_t: TypeAlias = ctypes.c_uint64
|
||||
MetricsTableV0_t.register_fields([('AccumulationCounter', uint32_t, 0), ('MaxSocketTemperature', uint32_t, 4), ('MaxVrTemperature', uint32_t, 8), ('MaxHbmTemperature', uint32_t, 12), ('MaxSocketTemperatureAcc', uint64_t, 16), ('MaxVrTemperatureAcc', uint64_t, 24), ('MaxHbmTemperatureAcc', uint64_t, 32), ('SocketPowerLimit', uint32_t, 40), ('MaxSocketPowerLimit', uint32_t, 44), ('SocketPower', uint32_t, 48), ('Timestamp', uint64_t, 52), ('SocketEnergyAcc', uint64_t, 60), ('CcdEnergyAcc', uint64_t, 68), ('XcdEnergyAcc', uint64_t, 76), ('AidEnergyAcc', uint64_t, 84), ('HbmEnergyAcc', uint64_t, 92), ('CclkFrequencyLimit', uint32_t, 100), ('GfxclkFrequencyLimit', uint32_t, 104), ('FclkFrequency', uint32_t, 108), ('UclkFrequency', uint32_t, 112), ('SocclkFrequency', c.Array[uint32_t, Literal[4]], 116), ('VclkFrequency', c.Array[uint32_t, Literal[4]], 132), ('DclkFrequency', c.Array[uint32_t, Literal[4]], 148), ('LclkFrequency', c.Array[uint32_t, Literal[4]], 164), ('GfxclkFrequencyAcc', c.Array[uint64_t, Literal[8]], 180), ('CclkFrequencyAcc', c.Array[uint64_t, Literal[96]], 244), ('MaxCclkFrequency', uint32_t, 1012), ('MinCclkFrequency', uint32_t, 1016), ('MaxGfxclkFrequency', uint32_t, 1020), ('MinGfxclkFrequency', uint32_t, 1024), ('FclkFrequencyTable', c.Array[uint32_t, Literal[4]], 1028), ('UclkFrequencyTable', c.Array[uint32_t, Literal[4]], 1044), ('SocclkFrequencyTable', c.Array[uint32_t, Literal[4]], 1060), ('VclkFrequencyTable', c.Array[uint32_t, Literal[4]], 1076), ('DclkFrequencyTable', c.Array[uint32_t, Literal[4]], 1092), ('LclkFrequencyTable', c.Array[uint32_t, Literal[4]], 1108), ('MaxLclkDpmRange', uint32_t, 1124), ('MinLclkDpmRange', uint32_t, 1128), ('XgmiWidth', uint32_t, 1132), ('XgmiBitrate', uint32_t, 1136), ('XgmiReadBandwidthAcc', c.Array[uint64_t, Literal[8]], 1140), ('XgmiWriteBandwidthAcc', c.Array[uint64_t, Literal[8]], 1204), ('SocketC0Residency', uint32_t, 1268), ('SocketGfxBusy', uint32_t, 1272), ('DramBandwidthUtilization', uint32_t, 1276), ('SocketC0ResidencyAcc', uint64_t, 1280), ('SocketGfxBusyAcc', uint64_t, 1288), ('DramBandwidthAcc', uint64_t, 1296), ('MaxDramBandwidth', uint32_t, 1304), ('DramBandwidthUtilizationAcc', uint64_t, 1308), ('PcieBandwidthAcc', c.Array[uint64_t, Literal[4]], 1316), ('ProchotResidencyAcc', uint32_t, 1348), ('PptResidencyAcc', uint32_t, 1352), ('SocketThmResidencyAcc', uint32_t, 1356), ('VrThmResidencyAcc', uint32_t, 1360), ('HbmThmResidencyAcc', uint32_t, 1364), ('GfxLockXCDMak', uint32_t, 1368), ('GfxclkFrequency', c.Array[uint32_t, Literal[8]], 1372), ('PublicSerialNumber_AID', c.Array[uint64_t, Literal[4]], 1404), ('PublicSerialNumber_XCD', c.Array[uint64_t, Literal[8]], 1436), ('PublicSerialNumber_CCD', c.Array[uint64_t, Literal[12]], 1500), ('XgmiReadDataSizeAcc', c.Array[uint64_t, Literal[8]], 1596), ('XgmiWriteDataSizeAcc', c.Array[uint64_t, Literal[8]], 1660), ('PcieBandwidth', c.Array[uint32_t, Literal[4]], 1724), ('PCIeL0ToRecoveryCountAcc', uint32_t, 1740), ('PCIenReplayAAcc', uint32_t, 1744), ('PCIenReplayARolloverCountAcc', uint32_t, 1748), ('PCIeNAKSentCountAcc', uint32_t, 1752), ('PCIeNAKReceivedCountAcc', uint32_t, 1756), ('VcnBusy', c.Array[uint32_t, Literal[4]], 1760), ('JpegBusy', c.Array[uint32_t, Literal[32]], 1776), ('PCIeLinkSpeed', uint32_t, 1904), ('PCIeLinkWidth', uint32_t, 1908), ('GfxBusy', c.Array[uint32_t, Literal[8]], 1912), ('GfxBusyAcc', c.Array[uint64_t, Literal[8]], 1944), ('PCIeOtherEndRecoveryAcc', uint32_t, 2008), ('GfxclkBelowHostLimitPptAcc', c.Array[uint64_t, Literal[8]], 2012), ('GfxclkBelowHostLimitThmAcc', c.Array[uint64_t, Literal[8]], 2076), ('GfxclkBelowHostLimitTotalAcc', c.Array[uint64_t, Literal[8]], 2140), ('GfxclkLowUtilizationAcc', c.Array[uint64_t, Literal[8]], 2204)])
|
||||
@c.record
|
||||
class MetricsTableV1_t(c.Struct):
|
||||
SIZE = 1868
|
||||
AccumulationCounter: int
|
||||
MaxSocketTemperature: int
|
||||
MaxVrTemperature: int
|
||||
MaxHbmTemperature: int
|
||||
MaxSocketTemperatureAcc: int
|
||||
MaxVrTemperatureAcc: int
|
||||
MaxHbmTemperatureAcc: int
|
||||
SocketPowerLimit: int
|
||||
MaxSocketPowerLimit: int
|
||||
SocketPower: int
|
||||
Timestamp: int
|
||||
SocketEnergyAcc: int
|
||||
CcdEnergyAcc: int
|
||||
XcdEnergyAcc: int
|
||||
AidEnergyAcc: int
|
||||
HbmEnergyAcc: int
|
||||
CclkFrequencyLimit: int
|
||||
GfxclkFrequencyLimit: int
|
||||
FclkFrequency: int
|
||||
UclkFrequency: int
|
||||
SocclkFrequency: c.Array[ctypes.c_uint32, Literal[4]]
|
||||
VclkFrequency: c.Array[ctypes.c_uint32, Literal[4]]
|
||||
DclkFrequency: c.Array[ctypes.c_uint32, Literal[4]]
|
||||
LclkFrequency: c.Array[ctypes.c_uint32, Literal[4]]
|
||||
GfxclkFrequencyAcc: c.Array[ctypes.c_uint64, Literal[8]]
|
||||
CclkFrequencyAcc: c.Array[ctypes.c_uint64, Literal[96]]
|
||||
MaxCclkFrequency: int
|
||||
MinCclkFrequency: int
|
||||
MaxGfxclkFrequency: int
|
||||
MinGfxclkFrequency: int
|
||||
FclkFrequencyTable: c.Array[ctypes.c_uint32, Literal[4]]
|
||||
UclkFrequencyTable: c.Array[ctypes.c_uint32, Literal[4]]
|
||||
SocclkFrequencyTable: c.Array[ctypes.c_uint32, Literal[4]]
|
||||
VclkFrequencyTable: c.Array[ctypes.c_uint32, Literal[4]]
|
||||
DclkFrequencyTable: c.Array[ctypes.c_uint32, Literal[4]]
|
||||
LclkFrequencyTable: c.Array[ctypes.c_uint32, Literal[4]]
|
||||
MaxLclkDpmRange: int
|
||||
MinLclkDpmRange: int
|
||||
XgmiWidth: int
|
||||
XgmiBitrate: int
|
||||
XgmiReadBandwidthAcc: c.Array[ctypes.c_uint64, Literal[8]]
|
||||
XgmiWriteBandwidthAcc: c.Array[ctypes.c_uint64, Literal[8]]
|
||||
SocketC0Residency: int
|
||||
SocketGfxBusy: int
|
||||
DramBandwidthUtilization: int
|
||||
SocketC0ResidencyAcc: int
|
||||
SocketGfxBusyAcc: int
|
||||
DramBandwidthAcc: int
|
||||
MaxDramBandwidth: int
|
||||
DramBandwidthUtilizationAcc: int
|
||||
PcieBandwidthAcc: c.Array[ctypes.c_uint64, Literal[4]]
|
||||
ProchotResidencyAcc: int
|
||||
PptResidencyAcc: int
|
||||
SocketThmResidencyAcc: int
|
||||
VrThmResidencyAcc: int
|
||||
HbmThmResidencyAcc: int
|
||||
GfxLockXCDMak: int
|
||||
GfxclkFrequency: c.Array[ctypes.c_uint32, Literal[8]]
|
||||
PublicSerialNumber_AID: c.Array[ctypes.c_uint64, Literal[4]]
|
||||
PublicSerialNumber_XCD: c.Array[ctypes.c_uint64, Literal[8]]
|
||||
PublicSerialNumber_CCD: c.Array[ctypes.c_uint64, Literal[12]]
|
||||
XgmiReadDataSizeAcc: c.Array[ctypes.c_uint64, Literal[8]]
|
||||
XgmiWriteDataSizeAcc: c.Array[ctypes.c_uint64, Literal[8]]
|
||||
VcnBusy: c.Array[ctypes.c_uint32, Literal[4]]
|
||||
JpegBusy: c.Array[ctypes.c_uint32, Literal[32]]
|
||||
MetricsTableV1_t.register_fields([('AccumulationCounter', uint32_t, 0), ('MaxSocketTemperature', uint32_t, 4), ('MaxVrTemperature', uint32_t, 8), ('MaxHbmTemperature', uint32_t, 12), ('MaxSocketTemperatureAcc', uint64_t, 16), ('MaxVrTemperatureAcc', uint64_t, 24), ('MaxHbmTemperatureAcc', uint64_t, 32), ('SocketPowerLimit', uint32_t, 40), ('MaxSocketPowerLimit', uint32_t, 44), ('SocketPower', uint32_t, 48), ('Timestamp', uint64_t, 52), ('SocketEnergyAcc', uint64_t, 60), ('CcdEnergyAcc', uint64_t, 68), ('XcdEnergyAcc', uint64_t, 76), ('AidEnergyAcc', uint64_t, 84), ('HbmEnergyAcc', uint64_t, 92), ('CclkFrequencyLimit', uint32_t, 100), ('GfxclkFrequencyLimit', uint32_t, 104), ('FclkFrequency', uint32_t, 108), ('UclkFrequency', uint32_t, 112), ('SocclkFrequency', c.Array[uint32_t, Literal[4]], 116), ('VclkFrequency', c.Array[uint32_t, Literal[4]], 132), ('DclkFrequency', c.Array[uint32_t, Literal[4]], 148), ('LclkFrequency', c.Array[uint32_t, Literal[4]], 164), ('GfxclkFrequencyAcc', c.Array[uint64_t, Literal[8]], 180), ('CclkFrequencyAcc', c.Array[uint64_t, Literal[96]], 244), ('MaxCclkFrequency', uint32_t, 1012), ('MinCclkFrequency', uint32_t, 1016), ('MaxGfxclkFrequency', uint32_t, 1020), ('MinGfxclkFrequency', uint32_t, 1024), ('FclkFrequencyTable', c.Array[uint32_t, Literal[4]], 1028), ('UclkFrequencyTable', c.Array[uint32_t, Literal[4]], 1044), ('SocclkFrequencyTable', c.Array[uint32_t, Literal[4]], 1060), ('VclkFrequencyTable', c.Array[uint32_t, Literal[4]], 1076), ('DclkFrequencyTable', c.Array[uint32_t, Literal[4]], 1092), ('LclkFrequencyTable', c.Array[uint32_t, Literal[4]], 1108), ('MaxLclkDpmRange', uint32_t, 1124), ('MinLclkDpmRange', uint32_t, 1128), ('XgmiWidth', uint32_t, 1132), ('XgmiBitrate', uint32_t, 1136), ('XgmiReadBandwidthAcc', c.Array[uint64_t, Literal[8]], 1140), ('XgmiWriteBandwidthAcc', c.Array[uint64_t, Literal[8]], 1204), ('SocketC0Residency', uint32_t, 1268), ('SocketGfxBusy', uint32_t, 1272), ('DramBandwidthUtilization', uint32_t, 1276), ('SocketC0ResidencyAcc', uint64_t, 1280), ('SocketGfxBusyAcc', uint64_t, 1288), ('DramBandwidthAcc', uint64_t, 1296), ('MaxDramBandwidth', uint32_t, 1304), ('DramBandwidthUtilizationAcc', uint64_t, 1308), ('PcieBandwidthAcc', c.Array[uint64_t, Literal[4]], 1316), ('ProchotResidencyAcc', uint32_t, 1348), ('PptResidencyAcc', uint32_t, 1352), ('SocketThmResidencyAcc', uint32_t, 1356), ('VrThmResidencyAcc', uint32_t, 1360), ('HbmThmResidencyAcc', uint32_t, 1364), ('GfxLockXCDMak', uint32_t, 1368), ('GfxclkFrequency', c.Array[uint32_t, Literal[8]], 1372), ('PublicSerialNumber_AID', c.Array[uint64_t, Literal[4]], 1404), ('PublicSerialNumber_XCD', c.Array[uint64_t, Literal[8]], 1436), ('PublicSerialNumber_CCD', c.Array[uint64_t, Literal[12]], 1500), ('XgmiReadDataSizeAcc', c.Array[uint64_t, Literal[8]], 1596), ('XgmiWriteDataSizeAcc', c.Array[uint64_t, Literal[8]], 1660), ('VcnBusy', c.Array[uint32_t, Literal[4]], 1724), ('JpegBusy', c.Array[uint32_t, Literal[32]], 1740)])
|
||||
@c.record
|
||||
class MetricsTableV2_t(c.Struct):
|
||||
SIZE = 1200
|
||||
AccumulationCounter: int
|
||||
MaxSocketTemperature: int
|
||||
MaxVrTemperature: int
|
||||
MaxHbmTemperature: int
|
||||
MaxSocketTemperatureAcc: int
|
||||
MaxVrTemperatureAcc: int
|
||||
MaxHbmTemperatureAcc: int
|
||||
SocketPowerLimit: int
|
||||
MaxSocketPowerLimit: int
|
||||
SocketPower: int
|
||||
Timestamp: int
|
||||
SocketEnergyAcc: int
|
||||
CcdEnergyAcc: int
|
||||
XcdEnergyAcc: int
|
||||
AidEnergyAcc: int
|
||||
HbmEnergyAcc: int
|
||||
GfxclkFrequencyLimit: int
|
||||
FclkFrequency: int
|
||||
UclkFrequency: int
|
||||
SocclkFrequency: c.Array[ctypes.c_uint32, Literal[4]]
|
||||
VclkFrequency: c.Array[ctypes.c_uint32, Literal[4]]
|
||||
DclkFrequency: c.Array[ctypes.c_uint32, Literal[4]]
|
||||
LclkFrequency: c.Array[ctypes.c_uint32, Literal[4]]
|
||||
GfxclkFrequencyAcc: c.Array[ctypes.c_uint64, Literal[8]]
|
||||
MaxGfxclkFrequency: int
|
||||
MinGfxclkFrequency: int
|
||||
FclkFrequencyTable: c.Array[ctypes.c_uint32, Literal[4]]
|
||||
UclkFrequencyTable: c.Array[ctypes.c_uint32, Literal[4]]
|
||||
SocclkFrequencyTable: c.Array[ctypes.c_uint32, Literal[4]]
|
||||
VclkFrequencyTable: c.Array[ctypes.c_uint32, Literal[4]]
|
||||
DclkFrequencyTable: c.Array[ctypes.c_uint32, Literal[4]]
|
||||
LclkFrequencyTable: c.Array[ctypes.c_uint32, Literal[4]]
|
||||
MaxLclkDpmRange: int
|
||||
MinLclkDpmRange: int
|
||||
XgmiWidth: int
|
||||
XgmiBitrate: int
|
||||
XgmiReadBandwidthAcc: c.Array[ctypes.c_uint64, Literal[8]]
|
||||
XgmiWriteBandwidthAcc: c.Array[ctypes.c_uint64, Literal[8]]
|
||||
SocketGfxBusy: int
|
||||
DramBandwidthUtilization: int
|
||||
SocketC0ResidencyAcc: int
|
||||
SocketGfxBusyAcc: int
|
||||
DramBandwidthAcc: int
|
||||
MaxDramBandwidth: int
|
||||
DramBandwidthUtilizationAcc: int
|
||||
PcieBandwidthAcc: c.Array[ctypes.c_uint64, Literal[4]]
|
||||
ProchotResidencyAcc: int
|
||||
PptResidencyAcc: int
|
||||
SocketThmResidencyAcc: int
|
||||
VrThmResidencyAcc: int
|
||||
HbmThmResidencyAcc: int
|
||||
GfxLockXCDMak: int
|
||||
GfxclkFrequency: c.Array[ctypes.c_uint32, Literal[8]]
|
||||
PublicSerialNumber_AID: c.Array[ctypes.c_uint64, Literal[4]]
|
||||
PublicSerialNumber_XCD: c.Array[ctypes.c_uint64, Literal[8]]
|
||||
XgmiReadDataSizeAcc: c.Array[ctypes.c_uint64, Literal[8]]
|
||||
XgmiWriteDataSizeAcc: c.Array[ctypes.c_uint64, Literal[8]]
|
||||
PcieBandwidth: c.Array[ctypes.c_uint32, Literal[4]]
|
||||
PCIeL0ToRecoveryCountAcc: int
|
||||
PCIenReplayAAcc: int
|
||||
PCIenReplayARolloverCountAcc: int
|
||||
PCIeNAKSentCountAcc: int
|
||||
PCIeNAKReceivedCountAcc: int
|
||||
VcnBusy: c.Array[ctypes.c_uint32, Literal[4]]
|
||||
JpegBusy: c.Array[ctypes.c_uint32, Literal[32]]
|
||||
PCIeLinkSpeed: int
|
||||
PCIeLinkWidth: int
|
||||
GfxBusy: c.Array[ctypes.c_uint32, Literal[8]]
|
||||
GfxBusyAcc: c.Array[ctypes.c_uint64, Literal[8]]
|
||||
PCIeOtherEndRecoveryAcc: int
|
||||
GfxclkBelowHostLimitAcc: c.Array[ctypes.c_uint64, Literal[8]]
|
||||
MetricsTableV2_t.register_fields([('AccumulationCounter', uint64_t, 0), ('MaxSocketTemperature', uint32_t, 8), ('MaxVrTemperature', uint32_t, 12), ('MaxHbmTemperature', uint32_t, 16), ('MaxSocketTemperatureAcc', uint64_t, 20), ('MaxVrTemperatureAcc', uint64_t, 28), ('MaxHbmTemperatureAcc', uint64_t, 36), ('SocketPowerLimit', uint32_t, 44), ('MaxSocketPowerLimit', uint32_t, 48), ('SocketPower', uint32_t, 52), ('Timestamp', uint64_t, 56), ('SocketEnergyAcc', uint64_t, 64), ('CcdEnergyAcc', uint64_t, 72), ('XcdEnergyAcc', uint64_t, 80), ('AidEnergyAcc', uint64_t, 88), ('HbmEnergyAcc', uint64_t, 96), ('GfxclkFrequencyLimit', uint32_t, 104), ('FclkFrequency', uint32_t, 108), ('UclkFrequency', uint32_t, 112), ('SocclkFrequency', c.Array[uint32_t, Literal[4]], 116), ('VclkFrequency', c.Array[uint32_t, Literal[4]], 132), ('DclkFrequency', c.Array[uint32_t, Literal[4]], 148), ('LclkFrequency', c.Array[uint32_t, Literal[4]], 164), ('GfxclkFrequencyAcc', c.Array[uint64_t, Literal[8]], 180), ('MaxGfxclkFrequency', uint32_t, 244), ('MinGfxclkFrequency', uint32_t, 248), ('FclkFrequencyTable', c.Array[uint32_t, Literal[4]], 252), ('UclkFrequencyTable', c.Array[uint32_t, Literal[4]], 268), ('SocclkFrequencyTable', c.Array[uint32_t, Literal[4]], 284), ('VclkFrequencyTable', c.Array[uint32_t, Literal[4]], 300), ('DclkFrequencyTable', c.Array[uint32_t, Literal[4]], 316), ('LclkFrequencyTable', c.Array[uint32_t, Literal[4]], 332), ('MaxLclkDpmRange', uint32_t, 348), ('MinLclkDpmRange', uint32_t, 352), ('XgmiWidth', uint32_t, 356), ('XgmiBitrate', uint32_t, 360), ('XgmiReadBandwidthAcc', c.Array[uint64_t, Literal[8]], 364), ('XgmiWriteBandwidthAcc', c.Array[uint64_t, Literal[8]], 428), ('SocketGfxBusy', uint32_t, 492), ('DramBandwidthUtilization', uint32_t, 496), ('SocketC0ResidencyAcc', uint64_t, 500), ('SocketGfxBusyAcc', uint64_t, 508), ('DramBandwidthAcc', uint64_t, 516), ('MaxDramBandwidth', uint32_t, 524), ('DramBandwidthUtilizationAcc', uint64_t, 528), ('PcieBandwidthAcc', c.Array[uint64_t, Literal[4]], 536), ('ProchotResidencyAcc', uint32_t, 568), ('PptResidencyAcc', uint32_t, 572), ('SocketThmResidencyAcc', uint32_t, 576), ('VrThmResidencyAcc', uint32_t, 580), ('HbmThmResidencyAcc', uint32_t, 584), ('GfxLockXCDMak', uint32_t, 588), ('GfxclkFrequency', c.Array[uint32_t, Literal[8]], 592), ('PublicSerialNumber_AID', c.Array[uint64_t, Literal[4]], 624), ('PublicSerialNumber_XCD', c.Array[uint64_t, Literal[8]], 656), ('XgmiReadDataSizeAcc', c.Array[uint64_t, Literal[8]], 720), ('XgmiWriteDataSizeAcc', c.Array[uint64_t, Literal[8]], 784), ('PcieBandwidth', c.Array[uint32_t, Literal[4]], 848), ('PCIeL0ToRecoveryCountAcc', uint32_t, 864), ('PCIenReplayAAcc', uint32_t, 868), ('PCIenReplayARolloverCountAcc', uint32_t, 872), ('PCIeNAKSentCountAcc', uint32_t, 876), ('PCIeNAKReceivedCountAcc', uint32_t, 880), ('VcnBusy', c.Array[uint32_t, Literal[4]], 884), ('JpegBusy', c.Array[uint32_t, Literal[32]], 900), ('PCIeLinkSpeed', uint32_t, 1028), ('PCIeLinkWidth', uint32_t, 1032), ('GfxBusy', c.Array[uint32_t, Literal[8]], 1036), ('GfxBusyAcc', c.Array[uint64_t, Literal[8]], 1068), ('PCIeOtherEndRecoveryAcc', uint32_t, 1132), ('GfxclkBelowHostLimitAcc', c.Array[uint64_t, Literal[8]], 1136)])
|
||||
@c.record
|
||||
class VfMetricsTable_t(c.Struct):
|
||||
SIZE = 32
|
||||
AccumulationCounter: int
|
||||
InstGfxclk_TargFreq: int
|
||||
AccGfxclk_TargFreq: int
|
||||
AccGfxRsmuDpm_Busy: int
|
||||
AccGfxclkBelowHostLimit: int
|
||||
VfMetricsTable_t.register_fields([('AccumulationCounter', uint32_t, 0), ('InstGfxclk_TargFreq', uint32_t, 4), ('AccGfxclk_TargFreq', uint64_t, 8), ('AccGfxRsmuDpm_Busy', uint64_t, 16), ('AccGfxclkBelowHostLimit', uint64_t, 24)])
|
||||
@c.record
|
||||
class StaticMetricsTable_t(c.Struct):
|
||||
SIZE = 12
|
||||
InputTelemetryVoltageInmV: int
|
||||
pldmVersion: c.Array[ctypes.c_uint32, Literal[2]]
|
||||
StaticMetricsTable_t.register_fields([('InputTelemetryVoltageInmV', uint32_t, 0), ('pldmVersion', c.Array[uint32_t, Literal[2]], 4)])
|
||||
I2cControllerPort_e: dict[int, str] = {(I2C_CONTROLLER_PORT_0:=0): 'I2C_CONTROLLER_PORT_0', (I2C_CONTROLLER_PORT_1:=1): 'I2C_CONTROLLER_PORT_1', (I2C_CONTROLLER_PORT_COUNT:=2): 'I2C_CONTROLLER_PORT_COUNT'}
|
||||
I2cSpeed_e: dict[int, str] = {(UNSUPPORTED_1:=0): 'UNSUPPORTED_1', (I2C_SPEED_STANDARD_100K:=1): 'I2C_SPEED_STANDARD_100K', (I2C_SPEED_FAST_400K:=2): 'I2C_SPEED_FAST_400K', (I2C_SPEED_FAST_PLUS_1M:=3): 'I2C_SPEED_FAST_PLUS_1M', (UNSUPPORTED_2:=4): 'UNSUPPORTED_2', (UNSUPPORTED_3:=5): 'UNSUPPORTED_3', (I2C_SPEED_COUNT:=6): 'I2C_SPEED_COUNT'}
|
||||
I2cCmdType_e: dict[int, str] = {(I2C_CMD_READ:=0): 'I2C_CMD_READ', (I2C_CMD_WRITE:=1): 'I2C_CMD_WRITE', (I2C_CMD_COUNT:=2): 'I2C_CMD_COUNT'}
|
||||
ERR_CODE_e: dict[int, str] = {(CODE_DAGB0:=0): 'CODE_DAGB0', (CODE_EA0:=5): 'CODE_EA0', (CODE_UTCL2_ROUTER:=10): 'CODE_UTCL2_ROUTER', (CODE_VML2:=11): 'CODE_VML2', (CODE_VML2_WALKER:=12): 'CODE_VML2_WALKER', (CODE_MMCANE:=13): 'CODE_MMCANE', (CODE_VIDD:=14): 'CODE_VIDD', (CODE_VIDV:=15): 'CODE_VIDV', (CODE_JPEG0S:=16): 'CODE_JPEG0S', (CODE_JPEG0D:=17): 'CODE_JPEG0D', (CODE_JPEG1S:=18): 'CODE_JPEG1S', (CODE_JPEG1D:=19): 'CODE_JPEG1D', (CODE_JPEG2S:=20): 'CODE_JPEG2S', (CODE_JPEG2D:=21): 'CODE_JPEG2D', (CODE_JPEG3S:=22): 'CODE_JPEG3S', (CODE_JPEG3D:=23): 'CODE_JPEG3D', (CODE_JPEG4S:=24): 'CODE_JPEG4S', (CODE_JPEG4D:=25): 'CODE_JPEG4D', (CODE_JPEG5S:=26): 'CODE_JPEG5S', (CODE_JPEG5D:=27): 'CODE_JPEG5D', (CODE_JPEG6S:=28): 'CODE_JPEG6S', (CODE_JPEG6D:=29): 'CODE_JPEG6D', (CODE_JPEG7S:=30): 'CODE_JPEG7S', (CODE_JPEG7D:=31): 'CODE_JPEG7D', (CODE_MMSCHD:=32): 'CODE_MMSCHD', (CODE_SDMA0:=33): 'CODE_SDMA0', (CODE_SDMA1:=34): 'CODE_SDMA1', (CODE_SDMA2:=35): 'CODE_SDMA2', (CODE_SDMA3:=36): 'CODE_SDMA3', (CODE_HDP:=37): 'CODE_HDP', (CODE_ATHUB:=38): 'CODE_ATHUB', (CODE_IH:=39): 'CODE_IH', (CODE_XHUB_POISON:=40): 'CODE_XHUB_POISON', (CODE_SMN_SLVERR:=40): 'CODE_SMN_SLVERR', (CODE_WDT:=41): 'CODE_WDT', (CODE_UNKNOWN:=42): 'CODE_UNKNOWN', (CODE_COUNT:=43): 'CODE_COUNT'}
|
||||
GC_ERROR_CODE_e: dict[int, str] = {(SH_FED_CODE:=0): 'SH_FED_CODE', (GCEA_CODE:=1): 'GCEA_CODE', (SQ_CODE:=2): 'SQ_CODE', (LDS_CODE:=3): 'LDS_CODE', (GDS_CODE:=4): 'GDS_CODE', (SP0_CODE:=5): 'SP0_CODE', (SP1_CODE:=6): 'SP1_CODE', (TCC_CODE:=7): 'TCC_CODE', (TCA_CODE:=8): 'TCA_CODE', (TCX_CODE:=9): 'TCX_CODE', (CPC_CODE:=10): 'CPC_CODE', (CPF_CODE:=11): 'CPF_CODE', (CPG_CODE:=12): 'CPG_CODE', (SPI_CODE:=13): 'SPI_CODE', (RLC_CODE:=14): 'RLC_CODE', (SQC_CODE:=15): 'SQC_CODE', (TA_CODE:=16): 'TA_CODE', (TD_CODE:=17): 'TD_CODE', (TCP_CODE:=18): 'TCP_CODE', (TCI_CODE:=19): 'TCI_CODE', (GC_ROUTER_CODE:=20): 'GC_ROUTER_CODE', (VML2_CODE:=21): 'VML2_CODE', (VML2_WALKER_CODE:=22): 'VML2_WALKER_CODE', (ATCL2_CODE:=23): 'ATCL2_CODE', (GC_CANE_CODE:=24): 'GC_CANE_CODE', (MP5_CODE_SMN_SLVERR:=40): 'MP5_CODE_SMN_SLVERR', (MP5_CODE_UNKNOWN:=42): 'MP5_CODE_UNKNOWN'}
|
||||
@c.record
|
||||
class SwI2cCmd_t(c.Struct):
|
||||
SIZE = 2
|
||||
ReadWriteData: int
|
||||
CmdConfig: int
|
||||
uint8_t: TypeAlias = ctypes.c_ubyte
|
||||
SwI2cCmd_t.register_fields([('ReadWriteData', uint8_t, 0), ('CmdConfig', uint8_t, 1)])
|
||||
@c.record
|
||||
class SwI2cRequest_t(c.Struct):
|
||||
SIZE = 52
|
||||
I2CcontrollerPort: int
|
||||
I2CSpeed: int
|
||||
SlaveAddress: int
|
||||
NumCmds: int
|
||||
SwI2cCmds: c.Array[SwI2cCmd_t, Literal[24]]
|
||||
SwI2cRequest_t.register_fields([('I2CcontrollerPort', uint8_t, 0), ('I2CSpeed', uint8_t, 1), ('SlaveAddress', uint8_t, 2), ('NumCmds', uint8_t, 3), ('SwI2cCmds', c.Array[SwI2cCmd_t, Literal[24]], 4)])
|
||||
@c.record
|
||||
class SwI2cRequestExternal_t(c.Struct):
|
||||
SIZE = 116
|
||||
SwI2cRequest: SwI2cRequest_t
|
||||
Spare: c.Array[ctypes.c_uint32, Literal[8]]
|
||||
MmHubPadding: c.Array[ctypes.c_uint32, Literal[8]]
|
||||
SwI2cRequestExternal_t.register_fields([('SwI2cRequest', SwI2cRequest_t, 0), ('Spare', c.Array[uint32_t, Literal[8]], 52), ('MmHubPadding', c.Array[uint32_t, Literal[8]], 84)])
|
||||
PPCLK_e: dict[int, str] = {(PPCLK_VCLK:=0): 'PPCLK_VCLK', (PPCLK_DCLK:=1): 'PPCLK_DCLK', (PPCLK_SOCCLK:=2): 'PPCLK_SOCCLK', (PPCLK_UCLK:=3): 'PPCLK_UCLK', (PPCLK_FCLK:=4): 'PPCLK_FCLK', (PPCLK_LCLK:=5): 'PPCLK_LCLK', (PPCLK_COUNT:=6): 'PPCLK_COUNT'}
|
||||
GpioIntPolarity_e: dict[int, str] = {(GPIO_INT_POLARITY_ACTIVE_LOW:=0): 'GPIO_INT_POLARITY_ACTIVE_LOW', (GPIO_INT_POLARITY_ACTIVE_HIGH:=1): 'GPIO_INT_POLARITY_ACTIVE_HIGH'}
|
||||
UCLK_DPM_MODE_e: dict[int, str] = {(UCLK_DPM_MODE_BANDWIDTH:=0): 'UCLK_DPM_MODE_BANDWIDTH', (UCLK_DPM_MODE_LATENCY:=1): 'UCLK_DPM_MODE_LATENCY'}
|
||||
@c.record
|
||||
class AvfsDebugTableAid_t(c.Struct):
|
||||
SIZE = 360
|
||||
avgPsmCount: c.Array[ctypes.c_uint16, Literal[30]]
|
||||
minPsmCount: c.Array[ctypes.c_uint16, Literal[30]]
|
||||
avgPsmVoltage: c.Array[ctypes.c_float, Literal[30]]
|
||||
minPsmVoltage: c.Array[ctypes.c_float, Literal[30]]
|
||||
uint16_t: TypeAlias = ctypes.c_uint16
|
||||
AvfsDebugTableAid_t.register_fields([('avgPsmCount', c.Array[uint16_t, Literal[30]], 0), ('minPsmCount', c.Array[uint16_t, Literal[30]], 60), ('avgPsmVoltage', c.Array[ctypes.c_float, Literal[30]], 120), ('minPsmVoltage', c.Array[ctypes.c_float, Literal[30]], 240)])
|
||||
@c.record
|
||||
class AvfsDebugTableXcd_t(c.Struct):
|
||||
SIZE = 360
|
||||
avgPsmCount: c.Array[ctypes.c_uint16, Literal[30]]
|
||||
minPsmCount: c.Array[ctypes.c_uint16, Literal[30]]
|
||||
avgPsmVoltage: c.Array[ctypes.c_float, Literal[30]]
|
||||
minPsmVoltage: c.Array[ctypes.c_float, Literal[30]]
|
||||
AvfsDebugTableXcd_t.register_fields([('avgPsmCount', c.Array[uint16_t, Literal[30]], 0), ('minPsmCount', c.Array[uint16_t, Literal[30]], 60), ('avgPsmVoltage', c.Array[ctypes.c_float, Literal[30]], 120), ('minPsmVoltage', c.Array[ctypes.c_float, Literal[30]], 240)])
|
||||
@c.record
|
||||
class struct_smu_hw_power_state(c.Struct):
|
||||
SIZE = 4
|
||||
magic: int
|
||||
struct_smu_hw_power_state.register_fields([('magic', ctypes.c_uint32, 0)])
|
||||
class struct_smu_power_state(c.Struct): pass
|
||||
enum_smu_state_ui_label: dict[int, str] = {(SMU_STATE_UI_LABEL_NONE:=0): 'SMU_STATE_UI_LABEL_NONE', (SMU_STATE_UI_LABEL_BATTERY:=1): 'SMU_STATE_UI_LABEL_BATTERY', (SMU_STATE_UI_TABEL_MIDDLE_LOW:=2): 'SMU_STATE_UI_TABEL_MIDDLE_LOW', (SMU_STATE_UI_LABEL_BALLANCED:=3): 'SMU_STATE_UI_LABEL_BALLANCED', (SMU_STATE_UI_LABEL_MIDDLE_HIGHT:=4): 'SMU_STATE_UI_LABEL_MIDDLE_HIGHT', (SMU_STATE_UI_LABEL_PERFORMANCE:=5): 'SMU_STATE_UI_LABEL_PERFORMANCE', (SMU_STATE_UI_LABEL_BACO:=6): 'SMU_STATE_UI_LABEL_BACO'}
|
||||
enum_smu_state_classification_flag: dict[int, str] = {(SMU_STATE_CLASSIFICATION_FLAG_BOOT:=1): 'SMU_STATE_CLASSIFICATION_FLAG_BOOT', (SMU_STATE_CLASSIFICATION_FLAG_THERMAL:=2): 'SMU_STATE_CLASSIFICATION_FLAG_THERMAL', (SMU_STATE_CLASSIFICATIN_FLAG_LIMITED_POWER_SOURCE:=4): 'SMU_STATE_CLASSIFICATIN_FLAG_LIMITED_POWER_SOURCE', (SMU_STATE_CLASSIFICATION_FLAG_RESET:=8): 'SMU_STATE_CLASSIFICATION_FLAG_RESET', (SMU_STATE_CLASSIFICATION_FLAG_FORCED:=16): 'SMU_STATE_CLASSIFICATION_FLAG_FORCED', (SMU_STATE_CLASSIFICATION_FLAG_USER_3D_PERFORMANCE:=32): 'SMU_STATE_CLASSIFICATION_FLAG_USER_3D_PERFORMANCE', (SMU_STATE_CLASSIFICATION_FLAG_USER_2D_PERFORMANCE:=64): 'SMU_STATE_CLASSIFICATION_FLAG_USER_2D_PERFORMANCE', (SMU_STATE_CLASSIFICATION_FLAG_3D_PERFORMANCE:=128): 'SMU_STATE_CLASSIFICATION_FLAG_3D_PERFORMANCE', (SMU_STATE_CLASSIFICATION_FLAG_AC_OVERDIRVER_TEMPLATE:=256): 'SMU_STATE_CLASSIFICATION_FLAG_AC_OVERDIRVER_TEMPLATE', (SMU_STATE_CLASSIFICATION_FLAG_UVD:=512): 'SMU_STATE_CLASSIFICATION_FLAG_UVD', (SMU_STATE_CLASSIFICATION_FLAG_3D_PERFORMANCE_LOW:=1024): 'SMU_STATE_CLASSIFICATION_FLAG_3D_PERFORMANCE_LOW', (SMU_STATE_CLASSIFICATION_FLAG_ACPI:=2048): 'SMU_STATE_CLASSIFICATION_FLAG_ACPI', (SMU_STATE_CLASSIFICATION_FLAG_HD2:=4096): 'SMU_STATE_CLASSIFICATION_FLAG_HD2', (SMU_STATE_CLASSIFICATION_FLAG_UVD_HD:=8192): 'SMU_STATE_CLASSIFICATION_FLAG_UVD_HD', (SMU_STATE_CLASSIFICATION_FLAG_UVD_SD:=16384): 'SMU_STATE_CLASSIFICATION_FLAG_UVD_SD', (SMU_STATE_CLASSIFICATION_FLAG_USER_DC_PERFORMANCE:=32768): 'SMU_STATE_CLASSIFICATION_FLAG_USER_DC_PERFORMANCE', (SMU_STATE_CLASSIFICATION_FLAG_DC_OVERDIRVER_TEMPLATE:=65536): 'SMU_STATE_CLASSIFICATION_FLAG_DC_OVERDIRVER_TEMPLATE', (SMU_STATE_CLASSIFICATION_FLAG_BACO:=131072): 'SMU_STATE_CLASSIFICATION_FLAG_BACO', (SMU_STATE_CLASSIFICATIN_FLAG_LIMITED_POWER_SOURCE2:=262144): 'SMU_STATE_CLASSIFICATIN_FLAG_LIMITED_POWER_SOURCE2', (SMU_STATE_CLASSIFICATION_FLAG_ULV:=524288): 'SMU_STATE_CLASSIFICATION_FLAG_ULV', (SMU_STATE_CLASSIFICATION_FLAG_UVD_MVC:=1048576): 'SMU_STATE_CLASSIFICATION_FLAG_UVD_MVC'}
|
||||
@c.record
|
||||
class struct_smu_state_classification_block(c.Struct):
|
||||
SIZE = 16
|
||||
ui_label: int
|
||||
flags: int
|
||||
bios_index: int
|
||||
temporary_state: bool
|
||||
to_be_deleted: bool
|
||||
struct_smu_state_classification_block.register_fields([('ui_label', ctypes.c_uint32, 0), ('flags', ctypes.c_uint32, 4), ('bios_index', ctypes.c_int32, 8), ('temporary_state', ctypes.c_bool, 12), ('to_be_deleted', ctypes.c_bool, 13)])
|
||||
@c.record
|
||||
class struct_smu_state_pcie_block(c.Struct):
|
||||
SIZE = 4
|
||||
lanes: int
|
||||
struct_smu_state_pcie_block.register_fields([('lanes', ctypes.c_uint32, 0)])
|
||||
enum_smu_refreshrate_source: dict[int, str] = {(SMU_REFRESHRATE_SOURCE_EDID:=0): 'SMU_REFRESHRATE_SOURCE_EDID', (SMU_REFRESHRATE_SOURCE_EXPLICIT:=1): 'SMU_REFRESHRATE_SOURCE_EXPLICIT'}
|
||||
@c.record
|
||||
class struct_smu_state_display_block(c.Struct):
|
||||
SIZE = 20
|
||||
disable_frame_modulation: bool
|
||||
limit_refreshrate: bool
|
||||
refreshrate_source: int
|
||||
explicit_refreshrate: int
|
||||
edid_refreshrate_index: int
|
||||
enable_vari_bright: bool
|
||||
struct_smu_state_display_block.register_fields([('disable_frame_modulation', ctypes.c_bool, 0), ('limit_refreshrate', ctypes.c_bool, 1), ('refreshrate_source', ctypes.c_uint32, 4), ('explicit_refreshrate', ctypes.c_int32, 8), ('edid_refreshrate_index', ctypes.c_int32, 12), ('enable_vari_bright', ctypes.c_bool, 16)])
|
||||
@c.record
|
||||
class struct_smu_state_memory_block(c.Struct):
|
||||
SIZE = 5
|
||||
dll_off: bool
|
||||
m3arb: int
|
||||
unused: c.Array[ctypes.c_ubyte, Literal[3]]
|
||||
struct_smu_state_memory_block.register_fields([('dll_off', ctypes.c_bool, 0), ('m3arb', uint8_t, 1), ('unused', c.Array[uint8_t, Literal[3]], 2)])
|
||||
@c.record
|
||||
class struct_smu_state_software_algorithm_block(c.Struct):
|
||||
SIZE = 2
|
||||
disable_load_balancing: bool
|
||||
enable_sleep_for_timestamps: bool
|
||||
struct_smu_state_software_algorithm_block.register_fields([('disable_load_balancing', ctypes.c_bool, 0), ('enable_sleep_for_timestamps', ctypes.c_bool, 1)])
|
||||
@c.record
|
||||
class struct_smu_temperature_range(c.Struct):
|
||||
SIZE = 44
|
||||
min: int
|
||||
max: int
|
||||
edge_emergency_max: int
|
||||
hotspot_min: int
|
||||
hotspot_crit_max: int
|
||||
hotspot_emergency_max: int
|
||||
mem_min: int
|
||||
mem_crit_max: int
|
||||
mem_emergency_max: int
|
||||
software_shutdown_temp: int
|
||||
software_shutdown_temp_offset: int
|
||||
struct_smu_temperature_range.register_fields([('min', ctypes.c_int32, 0), ('max', ctypes.c_int32, 4), ('edge_emergency_max', ctypes.c_int32, 8), ('hotspot_min', ctypes.c_int32, 12), ('hotspot_crit_max', ctypes.c_int32, 16), ('hotspot_emergency_max', ctypes.c_int32, 20), ('mem_min', ctypes.c_int32, 24), ('mem_crit_max', ctypes.c_int32, 28), ('mem_emergency_max', ctypes.c_int32, 32), ('software_shutdown_temp', ctypes.c_int32, 36), ('software_shutdown_temp_offset', ctypes.c_int32, 40)])
|
||||
@c.record
|
||||
class struct_smu_state_validation_block(c.Struct):
|
||||
SIZE = 3
|
||||
single_display_only: bool
|
||||
disallow_on_dc: bool
|
||||
supported_power_levels: int
|
||||
struct_smu_state_validation_block.register_fields([('single_display_only', ctypes.c_bool, 0), ('disallow_on_dc', ctypes.c_bool, 1), ('supported_power_levels', uint8_t, 2)])
|
||||
@c.record
|
||||
class struct_smu_uvd_clocks(c.Struct):
|
||||
SIZE = 8
|
||||
vclk: int
|
||||
dclk: int
|
||||
struct_smu_uvd_clocks.register_fields([('vclk', uint32_t, 0), ('dclk', uint32_t, 4)])
|
||||
enum_smu_power_src_type: dict[int, str] = {(SMU_POWER_SOURCE_AC:=0): 'SMU_POWER_SOURCE_AC', (SMU_POWER_SOURCE_DC:=1): 'SMU_POWER_SOURCE_DC', (SMU_POWER_SOURCE_COUNT:=2): 'SMU_POWER_SOURCE_COUNT'}
|
||||
enum_smu_ppt_limit_type: dict[int, str] = {(SMU_DEFAULT_PPT_LIMIT:=0): 'SMU_DEFAULT_PPT_LIMIT', (SMU_FAST_PPT_LIMIT:=1): 'SMU_FAST_PPT_LIMIT'}
|
||||
enum_smu_ppt_limit_level: dict[int, str] = {(SMU_PPT_LIMIT_MIN:=-1): 'SMU_PPT_LIMIT_MIN', (SMU_PPT_LIMIT_CURRENT:=0): 'SMU_PPT_LIMIT_CURRENT', (SMU_PPT_LIMIT_DEFAULT:=1): 'SMU_PPT_LIMIT_DEFAULT', (SMU_PPT_LIMIT_MAX:=2): 'SMU_PPT_LIMIT_MAX'}
|
||||
enum_smu_memory_pool_size: dict[int, str] = {(SMU_MEMORY_POOL_SIZE_ZERO:=0): 'SMU_MEMORY_POOL_SIZE_ZERO', (SMU_MEMORY_POOL_SIZE_256_MB:=268435456): 'SMU_MEMORY_POOL_SIZE_256_MB', (SMU_MEMORY_POOL_SIZE_512_MB:=536870912): 'SMU_MEMORY_POOL_SIZE_512_MB', (SMU_MEMORY_POOL_SIZE_1_GB:=1073741824): 'SMU_MEMORY_POOL_SIZE_1_GB', (SMU_MEMORY_POOL_SIZE_2_GB:=2147483648): 'SMU_MEMORY_POOL_SIZE_2_GB'}
|
||||
enum_smu_clk_type: dict[int, str] = {(SMU_GFXCLK:=0): 'SMU_GFXCLK', (SMU_VCLK:=1): 'SMU_VCLK', (SMU_DCLK:=2): 'SMU_DCLK', (SMU_VCLK1:=3): 'SMU_VCLK1', (SMU_DCLK1:=4): 'SMU_DCLK1', (SMU_ECLK:=5): 'SMU_ECLK', (SMU_SOCCLK:=6): 'SMU_SOCCLK', (SMU_UCLK:=7): 'SMU_UCLK', (SMU_DCEFCLK:=8): 'SMU_DCEFCLK', (SMU_DISPCLK:=9): 'SMU_DISPCLK', (SMU_PIXCLK:=10): 'SMU_PIXCLK', (SMU_PHYCLK:=11): 'SMU_PHYCLK', (SMU_FCLK:=12): 'SMU_FCLK', (SMU_SCLK:=13): 'SMU_SCLK', (SMU_MCLK:=14): 'SMU_MCLK', (SMU_PCIE:=15): 'SMU_PCIE', (SMU_LCLK:=16): 'SMU_LCLK', (SMU_OD_CCLK:=17): 'SMU_OD_CCLK', (SMU_OD_SCLK:=18): 'SMU_OD_SCLK', (SMU_OD_MCLK:=19): 'SMU_OD_MCLK', (SMU_OD_VDDC_CURVE:=20): 'SMU_OD_VDDC_CURVE', (SMU_OD_RANGE:=21): 'SMU_OD_RANGE', (SMU_OD_VDDGFX_OFFSET:=22): 'SMU_OD_VDDGFX_OFFSET', (SMU_OD_FAN_CURVE:=23): 'SMU_OD_FAN_CURVE', (SMU_OD_ACOUSTIC_LIMIT:=24): 'SMU_OD_ACOUSTIC_LIMIT', (SMU_OD_ACOUSTIC_TARGET:=25): 'SMU_OD_ACOUSTIC_TARGET', (SMU_OD_FAN_TARGET_TEMPERATURE:=26): 'SMU_OD_FAN_TARGET_TEMPERATURE', (SMU_OD_FAN_MINIMUM_PWM:=27): 'SMU_OD_FAN_MINIMUM_PWM', (SMU_CLK_COUNT:=28): 'SMU_CLK_COUNT'}
|
||||
@c.record
|
||||
class struct_smu_user_dpm_profile(c.Struct):
|
||||
SIZE = 140
|
||||
fan_mode: int
|
||||
power_limit: int
|
||||
fan_speed_pwm: int
|
||||
fan_speed_rpm: int
|
||||
flags: int
|
||||
user_od: int
|
||||
clk_mask: c.Array[ctypes.c_uint32, Literal[28]]
|
||||
clk_dependency: int
|
||||
struct_smu_user_dpm_profile.register_fields([('fan_mode', uint32_t, 0), ('power_limit', uint32_t, 4), ('fan_speed_pwm', uint32_t, 8), ('fan_speed_rpm', uint32_t, 12), ('flags', uint32_t, 16), ('user_od', uint32_t, 20), ('clk_mask', c.Array[uint32_t, Literal[28]], 24), ('clk_dependency', uint32_t, 136)])
|
||||
@c.record
|
||||
class struct_smu_table(c.Struct):
|
||||
SIZE = 48
|
||||
size: int
|
||||
align: int
|
||||
domain: int
|
||||
mc_address: int
|
||||
cpu_addr: ctypes.c_void_p
|
||||
bo: c.POINTER[struct_amdgpu_bo]
|
||||
version: int
|
||||
class struct_amdgpu_bo(c.Struct): pass
|
||||
struct_smu_table.register_fields([('size', uint64_t, 0), ('align', uint32_t, 8), ('domain', uint8_t, 12), ('mc_address', uint64_t, 16), ('cpu_addr', ctypes.c_void_p, 24), ('bo', c.POINTER[struct_amdgpu_bo], 32), ('version', uint32_t, 40)])
|
||||
enum_smu_perf_level_designation: dict[int, str] = {(PERF_LEVEL_ACTIVITY:=0): 'PERF_LEVEL_ACTIVITY', (PERF_LEVEL_POWER_CONTAINMENT:=1): 'PERF_LEVEL_POWER_CONTAINMENT'}
|
||||
@c.record
|
||||
class struct_smu_performance_level(c.Struct):
|
||||
SIZE = 24
|
||||
core_clock: int
|
||||
memory_clock: int
|
||||
vddc: int
|
||||
vddci: int
|
||||
non_local_mem_freq: int
|
||||
non_local_mem_width: int
|
||||
struct_smu_performance_level.register_fields([('core_clock', uint32_t, 0), ('memory_clock', uint32_t, 4), ('vddc', uint32_t, 8), ('vddci', uint32_t, 12), ('non_local_mem_freq', uint32_t, 16), ('non_local_mem_width', uint32_t, 20)])
|
||||
@c.record
|
||||
class struct_smu_clock_info(c.Struct):
|
||||
SIZE = 24
|
||||
min_mem_clk: int
|
||||
max_mem_clk: int
|
||||
min_eng_clk: int
|
||||
max_eng_clk: int
|
||||
min_bus_bandwidth: int
|
||||
max_bus_bandwidth: int
|
||||
struct_smu_clock_info.register_fields([('min_mem_clk', uint32_t, 0), ('max_mem_clk', uint32_t, 4), ('min_eng_clk', uint32_t, 8), ('max_eng_clk', uint32_t, 12), ('min_bus_bandwidth', uint32_t, 16), ('max_bus_bandwidth', uint32_t, 20)])
|
||||
@c.record
|
||||
class struct_smu_bios_boot_up_values(c.Struct):
|
||||
SIZE = 68
|
||||
revision: int
|
||||
gfxclk: int
|
||||
uclk: int
|
||||
socclk: int
|
||||
dcefclk: int
|
||||
eclk: int
|
||||
vclk: int
|
||||
dclk: int
|
||||
vddc: int
|
||||
vddci: int
|
||||
mvddc: int
|
||||
vdd_gfx: int
|
||||
cooling_id: int
|
||||
pp_table_id: int
|
||||
format_revision: int
|
||||
content_revision: int
|
||||
fclk: int
|
||||
lclk: int
|
||||
firmware_caps: int
|
||||
struct_smu_bios_boot_up_values.register_fields([('revision', uint32_t, 0), ('gfxclk', uint32_t, 4), ('uclk', uint32_t, 8), ('socclk', uint32_t, 12), ('dcefclk', uint32_t, 16), ('eclk', uint32_t, 20), ('vclk', uint32_t, 24), ('dclk', uint32_t, 28), ('vddc', uint16_t, 32), ('vddci', uint16_t, 34), ('mvddc', uint16_t, 36), ('vdd_gfx', uint16_t, 38), ('cooling_id', uint8_t, 40), ('pp_table_id', uint32_t, 44), ('format_revision', uint32_t, 48), ('content_revision', uint32_t, 52), ('fclk', uint32_t, 56), ('lclk', uint32_t, 60), ('firmware_caps', uint32_t, 64)])
|
||||
enum_smu_table_id: dict[int, str] = {(SMU_TABLE_PPTABLE:=0): 'SMU_TABLE_PPTABLE', (SMU_TABLE_WATERMARKS:=1): 'SMU_TABLE_WATERMARKS', (SMU_TABLE_CUSTOM_DPM:=2): 'SMU_TABLE_CUSTOM_DPM', (SMU_TABLE_DPMCLOCKS:=3): 'SMU_TABLE_DPMCLOCKS', (SMU_TABLE_AVFS:=4): 'SMU_TABLE_AVFS', (SMU_TABLE_AVFS_PSM_DEBUG:=5): 'SMU_TABLE_AVFS_PSM_DEBUG', (SMU_TABLE_AVFS_FUSE_OVERRIDE:=6): 'SMU_TABLE_AVFS_FUSE_OVERRIDE', (SMU_TABLE_PMSTATUSLOG:=7): 'SMU_TABLE_PMSTATUSLOG', (SMU_TABLE_SMU_METRICS:=8): 'SMU_TABLE_SMU_METRICS', (SMU_TABLE_DRIVER_SMU_CONFIG:=9): 'SMU_TABLE_DRIVER_SMU_CONFIG', (SMU_TABLE_ACTIVITY_MONITOR_COEFF:=10): 'SMU_TABLE_ACTIVITY_MONITOR_COEFF', (SMU_TABLE_OVERDRIVE:=11): 'SMU_TABLE_OVERDRIVE', (SMU_TABLE_I2C_COMMANDS:=12): 'SMU_TABLE_I2C_COMMANDS', (SMU_TABLE_PACE:=13): 'SMU_TABLE_PACE', (SMU_TABLE_ECCINFO:=14): 'SMU_TABLE_ECCINFO', (SMU_TABLE_COMBO_PPTABLE:=15): 'SMU_TABLE_COMBO_PPTABLE', (SMU_TABLE_WIFIBAND:=16): 'SMU_TABLE_WIFIBAND', (SMU_TABLE_COUNT:=17): 'SMU_TABLE_COUNT'}
|
||||
PPSMC_Result_OK = 0x1
|
||||
PPSMC_Result_Failed = 0xFF
|
||||
PPSMC_Result_UnknownCmd = 0xFE
|
||||
PPSMC_Result_CmdRejectedPrereq = 0xFD
|
||||
PPSMC_Result_CmdRejectedBusy = 0xFC
|
||||
PPSMC_MSG_TestMessage = 0x1
|
||||
PPSMC_MSG_GetSmuVersion = 0x2
|
||||
PPSMC_MSG_GfxDriverReset = 0x3
|
||||
PPSMC_MSG_GetDriverIfVersion = 0x4
|
||||
PPSMC_MSG_EnableAllSmuFeatures = 0x5
|
||||
PPSMC_MSG_DisableAllSmuFeatures = 0x6
|
||||
PPSMC_MSG_RequestI2cTransaction = 0x7
|
||||
PPSMC_MSG_GetMetricsVersion = 0x8
|
||||
PPSMC_MSG_GetMetricsTable = 0x9
|
||||
PPSMC_MSG_GetEccInfoTable = 0xA
|
||||
PPSMC_MSG_GetEnabledSmuFeaturesLow = 0xB
|
||||
PPSMC_MSG_GetEnabledSmuFeaturesHigh = 0xC
|
||||
PPSMC_MSG_SetDriverDramAddrHigh = 0xD
|
||||
PPSMC_MSG_SetDriverDramAddrLow = 0xE
|
||||
PPSMC_MSG_SetToolsDramAddrHigh = 0xF
|
||||
PPSMC_MSG_SetToolsDramAddrLow = 0x10
|
||||
PPSMC_MSG_SetSystemVirtualDramAddrHigh = 0x11
|
||||
PPSMC_MSG_SetSystemVirtualDramAddrLow = 0x12
|
||||
PPSMC_MSG_SetSoftMinByFreq = 0x13
|
||||
PPSMC_MSG_SetSoftMaxByFreq = 0x14
|
||||
PPSMC_MSG_GetMinDpmFreq = 0x15
|
||||
PPSMC_MSG_GetMaxDpmFreq = 0x16
|
||||
PPSMC_MSG_GetDpmFreqByIndex = 0x17
|
||||
PPSMC_MSG_SetPptLimit = 0x18
|
||||
PPSMC_MSG_GetPptLimit = 0x19
|
||||
PPSMC_MSG_DramLogSetDramAddrHigh = 0x1A
|
||||
PPSMC_MSG_DramLogSetDramAddrLow = 0x1B
|
||||
PPSMC_MSG_DramLogSetDramSize = 0x1C
|
||||
PPSMC_MSG_GetDebugData = 0x1D
|
||||
PPSMC_MSG_HeavySBR = 0x1E
|
||||
PPSMC_MSG_SetNumBadHbmPagesRetired = 0x1F
|
||||
PPSMC_MSG_DFCstateControl = 0x20
|
||||
PPSMC_MSG_GetGmiPwrDnHyst = 0x21
|
||||
PPSMC_MSG_SetGmiPwrDnHyst = 0x22
|
||||
PPSMC_MSG_GmiPwrDnControl = 0x23
|
||||
PPSMC_MSG_EnterGfxoff = 0x24
|
||||
PPSMC_MSG_ExitGfxoff = 0x25
|
||||
PPSMC_MSG_EnableDeterminism = 0x26
|
||||
PPSMC_MSG_DisableDeterminism = 0x27
|
||||
PPSMC_MSG_DumpSTBtoDram = 0x28
|
||||
PPSMC_MSG_STBtoDramLogSetDramAddrHigh = 0x29
|
||||
PPSMC_MSG_STBtoDramLogSetDramAddrLow = 0x2A
|
||||
PPSMC_MSG_STBtoDramLogSetDramSize = 0x2B
|
||||
PPSMC_MSG_SetSystemVirtualSTBtoDramAddrHigh = 0x2C
|
||||
PPSMC_MSG_SetSystemVirtualSTBtoDramAddrLow = 0x2D
|
||||
PPSMC_MSG_GfxDriverResetRecovery = 0x2E
|
||||
PPSMC_MSG_TriggerVFFLR = 0x2F
|
||||
PPSMC_MSG_SetSoftMinGfxClk = 0x30
|
||||
PPSMC_MSG_SetSoftMaxGfxClk = 0x31
|
||||
PPSMC_MSG_GetMinGfxDpmFreq = 0x32
|
||||
PPSMC_MSG_GetMaxGfxDpmFreq = 0x33
|
||||
PPSMC_MSG_PrepareForDriverUnload = 0x34
|
||||
PPSMC_MSG_ReadThrottlerLimit = 0x35
|
||||
PPSMC_MSG_QueryValidMcaCount = 0x36
|
||||
PPSMC_MSG_McaBankDumpDW = 0x37
|
||||
PPSMC_MSG_GetCTFLimit = 0x38
|
||||
PPSMC_MSG_ClearMcaOnRead = 0x39
|
||||
PPSMC_MSG_QueryValidMcaCeCount = 0x3A
|
||||
PPSMC_MSG_McaBankCeDumpDW = 0x3B
|
||||
PPSMC_MSG_SelectPLPDMode = 0x40
|
||||
PPSMC_MSG_RmaDueToBadPageThreshold = 0x43
|
||||
PPSMC_MSG_SetThrottlingPolicy = 0x44
|
||||
PPSMC_MSG_SetPhsDetWRbwThreshold = 0x45
|
||||
PPSMC_MSG_SetPhsDetWRbwFreqHigh = 0x46
|
||||
PPSMC_MSG_SetPhsDetWRbwFreqLow = 0x47
|
||||
PPSMC_MSG_SetPhsDetWRbwHystDown = 0x48
|
||||
PPSMC_MSG_SetPhsDetWRbwAlpha = 0x49
|
||||
PPSMC_MSG_SetPhsDetOnOff = 0x4A
|
||||
PPSMC_MSG_GetPhsDetResidency = 0x4B
|
||||
PPSMC_MSG_ResetSDMA = 0x4D
|
||||
PPSMC_MSG_GetStaticMetricsTable = 0x59
|
||||
PPSMC_MSG_ResetVCN = 0x5B
|
||||
PPSMC_Message_Count = 0x5C
|
||||
PPSMC_RESET_TYPE_DRIVER_MODE_1_RESET = 0x1
|
||||
PPSMC_RESET_TYPE_DRIVER_MODE_2_RESET = 0x2
|
||||
PPSMC_RESET_TYPE_DRIVER_MODE_3_RESET = 0x3
|
||||
PPSMC_THROTTLING_LIMIT_TYPE_SOCKET = 0x1
|
||||
PPSMC_THROTTLING_LIMIT_TYPE_HBM = 0x2
|
||||
PPSMC_AID_THM_TYPE = 0x1
|
||||
PPSMC_CCD_THM_TYPE = 0x2
|
||||
PPSMC_XCD_THM_TYPE = 0x3
|
||||
PPSMC_HBM_THM_TYPE = 0x4
|
||||
PPSMC_PLPD_MODE_DEFAULT = 0x1
|
||||
PPSMC_PLPD_MODE_OPTIMIZED = 0x2
|
||||
NUM_VCLK_DPM_LEVELS = 4
|
||||
NUM_DCLK_DPM_LEVELS = 4
|
||||
NUM_SOCCLK_DPM_LEVELS = 4
|
||||
NUM_LCLK_DPM_LEVELS = 4
|
||||
NUM_UCLK_DPM_LEVELS = 4
|
||||
NUM_FCLK_DPM_LEVELS = 4
|
||||
NUM_XGMI_DPM_LEVELS = 2
|
||||
NUM_CXL_BITRATES = 4
|
||||
NUM_PCIE_BITRATES = 4
|
||||
NUM_XGMI_BITRATES = 4
|
||||
NUM_XGMI_WIDTHS = 3
|
||||
NUM_SOC_P2S_TABLES = 3
|
||||
NUM_TDP_GROUPS = 4
|
||||
SMU_METRICS_TABLE_VERSION = 0x11
|
||||
SMU_VF_METRICS_TABLE_VERSION = 0x5
|
||||
SMU13_0_6_DRIVER_IF_VERSION = 0x08042024
|
||||
NUM_I2C_CONTROLLERS = 8
|
||||
I2C_CONTROLLER_ENABLED = 1
|
||||
I2C_CONTROLLER_DISABLED = 0
|
||||
MAX_SW_I2C_COMMANDS = 24
|
||||
CMDCONFIG_STOP_BIT = 0
|
||||
CMDCONFIG_RESTART_BIT = 1
|
||||
CMDCONFIG_READWRITE_BIT = 2
|
||||
CMDCONFIG_STOP_MASK = (1 << CMDCONFIG_STOP_BIT)
|
||||
CMDCONFIG_RESTART_MASK = (1 << CMDCONFIG_RESTART_BIT)
|
||||
CMDCONFIG_READWRITE_MASK = (1 << CMDCONFIG_READWRITE_BIT)
|
||||
IH_INTERRUPT_ID_TO_DRIVER = 0xFE
|
||||
IH_INTERRUPT_CONTEXT_ID_THERMAL_THROTTLING = 0x7
|
||||
THROTTLER_PROCHOT_BIT = 0
|
||||
THROTTLER_PPT_BIT = 1
|
||||
THROTTLER_THERMAL_SOCKET_BIT = 2
|
||||
THROTTLER_THERMAL_VR_BIT = 3
|
||||
THROTTLER_THERMAL_HBM_BIT = 4
|
||||
ClearMcaOnRead_UE_FLAG_MASK = 0x1
|
||||
ClearMcaOnRead_CE_POLL_MASK = 0x2
|
||||
SMU_THERMAL_MINIMUM_ALERT_TEMP = 0
|
||||
SMU_THERMAL_MAXIMUM_ALERT_TEMP = 255
|
||||
SMU_TEMPERATURE_UNITS_PER_CENTIGRADES = 1000
|
||||
SMU_FW_NAME_LEN = 0x24
|
||||
SMU_DPM_USER_PROFILE_RESTORE = (1 << 0)
|
||||
SMU_CUSTOM_FAN_SPEED_RPM = (1 << 1)
|
||||
SMU_CUSTOM_FAN_SPEED_PWM = (1 << 2)
|
||||
SMU_THROTTLER_PPT0_BIT = 0
|
||||
SMU_THROTTLER_PPT1_BIT = 1
|
||||
SMU_THROTTLER_PPT2_BIT = 2
|
||||
SMU_THROTTLER_PPT3_BIT = 3
|
||||
SMU_THROTTLER_SPL_BIT = 4
|
||||
SMU_THROTTLER_FPPT_BIT = 5
|
||||
SMU_THROTTLER_SPPT_BIT = 6
|
||||
SMU_THROTTLER_SPPT_APU_BIT = 7
|
||||
SMU_THROTTLER_TDC_GFX_BIT = 16
|
||||
SMU_THROTTLER_TDC_SOC_BIT = 17
|
||||
SMU_THROTTLER_TDC_MEM_BIT = 18
|
||||
SMU_THROTTLER_TDC_VDD_BIT = 19
|
||||
SMU_THROTTLER_TDC_CVIP_BIT = 20
|
||||
SMU_THROTTLER_EDC_CPU_BIT = 21
|
||||
SMU_THROTTLER_EDC_GFX_BIT = 22
|
||||
SMU_THROTTLER_APCC_BIT = 23
|
||||
SMU_THROTTLER_TEMP_GPU_BIT = 32
|
||||
SMU_THROTTLER_TEMP_CORE_BIT = 33
|
||||
SMU_THROTTLER_TEMP_MEM_BIT = 34
|
||||
SMU_THROTTLER_TEMP_EDGE_BIT = 35
|
||||
SMU_THROTTLER_TEMP_HOTSPOT_BIT = 36
|
||||
SMU_THROTTLER_TEMP_SOC_BIT = 37
|
||||
SMU_THROTTLER_TEMP_VR_GFX_BIT = 38
|
||||
SMU_THROTTLER_TEMP_VR_SOC_BIT = 39
|
||||
SMU_THROTTLER_TEMP_VR_MEM0_BIT = 40
|
||||
SMU_THROTTLER_TEMP_VR_MEM1_BIT = 41
|
||||
SMU_THROTTLER_TEMP_LIQUID0_BIT = 42
|
||||
SMU_THROTTLER_TEMP_LIQUID1_BIT = 43
|
||||
SMU_THROTTLER_VRHOT0_BIT = 44
|
||||
SMU_THROTTLER_VRHOT1_BIT = 45
|
||||
SMU_THROTTLER_PROCHOT_CPU_BIT = 46
|
||||
SMU_THROTTLER_PROCHOT_GFX_BIT = 47
|
||||
SMU_THROTTLER_PPM_BIT = 56
|
||||
SMU_THROTTLER_FIT_BIT = 57
|
||||
1563
tinygrad_repo/tinygrad/runtime/autogen/am/smu_14_0_2.py
Normal file
1563
tinygrad_repo/tinygrad/runtime/autogen/am/smu_14_0_2.py
Normal file
File diff suppressed because one or more lines are too long
44
tinygrad_repo/tinygrad/runtime/autogen/am/soc_11.py
Normal file
44
tinygrad_repo/tinygrad/runtime/autogen/am/soc_11.py
Normal file
@@ -0,0 +1,44 @@
|
||||
# mypy: disable-error-code="empty-body"
|
||||
from __future__ import annotations
|
||||
import ctypes
|
||||
from typing import Literal, TypeAlias
|
||||
from tinygrad.runtime.support.c import _IO, _IOW, _IOR, _IOWR
|
||||
from tinygrad.runtime.support import c
|
||||
enum_MTYPE: dict[int, str] = {(MTYPE_C_RW_US:=0): 'MTYPE_C_RW_US', (MTYPE_RESERVED_1:=1): 'MTYPE_RESERVED_1', (MTYPE_C_RO_S:=2): 'MTYPE_C_RO_S', (MTYPE_UC:=3): 'MTYPE_UC', (MTYPE_C_RW_S:=4): 'MTYPE_C_RW_S', (MTYPE_RESERVED_5:=5): 'MTYPE_RESERVED_5', (MTYPE_C_RO_US:=6): 'MTYPE_C_RO_US', (MTYPE_RESERVED_7:=7): 'MTYPE_RESERVED_7'}
|
||||
MTYPE: TypeAlias = ctypes.c_uint32
|
||||
enum_SH_MEM_ADDRESS_MODE: dict[int, str] = {(SH_MEM_ADDRESS_MODE_64:=0): 'SH_MEM_ADDRESS_MODE_64', (SH_MEM_ADDRESS_MODE_32:=1): 'SH_MEM_ADDRESS_MODE_32'}
|
||||
SH_MEM_ADDRESS_MODE: TypeAlias = ctypes.c_uint32
|
||||
enum_SH_MEM_ALIGNMENT_MODE: dict[int, str] = {(SH_MEM_ALIGNMENT_MODE_DWORD:=0): 'SH_MEM_ALIGNMENT_MODE_DWORD', (SH_MEM_ALIGNMENT_MODE_DWORD_STRICT:=1): 'SH_MEM_ALIGNMENT_MODE_DWORD_STRICT', (SH_MEM_ALIGNMENT_MODE_STRICT:=2): 'SH_MEM_ALIGNMENT_MODE_STRICT', (SH_MEM_ALIGNMENT_MODE_UNALIGNED:=3): 'SH_MEM_ALIGNMENT_MODE_UNALIGNED'}
|
||||
SH_MEM_ALIGNMENT_MODE: TypeAlias = ctypes.c_uint32
|
||||
enum_SQ_TT_MODE: dict[int, str] = {(SQ_TT_MODE_OFF:=0): 'SQ_TT_MODE_OFF', (SQ_TT_MODE_ON:=1): 'SQ_TT_MODE_ON', (SQ_TT_MODE_GLOBAL:=2): 'SQ_TT_MODE_GLOBAL', (SQ_TT_MODE_DETAIL:=3): 'SQ_TT_MODE_DETAIL'}
|
||||
SQ_TT_MODE: TypeAlias = ctypes.c_uint32
|
||||
enum_SQ_TT_RT_FREQ: dict[int, str] = {(SQ_TT_RT_FREQ_NEVER:=0): 'SQ_TT_RT_FREQ_NEVER', (SQ_TT_RT_FREQ_1024_CLK:=1): 'SQ_TT_RT_FREQ_1024_CLK', (SQ_TT_RT_FREQ_4096_CLK:=2): 'SQ_TT_RT_FREQ_4096_CLK'}
|
||||
SQ_TT_RT_FREQ: TypeAlias = ctypes.c_uint32
|
||||
enum_SQ_TT_TOKEN_MASK_INST_EXCLUDE: dict[int, str] = {(SQ_TT_INST_EXCLUDE_VMEM_OTHER_SIMD_BIT:=1): 'SQ_TT_INST_EXCLUDE_VMEM_OTHER_SIMD_BIT', (SQ_TT_INST_EXCLUDE_EXPGNT234_BIT:=2): 'SQ_TT_INST_EXCLUDE_EXPGNT234_BIT'}
|
||||
SQ_TT_TOKEN_MASK_INST_EXCLUDE: TypeAlias = ctypes.c_uint32
|
||||
enum_SQ_TT_TOKEN_MASK_INST_EXCLUDE_SHIFT: dict[int, str] = {(SQ_TT_INST_EXCLUDE_VMEM_OTHER_SIMD_SHIFT:=0): 'SQ_TT_INST_EXCLUDE_VMEM_OTHER_SIMD_SHIFT', (SQ_TT_INST_EXCLUDE_EXPGNT234_SHIFT:=1): 'SQ_TT_INST_EXCLUDE_EXPGNT234_SHIFT'}
|
||||
SQ_TT_TOKEN_MASK_INST_EXCLUDE_SHIFT: TypeAlias = ctypes.c_uint32
|
||||
enum_SQ_TT_TOKEN_MASK_REG_EXCLUDE: dict[int, str] = {(SQ_TT_REG_EXCLUDE_USER_DATA_BIT:=1): 'SQ_TT_REG_EXCLUDE_USER_DATA_BIT', (SQ_TT_REG_EXCLUDE_CP_ME_MC_RADDR_BIT:=2): 'SQ_TT_REG_EXCLUDE_CP_ME_MC_RADDR_BIT', (SQ_TT_REG_EXCLUDE_GRBM_COMPUTE_EXCLUDE_BIT:=4): 'SQ_TT_REG_EXCLUDE_GRBM_COMPUTE_EXCLUDE_BIT'}
|
||||
SQ_TT_TOKEN_MASK_REG_EXCLUDE: TypeAlias = ctypes.c_uint32
|
||||
enum_SQ_TT_TOKEN_MASK_REG_EXCLUDE_SHIFT: dict[int, str] = {(SQ_TT_REG_EXCLUDE_USER_DATA_SHIFT:=0): 'SQ_TT_REG_EXCLUDE_USER_DATA_SHIFT', (SQ_TT_REG_EXCLUDE_CP_ME_MC_RADDR_SHIFT:=1): 'SQ_TT_REG_EXCLUDE_CP_ME_MC_RADDR_SHIFT', (SQ_TT_REG_EXCLUDE_GRBM_COMPUTE_EXCLUDE_SHIFT:=2): 'SQ_TT_REG_EXCLUDE_GRBM_COMPUTE_EXCLUDE_SHIFT'}
|
||||
SQ_TT_TOKEN_MASK_REG_EXCLUDE_SHIFT: TypeAlias = ctypes.c_uint32
|
||||
enum_SQ_TT_TOKEN_MASK_REG_INCLUDE: dict[int, str] = {(SQ_TT_TOKEN_MASK_SQDEC_BIT:=1): 'SQ_TT_TOKEN_MASK_SQDEC_BIT', (SQ_TT_TOKEN_MASK_SHDEC_BIT:=2): 'SQ_TT_TOKEN_MASK_SHDEC_BIT', (SQ_TT_TOKEN_MASK_GFXUDEC_BIT:=4): 'SQ_TT_TOKEN_MASK_GFXUDEC_BIT', (SQ_TT_TOKEN_MASK_COMP_BIT:=8): 'SQ_TT_TOKEN_MASK_COMP_BIT', (SQ_TT_TOKEN_MASK_CONTEXT_BIT:=16): 'SQ_TT_TOKEN_MASK_CONTEXT_BIT', (SQ_TT_TOKEN_MASK_CONFIG_BIT:=32): 'SQ_TT_TOKEN_MASK_CONFIG_BIT', (SQ_TT_TOKEN_MASK_ALL_BIT:=64): 'SQ_TT_TOKEN_MASK_ALL_BIT', (SQ_TT_TOKEN_MASK_RSVD_BIT:=128): 'SQ_TT_TOKEN_MASK_RSVD_BIT'}
|
||||
SQ_TT_TOKEN_MASK_REG_INCLUDE: TypeAlias = ctypes.c_uint32
|
||||
enum_SQ_TT_TOKEN_MASK_REG_INCLUDE_SHIFT: dict[int, str] = {(SQ_TT_TOKEN_MASK_SQDEC_SHIFT:=0): 'SQ_TT_TOKEN_MASK_SQDEC_SHIFT', (SQ_TT_TOKEN_MASK_SHDEC_SHIFT:=1): 'SQ_TT_TOKEN_MASK_SHDEC_SHIFT', (SQ_TT_TOKEN_MASK_GFXUDEC_SHIFT:=2): 'SQ_TT_TOKEN_MASK_GFXUDEC_SHIFT', (SQ_TT_TOKEN_MASK_COMP_SHIFT:=3): 'SQ_TT_TOKEN_MASK_COMP_SHIFT', (SQ_TT_TOKEN_MASK_CONTEXT_SHIFT:=4): 'SQ_TT_TOKEN_MASK_CONTEXT_SHIFT', (SQ_TT_TOKEN_MASK_CONFIG_SHIFT:=5): 'SQ_TT_TOKEN_MASK_CONFIG_SHIFT', (SQ_TT_TOKEN_MASK_ALL_SHIFT:=6): 'SQ_TT_TOKEN_MASK_ALL_SHIFT', (SQ_TT_TOKEN_MASK_RSVD_SHIFT:=7): 'SQ_TT_TOKEN_MASK_RSVD_SHIFT'}
|
||||
SQ_TT_TOKEN_MASK_REG_INCLUDE_SHIFT: TypeAlias = ctypes.c_uint32
|
||||
enum_SQ_TT_TOKEN_MASK_TOKEN_EXCLUDE_SHIFT: dict[int, str] = {(SQ_TT_TOKEN_EXCLUDE_VMEMEXEC_SHIFT:=0): 'SQ_TT_TOKEN_EXCLUDE_VMEMEXEC_SHIFT', (SQ_TT_TOKEN_EXCLUDE_ALUEXEC_SHIFT:=1): 'SQ_TT_TOKEN_EXCLUDE_ALUEXEC_SHIFT', (SQ_TT_TOKEN_EXCLUDE_VALUINST_SHIFT:=2): 'SQ_TT_TOKEN_EXCLUDE_VALUINST_SHIFT', (SQ_TT_TOKEN_EXCLUDE_WAVERDY_SHIFT:=3): 'SQ_TT_TOKEN_EXCLUDE_WAVERDY_SHIFT', (SQ_TT_TOKEN_EXCLUDE_WAVESTARTEND_SHIFT:=4): 'SQ_TT_TOKEN_EXCLUDE_WAVESTARTEND_SHIFT', (SQ_TT_TOKEN_EXCLUDE_IMMEDIATE_SHIFT:=5): 'SQ_TT_TOKEN_EXCLUDE_IMMEDIATE_SHIFT', (SQ_TT_TOKEN_EXCLUDE_REG_SHIFT:=6): 'SQ_TT_TOKEN_EXCLUDE_REG_SHIFT', (SQ_TT_TOKEN_EXCLUDE_EVENT_SHIFT:=7): 'SQ_TT_TOKEN_EXCLUDE_EVENT_SHIFT', (SQ_TT_TOKEN_EXCLUDE_INST_SHIFT:=8): 'SQ_TT_TOKEN_EXCLUDE_INST_SHIFT', (SQ_TT_TOKEN_EXCLUDE_UTILCTR_SHIFT:=9): 'SQ_TT_TOKEN_EXCLUDE_UTILCTR_SHIFT', (SQ_TT_TOKEN_EXCLUDE_WAVEALLOC_SHIFT:=10): 'SQ_TT_TOKEN_EXCLUDE_WAVEALLOC_SHIFT', (SQ_TT_TOKEN_EXCLUDE_PERF_SHIFT:=11): 'SQ_TT_TOKEN_EXCLUDE_PERF_SHIFT'}
|
||||
SQ_TT_TOKEN_MASK_TOKEN_EXCLUDE_SHIFT: TypeAlias = ctypes.c_uint32
|
||||
enum_SQ_TT_UTIL_TIMER: dict[int, str] = {(SQ_TT_UTIL_TIMER_100_CLK:=0): 'SQ_TT_UTIL_TIMER_100_CLK', (SQ_TT_UTIL_TIMER_250_CLK:=1): 'SQ_TT_UTIL_TIMER_250_CLK'}
|
||||
SQ_TT_UTIL_TIMER: TypeAlias = ctypes.c_uint32
|
||||
enum_SQ_TT_WAVESTART_MODE: dict[int, str] = {(SQ_TT_WAVESTART_MODE_SHORT:=0): 'SQ_TT_WAVESTART_MODE_SHORT', (SQ_TT_WAVESTART_MODE_ALLOC:=1): 'SQ_TT_WAVESTART_MODE_ALLOC', (SQ_TT_WAVESTART_MODE_PBB_ID:=2): 'SQ_TT_WAVESTART_MODE_PBB_ID'}
|
||||
SQ_TT_WAVESTART_MODE: TypeAlias = ctypes.c_uint32
|
||||
enum_SQ_TT_WTYPE_INCLUDE: dict[int, str] = {(SQ_TT_WTYPE_INCLUDE_PS_BIT:=1): 'SQ_TT_WTYPE_INCLUDE_PS_BIT', (SQ_TT_WTYPE_INCLUDE_RSVD0_BIT:=2): 'SQ_TT_WTYPE_INCLUDE_RSVD0_BIT', (SQ_TT_WTYPE_INCLUDE_GS_BIT:=4): 'SQ_TT_WTYPE_INCLUDE_GS_BIT', (SQ_TT_WTYPE_INCLUDE_RSVD1_BIT:=8): 'SQ_TT_WTYPE_INCLUDE_RSVD1_BIT', (SQ_TT_WTYPE_INCLUDE_HS_BIT:=16): 'SQ_TT_WTYPE_INCLUDE_HS_BIT', (SQ_TT_WTYPE_INCLUDE_RSVD2_BIT:=32): 'SQ_TT_WTYPE_INCLUDE_RSVD2_BIT', (SQ_TT_WTYPE_INCLUDE_CS_BIT:=64): 'SQ_TT_WTYPE_INCLUDE_CS_BIT'}
|
||||
SQ_TT_WTYPE_INCLUDE: TypeAlias = ctypes.c_uint32
|
||||
enum_SQ_TT_WTYPE_INCLUDE_SHIFT: dict[int, str] = {(SQ_TT_WTYPE_INCLUDE_PS_SHIFT:=0): 'SQ_TT_WTYPE_INCLUDE_PS_SHIFT', (SQ_TT_WTYPE_INCLUDE_RSVD0_SHIFT:=1): 'SQ_TT_WTYPE_INCLUDE_RSVD0_SHIFT', (SQ_TT_WTYPE_INCLUDE_GS_SHIFT:=2): 'SQ_TT_WTYPE_INCLUDE_GS_SHIFT', (SQ_TT_WTYPE_INCLUDE_RSVD1_SHIFT:=3): 'SQ_TT_WTYPE_INCLUDE_RSVD1_SHIFT', (SQ_TT_WTYPE_INCLUDE_HS_SHIFT:=4): 'SQ_TT_WTYPE_INCLUDE_HS_SHIFT', (SQ_TT_WTYPE_INCLUDE_RSVD2_SHIFT:=5): 'SQ_TT_WTYPE_INCLUDE_RSVD2_SHIFT', (SQ_TT_WTYPE_INCLUDE_CS_SHIFT:=6): 'SQ_TT_WTYPE_INCLUDE_CS_SHIFT'}
|
||||
SQ_TT_WTYPE_INCLUDE_SHIFT: TypeAlias = ctypes.c_uint32
|
||||
enum_CSCNTL_TYPE: dict[int, str] = {(CSCNTL_TYPE_TG:=0): 'CSCNTL_TYPE_TG', (CSCNTL_TYPE_STATE:=1): 'CSCNTL_TYPE_STATE', (CSCNTL_TYPE_EVENT:=2): 'CSCNTL_TYPE_EVENT', (CSCNTL_TYPE_PRIVATE:=3): 'CSCNTL_TYPE_PRIVATE'}
|
||||
CSCNTL_TYPE: TypeAlias = ctypes.c_uint32
|
||||
enum_CSDATA_TYPE: dict[int, str] = {(CSDATA_TYPE_TG:=0): 'CSDATA_TYPE_TG', (CSDATA_TYPE_STATE:=1): 'CSDATA_TYPE_STATE', (CSDATA_TYPE_EVENT:=2): 'CSDATA_TYPE_EVENT', (CSDATA_TYPE_PRIVATE:=3): 'CSDATA_TYPE_PRIVATE'}
|
||||
CSDATA_TYPE: TypeAlias = ctypes.c_uint32
|
||||
enum_VGT_EVENT_TYPE: dict[int, str] = {(Reserved_0x00:=0): 'Reserved_0x00', (SAMPLE_STREAMOUTSTATS1:=1): 'SAMPLE_STREAMOUTSTATS1', (SAMPLE_STREAMOUTSTATS2:=2): 'SAMPLE_STREAMOUTSTATS2', (SAMPLE_STREAMOUTSTATS3:=3): 'SAMPLE_STREAMOUTSTATS3', (CACHE_FLUSH_TS:=4): 'CACHE_FLUSH_TS', (CONTEXT_DONE:=5): 'CONTEXT_DONE', (CACHE_FLUSH:=6): 'CACHE_FLUSH', (CS_PARTIAL_FLUSH:=7): 'CS_PARTIAL_FLUSH', (VGT_STREAMOUT_SYNC:=8): 'VGT_STREAMOUT_SYNC', (Reserved_0x09:=9): 'Reserved_0x09', (VGT_STREAMOUT_RESET:=10): 'VGT_STREAMOUT_RESET', (END_OF_PIPE_INCR_DE:=11): 'END_OF_PIPE_INCR_DE', (END_OF_PIPE_IB_END:=12): 'END_OF_PIPE_IB_END', (RST_PIX_CNT:=13): 'RST_PIX_CNT', (BREAK_BATCH:=14): 'BREAK_BATCH', (VS_PARTIAL_FLUSH:=15): 'VS_PARTIAL_FLUSH', (PS_PARTIAL_FLUSH:=16): 'PS_PARTIAL_FLUSH', (FLUSH_HS_OUTPUT:=17): 'FLUSH_HS_OUTPUT', (FLUSH_DFSM:=18): 'FLUSH_DFSM', (RESET_TO_LOWEST_VGT:=19): 'RESET_TO_LOWEST_VGT', (CACHE_FLUSH_AND_INV_TS_EVENT:=20): 'CACHE_FLUSH_AND_INV_TS_EVENT', (WAIT_SYNC:=21): 'WAIT_SYNC', (CACHE_FLUSH_AND_INV_EVENT:=22): 'CACHE_FLUSH_AND_INV_EVENT', (PERFCOUNTER_START:=23): 'PERFCOUNTER_START', (PERFCOUNTER_STOP:=24): 'PERFCOUNTER_STOP', (PIPELINESTAT_START:=25): 'PIPELINESTAT_START', (PIPELINESTAT_STOP:=26): 'PIPELINESTAT_STOP', (PERFCOUNTER_SAMPLE:=27): 'PERFCOUNTER_SAMPLE', (FLUSH_ES_OUTPUT:=28): 'FLUSH_ES_OUTPUT', (BIN_CONF_OVERRIDE_CHECK:=29): 'BIN_CONF_OVERRIDE_CHECK', (SAMPLE_PIPELINESTAT:=30): 'SAMPLE_PIPELINESTAT', (SO_VGTSTREAMOUT_FLUSH:=31): 'SO_VGTSTREAMOUT_FLUSH', (SAMPLE_STREAMOUTSTATS:=32): 'SAMPLE_STREAMOUTSTATS', (RESET_VTX_CNT:=33): 'RESET_VTX_CNT', (BLOCK_CONTEXT_DONE:=34): 'BLOCK_CONTEXT_DONE', (CS_CONTEXT_DONE:=35): 'CS_CONTEXT_DONE', (VGT_FLUSH:=36): 'VGT_FLUSH', (TGID_ROLLOVER:=37): 'TGID_ROLLOVER', (SQ_NON_EVENT:=38): 'SQ_NON_EVENT', (SC_SEND_DB_VPZ:=39): 'SC_SEND_DB_VPZ', (BOTTOM_OF_PIPE_TS:=40): 'BOTTOM_OF_PIPE_TS', (FLUSH_SX_TS:=41): 'FLUSH_SX_TS', (DB_CACHE_FLUSH_AND_INV:=42): 'DB_CACHE_FLUSH_AND_INV', (FLUSH_AND_INV_DB_DATA_TS:=43): 'FLUSH_AND_INV_DB_DATA_TS', (FLUSH_AND_INV_DB_META:=44): 'FLUSH_AND_INV_DB_META', (FLUSH_AND_INV_CB_DATA_TS:=45): 'FLUSH_AND_INV_CB_DATA_TS', (FLUSH_AND_INV_CB_META:=46): 'FLUSH_AND_INV_CB_META', (CS_DONE:=47): 'CS_DONE', (PS_DONE:=48): 'PS_DONE', (FLUSH_AND_INV_CB_PIXEL_DATA:=49): 'FLUSH_AND_INV_CB_PIXEL_DATA', (SX_CB_RAT_ACK_REQUEST:=50): 'SX_CB_RAT_ACK_REQUEST', (THREAD_TRACE_START:=51): 'THREAD_TRACE_START', (THREAD_TRACE_STOP:=52): 'THREAD_TRACE_STOP', (THREAD_TRACE_MARKER:=53): 'THREAD_TRACE_MARKER', (THREAD_TRACE_DRAW:=54): 'THREAD_TRACE_DRAW', (THREAD_TRACE_FINISH:=55): 'THREAD_TRACE_FINISH', (PIXEL_PIPE_STAT_CONTROL:=56): 'PIXEL_PIPE_STAT_CONTROL', (PIXEL_PIPE_STAT_DUMP:=57): 'PIXEL_PIPE_STAT_DUMP', (PIXEL_PIPE_STAT_RESET:=58): 'PIXEL_PIPE_STAT_RESET', (CONTEXT_SUSPEND:=59): 'CONTEXT_SUSPEND', (OFFCHIP_HS_DEALLOC:=60): 'OFFCHIP_HS_DEALLOC', (ENABLE_NGG_PIPELINE:=61): 'ENABLE_NGG_PIPELINE', (ENABLE_LEGACY_PIPELINE:=62): 'ENABLE_LEGACY_PIPELINE', (DRAW_DONE:=63): 'DRAW_DONE'}
|
||||
VGT_EVENT_TYPE: TypeAlias = ctypes.c_uint32
|
||||
24
tinygrad_repo/tinygrad/runtime/autogen/am/soc_12.py
Normal file
24
tinygrad_repo/tinygrad/runtime/autogen/am/soc_12.py
Normal file
@@ -0,0 +1,24 @@
|
||||
# mypy: disable-error-code="empty-body"
|
||||
from __future__ import annotations
|
||||
import ctypes
|
||||
from typing import Literal, TypeAlias
|
||||
from tinygrad.runtime.support.c import _IO, _IOW, _IOR, _IOWR
|
||||
from tinygrad.runtime.support import c
|
||||
enum_MTYPE: dict[int, str] = {(MTYPE_C_RW_US:=0): 'MTYPE_C_RW_US', (MTYPE_RESERVED_1:=1): 'MTYPE_RESERVED_1', (MTYPE_C_RO_S:=2): 'MTYPE_C_RO_S', (MTYPE_UC:=3): 'MTYPE_UC', (MTYPE_C_RW_S:=4): 'MTYPE_C_RW_S', (MTYPE_RESERVED_5:=5): 'MTYPE_RESERVED_5', (MTYPE_C_RO_US:=6): 'MTYPE_C_RO_US', (MTYPE_RESERVED_7:=7): 'MTYPE_RESERVED_7'}
|
||||
MTYPE: TypeAlias = ctypes.c_uint32
|
||||
enum_CSCNTL_TYPE: dict[int, str] = {(CSCNTL_TYPE_TG:=0): 'CSCNTL_TYPE_TG', (CSCNTL_TYPE_STATE:=1): 'CSCNTL_TYPE_STATE', (CSCNTL_TYPE_EVENT:=2): 'CSCNTL_TYPE_EVENT', (CSCNTL_TYPE_PRIVATE:=3): 'CSCNTL_TYPE_PRIVATE'}
|
||||
CSCNTL_TYPE: TypeAlias = ctypes.c_uint32
|
||||
enum_CSDATA_TYPE: dict[int, str] = {(CSDATA_TYPE_TG:=0): 'CSDATA_TYPE_TG', (CSDATA_TYPE_STATE:=1): 'CSDATA_TYPE_STATE', (CSDATA_TYPE_EVENT:=2): 'CSDATA_TYPE_EVENT', (CSDATA_TYPE_PRIVATE:=3): 'CSDATA_TYPE_PRIVATE'}
|
||||
CSDATA_TYPE: TypeAlias = ctypes.c_uint32
|
||||
enum_VGT_EVENT_TYPE: dict[int, str] = {(Reserved_0x00:=0): 'Reserved_0x00', (SAMPLE_STREAMOUTSTATS1:=1): 'SAMPLE_STREAMOUTSTATS1', (SAMPLE_STREAMOUTSTATS2:=2): 'SAMPLE_STREAMOUTSTATS2', (SAMPLE_STREAMOUTSTATS3:=3): 'SAMPLE_STREAMOUTSTATS3', (CACHE_FLUSH_TS:=4): 'CACHE_FLUSH_TS', (CONTEXT_DONE:=5): 'CONTEXT_DONE', (CACHE_FLUSH:=6): 'CACHE_FLUSH', (CS_PARTIAL_FLUSH:=7): 'CS_PARTIAL_FLUSH', (VGT_STREAMOUT_SYNC:=8): 'VGT_STREAMOUT_SYNC', (EVENT_STATE_CHANGE:=9): 'EVENT_STATE_CHANGE', (VGT_STREAMOUT_RESET:=10): 'VGT_STREAMOUT_RESET', (END_OF_PIPE_INCR_DE:=11): 'END_OF_PIPE_INCR_DE', (END_OF_PIPE_IB_END:=12): 'END_OF_PIPE_IB_END', (RST_PIX_CNT:=13): 'RST_PIX_CNT', (BREAK_BATCH:=14): 'BREAK_BATCH', (VS_PARTIAL_FLUSH:=15): 'VS_PARTIAL_FLUSH', (PS_PARTIAL_FLUSH:=16): 'PS_PARTIAL_FLUSH', (FLUSH_HS_OUTPUT:=17): 'FLUSH_HS_OUTPUT', (FLUSH_DFSM:=18): 'FLUSH_DFSM', (RESET_TO_LOWEST_VGT:=19): 'RESET_TO_LOWEST_VGT', (CACHE_FLUSH_AND_INV_TS_EVENT:=20): 'CACHE_FLUSH_AND_INV_TS_EVENT', (WAIT_SYNC:=21): 'WAIT_SYNC', (CACHE_FLUSH_AND_INV_EVENT:=22): 'CACHE_FLUSH_AND_INV_EVENT', (PERFCOUNTER_START:=23): 'PERFCOUNTER_START', (PERFCOUNTER_STOP:=24): 'PERFCOUNTER_STOP', (PIPELINESTAT_START:=25): 'PIPELINESTAT_START', (PIPELINESTAT_STOP:=26): 'PIPELINESTAT_STOP', (PERFCOUNTER_SAMPLE:=27): 'PERFCOUNTER_SAMPLE', (FLUSH_ES_OUTPUT:=28): 'FLUSH_ES_OUTPUT', (BIN_CONF_OVERRIDE_CHECK:=29): 'BIN_CONF_OVERRIDE_CHECK', (SAMPLE_PIPELINESTAT:=30): 'SAMPLE_PIPELINESTAT', (SO_VGTSTREAMOUT_FLUSH:=31): 'SO_VGTSTREAMOUT_FLUSH', (SAMPLE_STREAMOUTSTATS:=32): 'SAMPLE_STREAMOUTSTATS', (RESET_VTX_CNT:=33): 'RESET_VTX_CNT', (BLOCK_CONTEXT_DONE:=34): 'BLOCK_CONTEXT_DONE', (CS_CONTEXT_DONE:=35): 'CS_CONTEXT_DONE', (VGT_FLUSH:=36): 'VGT_FLUSH', (TGID_ROLLOVER:=37): 'TGID_ROLLOVER', (SQ_NON_EVENT:=38): 'SQ_NON_EVENT', (SC_SEND_DB_VPZ:=39): 'SC_SEND_DB_VPZ', (BOTTOM_OF_PIPE_TS:=40): 'BOTTOM_OF_PIPE_TS', (FLUSH_SX_TS:=41): 'FLUSH_SX_TS', (DB_CACHE_FLUSH_AND_INV:=42): 'DB_CACHE_FLUSH_AND_INV', (FLUSH_AND_INV_DB_DATA_TS:=43): 'FLUSH_AND_INV_DB_DATA_TS', (FLUSH_AND_INV_DB_META:=44): 'FLUSH_AND_INV_DB_META', (FLUSH_AND_INV_CB_DATA_TS:=45): 'FLUSH_AND_INV_CB_DATA_TS', (FLUSH_AND_INV_CB_META:=46): 'FLUSH_AND_INV_CB_META', (CS_DONE:=47): 'CS_DONE', (PS_DONE:=48): 'PS_DONE', (FLUSH_AND_INV_CB_PIXEL_DATA:=49): 'FLUSH_AND_INV_CB_PIXEL_DATA', (SX_CB_RAT_ACK_REQUEST:=50): 'SX_CB_RAT_ACK_REQUEST', (THREAD_TRACE_START:=51): 'THREAD_TRACE_START', (THREAD_TRACE_STOP:=52): 'THREAD_TRACE_STOP', (THREAD_TRACE_MARKER:=53): 'THREAD_TRACE_MARKER', (THREAD_TRACE_DRAW:=54): 'THREAD_TRACE_DRAW', (THREAD_TRACE_FINISH:=55): 'THREAD_TRACE_FINISH', (PIXEL_PIPE_STAT_CONTROL:=56): 'PIXEL_PIPE_STAT_CONTROL', (PIXEL_PIPE_STAT_DUMP:=57): 'PIXEL_PIPE_STAT_DUMP', (PIXEL_PIPE_STAT_RESET:=58): 'PIXEL_PIPE_STAT_RESET', (CONTEXT_SUSPEND:=59): 'CONTEXT_SUSPEND', (OFFCHIP_HS_DEALLOC:=60): 'OFFCHIP_HS_DEALLOC', (ENABLE_NGG_PIPELINE:=61): 'ENABLE_NGG_PIPELINE', (ENABLE_PIPELINE_NOT_USED:=62): 'ENABLE_PIPELINE_NOT_USED', (DRAW_DONE:=63): 'DRAW_DONE'}
|
||||
VGT_EVENT_TYPE: TypeAlias = ctypes.c_uint32
|
||||
enum_SH_MEM_ADDRESS_MODE: dict[int, str] = {(SH_MEM_ADDRESS_MODE_64:=0): 'SH_MEM_ADDRESS_MODE_64', (SH_MEM_ADDRESS_MODE_32:=1): 'SH_MEM_ADDRESS_MODE_32'}
|
||||
SH_MEM_ADDRESS_MODE: TypeAlias = ctypes.c_uint32
|
||||
enum_SH_MEM_ALIGNMENT_MODE: dict[int, str] = {(SH_MEM_ALIGNMENT_MODE_DWORD:=0): 'SH_MEM_ALIGNMENT_MODE_DWORD', (SH_MEM_ALIGNMENT_MODE_DWORD_STRICT:=1): 'SH_MEM_ALIGNMENT_MODE_DWORD_STRICT', (SH_MEM_ALIGNMENT_MODE_STRICT:=2): 'SH_MEM_ALIGNMENT_MODE_STRICT', (SH_MEM_ALIGNMENT_MODE_UNALIGNED:=3): 'SH_MEM_ALIGNMENT_MODE_UNALIGNED'}
|
||||
SH_MEM_ALIGNMENT_MODE: TypeAlias = ctypes.c_uint32
|
||||
enum_SQ_TT_TOKEN_MASK_REG_INCLUDE: dict[int, str] = {(SQ_TT_TOKEN_MASK_SQDEC_BIT:=1): 'SQ_TT_TOKEN_MASK_SQDEC_BIT', (SQ_TT_TOKEN_MASK_SHDEC_BIT:=2): 'SQ_TT_TOKEN_MASK_SHDEC_BIT', (SQ_TT_TOKEN_MASK_GFXUDEC_BIT:=4): 'SQ_TT_TOKEN_MASK_GFXUDEC_BIT', (SQ_TT_TOKEN_MASK_COMP_BIT:=8): 'SQ_TT_TOKEN_MASK_COMP_BIT', (SQ_TT_TOKEN_MASK_CONTEXT_BIT:=16): 'SQ_TT_TOKEN_MASK_CONTEXT_BIT'}
|
||||
SQ_TT_TOKEN_MASK_REG_INCLUDE: TypeAlias = ctypes.c_uint32
|
||||
enum_SQ_TT_TOKEN_MASK_TOKEN_EXCLUDE_SHIFT: dict[int, str] = {(SQ_TT_TOKEN_EXCLUDE_VMEMEXEC_SHIFT:=0): 'SQ_TT_TOKEN_EXCLUDE_VMEMEXEC_SHIFT', (SQ_TT_TOKEN_EXCLUDE_ALUEXEC_SHIFT:=1): 'SQ_TT_TOKEN_EXCLUDE_ALUEXEC_SHIFT', (SQ_TT_TOKEN_EXCLUDE_WAVERDY_SHIFT:=3): 'SQ_TT_TOKEN_EXCLUDE_WAVERDY_SHIFT'}
|
||||
SQ_TT_TOKEN_MASK_TOKEN_EXCLUDE_SHIFT: TypeAlias = ctypes.c_uint32
|
||||
enum_SQ_TT_MODE: dict[int, str] = {(SQ_TT_MODE_OFF:=0): 'SQ_TT_MODE_OFF', (SQ_TT_MODE_ON:=1): 'SQ_TT_MODE_ON'}
|
||||
SQ_TT_MODE: TypeAlias = ctypes.c_uint32
|
||||
16
tinygrad_repo/tinygrad/runtime/autogen/am/soc_9.py
Normal file
16
tinygrad_repo/tinygrad/runtime/autogen/am/soc_9.py
Normal file
@@ -0,0 +1,16 @@
|
||||
# mypy: disable-error-code="empty-body"
|
||||
from __future__ import annotations
|
||||
import ctypes
|
||||
from typing import Literal, TypeAlias
|
||||
from tinygrad.runtime.support.c import _IO, _IOW, _IOR, _IOWR
|
||||
from tinygrad.runtime.support import c
|
||||
enum_MTYPE: dict[int, str] = {(MTYPE_NC:=0): 'MTYPE_NC', (MTYPE_WC:=1): 'MTYPE_WC', (MTYPE_RW:=1): 'MTYPE_RW', (MTYPE_CC:=2): 'MTYPE_CC', (MTYPE_UC:=3): 'MTYPE_UC'}
|
||||
MTYPE: TypeAlias = ctypes.c_uint32
|
||||
enum_SH_MEM_ADDRESS_MODE: dict[int, str] = {(SH_MEM_ADDRESS_MODE_64:=0): 'SH_MEM_ADDRESS_MODE_64', (SH_MEM_ADDRESS_MODE_32:=1): 'SH_MEM_ADDRESS_MODE_32'}
|
||||
SH_MEM_ADDRESS_MODE: TypeAlias = ctypes.c_uint32
|
||||
enum_SH_MEM_ALIGNMENT_MODE: dict[int, str] = {(SH_MEM_ALIGNMENT_MODE_DWORD:=0): 'SH_MEM_ALIGNMENT_MODE_DWORD', (SH_MEM_ALIGNMENT_MODE_DWORD_STRICT:=1): 'SH_MEM_ALIGNMENT_MODE_DWORD_STRICT', (SH_MEM_ALIGNMENT_MODE_STRICT:=2): 'SH_MEM_ALIGNMENT_MODE_STRICT', (SH_MEM_ALIGNMENT_MODE_UNALIGNED:=3): 'SH_MEM_ALIGNMENT_MODE_UNALIGNED'}
|
||||
SH_MEM_ALIGNMENT_MODE: TypeAlias = ctypes.c_uint32
|
||||
enum_CSDATA_TYPE: dict[int, str] = {(CSDATA_TYPE_TG:=0): 'CSDATA_TYPE_TG', (CSDATA_TYPE_STATE:=1): 'CSDATA_TYPE_STATE', (CSDATA_TYPE_EVENT:=2): 'CSDATA_TYPE_EVENT', (CSDATA_TYPE_PRIVATE:=3): 'CSDATA_TYPE_PRIVATE'}
|
||||
CSDATA_TYPE: TypeAlias = ctypes.c_uint32
|
||||
enum_VGT_EVENT_TYPE: dict[int, str] = {(Reserved_0x00:=0): 'Reserved_0x00', (SAMPLE_STREAMOUTSTATS1:=1): 'SAMPLE_STREAMOUTSTATS1', (SAMPLE_STREAMOUTSTATS2:=2): 'SAMPLE_STREAMOUTSTATS2', (SAMPLE_STREAMOUTSTATS3:=3): 'SAMPLE_STREAMOUTSTATS3', (CACHE_FLUSH_TS:=4): 'CACHE_FLUSH_TS', (CONTEXT_DONE:=5): 'CONTEXT_DONE', (CACHE_FLUSH:=6): 'CACHE_FLUSH', (CS_PARTIAL_FLUSH:=7): 'CS_PARTIAL_FLUSH', (VGT_STREAMOUT_SYNC:=8): 'VGT_STREAMOUT_SYNC', (Reserved_0x09:=9): 'Reserved_0x09', (VGT_STREAMOUT_RESET:=10): 'VGT_STREAMOUT_RESET', (END_OF_PIPE_INCR_DE:=11): 'END_OF_PIPE_INCR_DE', (END_OF_PIPE_IB_END:=12): 'END_OF_PIPE_IB_END', (RST_PIX_CNT:=13): 'RST_PIX_CNT', (BREAK_BATCH:=14): 'BREAK_BATCH', (VS_PARTIAL_FLUSH:=15): 'VS_PARTIAL_FLUSH', (PS_PARTIAL_FLUSH:=16): 'PS_PARTIAL_FLUSH', (FLUSH_HS_OUTPUT:=17): 'FLUSH_HS_OUTPUT', (FLUSH_DFSM:=18): 'FLUSH_DFSM', (RESET_TO_LOWEST_VGT:=19): 'RESET_TO_LOWEST_VGT', (CACHE_FLUSH_AND_INV_TS_EVENT:=20): 'CACHE_FLUSH_AND_INV_TS_EVENT', (ZPASS_DONE:=21): 'ZPASS_DONE', (CACHE_FLUSH_AND_INV_EVENT:=22): 'CACHE_FLUSH_AND_INV_EVENT', (PERFCOUNTER_START:=23): 'PERFCOUNTER_START', (PERFCOUNTER_STOP:=24): 'PERFCOUNTER_STOP', (PIPELINESTAT_START:=25): 'PIPELINESTAT_START', (PIPELINESTAT_STOP:=26): 'PIPELINESTAT_STOP', (PERFCOUNTER_SAMPLE:=27): 'PERFCOUNTER_SAMPLE', (Available_0x1c:=28): 'Available_0x1c', (Available_0x1d:=29): 'Available_0x1d', (SAMPLE_PIPELINESTAT:=30): 'SAMPLE_PIPELINESTAT', (SO_VGTSTREAMOUT_FLUSH:=31): 'SO_VGTSTREAMOUT_FLUSH', (SAMPLE_STREAMOUTSTATS:=32): 'SAMPLE_STREAMOUTSTATS', (RESET_VTX_CNT:=33): 'RESET_VTX_CNT', (BLOCK_CONTEXT_DONE:=34): 'BLOCK_CONTEXT_DONE', (CS_CONTEXT_DONE:=35): 'CS_CONTEXT_DONE', (VGT_FLUSH:=36): 'VGT_FLUSH', (TGID_ROLLOVER:=37): 'TGID_ROLLOVER', (SQ_NON_EVENT:=38): 'SQ_NON_EVENT', (SC_SEND_DB_VPZ:=39): 'SC_SEND_DB_VPZ', (BOTTOM_OF_PIPE_TS:=40): 'BOTTOM_OF_PIPE_TS', (FLUSH_SX_TS:=41): 'FLUSH_SX_TS', (DB_CACHE_FLUSH_AND_INV:=42): 'DB_CACHE_FLUSH_AND_INV', (FLUSH_AND_INV_DB_DATA_TS:=43): 'FLUSH_AND_INV_DB_DATA_TS', (FLUSH_AND_INV_DB_META:=44): 'FLUSH_AND_INV_DB_META', (FLUSH_AND_INV_CB_DATA_TS:=45): 'FLUSH_AND_INV_CB_DATA_TS', (FLUSH_AND_INV_CB_META:=46): 'FLUSH_AND_INV_CB_META', (CS_DONE:=47): 'CS_DONE', (PS_DONE:=48): 'PS_DONE', (FLUSH_AND_INV_CB_PIXEL_DATA:=49): 'FLUSH_AND_INV_CB_PIXEL_DATA', (SX_CB_RAT_ACK_REQUEST:=50): 'SX_CB_RAT_ACK_REQUEST', (THREAD_TRACE_START:=51): 'THREAD_TRACE_START', (THREAD_TRACE_STOP:=52): 'THREAD_TRACE_STOP', (THREAD_TRACE_MARKER:=53): 'THREAD_TRACE_MARKER', (THREAD_TRACE_FLUSH:=54): 'THREAD_TRACE_FLUSH', (THREAD_TRACE_FINISH:=55): 'THREAD_TRACE_FINISH', (PIXEL_PIPE_STAT_CONTROL:=56): 'PIXEL_PIPE_STAT_CONTROL', (PIXEL_PIPE_STAT_DUMP:=57): 'PIXEL_PIPE_STAT_DUMP', (PIXEL_PIPE_STAT_RESET:=58): 'PIXEL_PIPE_STAT_RESET', (CONTEXT_SUSPEND:=59): 'CONTEXT_SUSPEND', (OFFCHIP_HS_DEALLOC:=60): 'OFFCHIP_HS_DEALLOC', (ENABLE_NGG_PIPELINE:=61): 'ENABLE_NGG_PIPELINE', (ENABLE_LEGACY_PIPELINE:=62): 'ENABLE_LEGACY_PIPELINE', (Reserved_0x3f:=63): 'Reserved_0x3f'}
|
||||
VGT_EVENT_TYPE: TypeAlias = ctypes.c_uint32
|
||||
774
tinygrad_repo/tinygrad/runtime/autogen/am/vega_offsets.py
Normal file
774
tinygrad_repo/tinygrad/runtime/autogen/am/vega_offsets.py
Normal file
@@ -0,0 +1,774 @@
|
||||
# mypy: disable-error-code="empty-body"
|
||||
from __future__ import annotations
|
||||
import ctypes
|
||||
from typing import Literal, TypeAlias
|
||||
from tinygrad.runtime.support.c import _IO, _IOW, _IOR, _IOWR
|
||||
from tinygrad.runtime.support import c
|
||||
@c.record
|
||||
class struct_IP_BASE_INSTANCE(c.Struct):
|
||||
SIZE = 24
|
||||
segment: c.Array[ctypes.c_uint32, Literal[6]]
|
||||
struct_IP_BASE_INSTANCE.register_fields([('segment', c.Array[ctypes.c_uint32, Literal[6]], 0)])
|
||||
@c.record
|
||||
class struct_IP_BASE(c.Struct):
|
||||
SIZE = 144
|
||||
instance: c.Array[struct_IP_BASE_INSTANCE, Literal[6]]
|
||||
struct_IP_BASE.register_fields([('instance', c.Array[struct_IP_BASE_INSTANCE, Literal[6]], 0)])
|
||||
MAX_INSTANCE = 6
|
||||
MAX_SEGMENT = 6
|
||||
ATHUB_BASE__INST0_SEG0 = 0x00000C20
|
||||
ATHUB_BASE__INST0_SEG1 = 0
|
||||
ATHUB_BASE__INST0_SEG2 = 0
|
||||
ATHUB_BASE__INST0_SEG3 = 0
|
||||
ATHUB_BASE__INST0_SEG4 = 0
|
||||
ATHUB_BASE__INST0_SEG5 = 0
|
||||
ATHUB_BASE__INST1_SEG0 = 0
|
||||
ATHUB_BASE__INST1_SEG1 = 0
|
||||
ATHUB_BASE__INST1_SEG2 = 0
|
||||
ATHUB_BASE__INST1_SEG3 = 0
|
||||
ATHUB_BASE__INST1_SEG4 = 0
|
||||
ATHUB_BASE__INST1_SEG5 = 0
|
||||
ATHUB_BASE__INST2_SEG0 = 0
|
||||
ATHUB_BASE__INST2_SEG1 = 0
|
||||
ATHUB_BASE__INST2_SEG2 = 0
|
||||
ATHUB_BASE__INST2_SEG3 = 0
|
||||
ATHUB_BASE__INST2_SEG4 = 0
|
||||
ATHUB_BASE__INST2_SEG5 = 0
|
||||
ATHUB_BASE__INST3_SEG0 = 0
|
||||
ATHUB_BASE__INST3_SEG1 = 0
|
||||
ATHUB_BASE__INST3_SEG2 = 0
|
||||
ATHUB_BASE__INST3_SEG3 = 0
|
||||
ATHUB_BASE__INST3_SEG4 = 0
|
||||
ATHUB_BASE__INST3_SEG5 = 0
|
||||
ATHUB_BASE__INST4_SEG0 = 0
|
||||
ATHUB_BASE__INST4_SEG1 = 0
|
||||
ATHUB_BASE__INST4_SEG2 = 0
|
||||
ATHUB_BASE__INST4_SEG3 = 0
|
||||
ATHUB_BASE__INST4_SEG4 = 0
|
||||
ATHUB_BASE__INST4_SEG5 = 0
|
||||
ATHUB_BASE__INST5_SEG0 = 0
|
||||
ATHUB_BASE__INST5_SEG1 = 0
|
||||
ATHUB_BASE__INST5_SEG2 = 0
|
||||
ATHUB_BASE__INST5_SEG3 = 0
|
||||
ATHUB_BASE__INST5_SEG4 = 0
|
||||
ATHUB_BASE__INST5_SEG5 = 0
|
||||
CLK_BASE__INST0_SEG0 = 0x00016C00
|
||||
CLK_BASE__INST0_SEG1 = 0x00016E00
|
||||
CLK_BASE__INST0_SEG2 = 0x00017000
|
||||
CLK_BASE__INST0_SEG3 = 0x00017200
|
||||
CLK_BASE__INST0_SEG4 = 0x0001B000
|
||||
CLK_BASE__INST0_SEG5 = 0x0001B200
|
||||
CLK_BASE__INST1_SEG0 = 0
|
||||
CLK_BASE__INST1_SEG1 = 0
|
||||
CLK_BASE__INST1_SEG2 = 0
|
||||
CLK_BASE__INST1_SEG3 = 0
|
||||
CLK_BASE__INST1_SEG4 = 0
|
||||
CLK_BASE__INST1_SEG5 = 0
|
||||
CLK_BASE__INST2_SEG0 = 0
|
||||
CLK_BASE__INST2_SEG1 = 0
|
||||
CLK_BASE__INST2_SEG2 = 0
|
||||
CLK_BASE__INST2_SEG3 = 0
|
||||
CLK_BASE__INST2_SEG4 = 0
|
||||
CLK_BASE__INST2_SEG5 = 0
|
||||
CLK_BASE__INST3_SEG0 = 0
|
||||
CLK_BASE__INST3_SEG1 = 0
|
||||
CLK_BASE__INST3_SEG2 = 0
|
||||
CLK_BASE__INST3_SEG3 = 0
|
||||
CLK_BASE__INST3_SEG4 = 0
|
||||
CLK_BASE__INST3_SEG5 = 0
|
||||
CLK_BASE__INST4_SEG0 = 0
|
||||
CLK_BASE__INST4_SEG1 = 0
|
||||
CLK_BASE__INST4_SEG2 = 0
|
||||
CLK_BASE__INST4_SEG3 = 0
|
||||
CLK_BASE__INST4_SEG4 = 0
|
||||
CLK_BASE__INST4_SEG5 = 0
|
||||
CLK_BASE__INST5_SEG0 = 0
|
||||
CLK_BASE__INST5_SEG1 = 0
|
||||
CLK_BASE__INST5_SEG2 = 0
|
||||
CLK_BASE__INST5_SEG3 = 0
|
||||
CLK_BASE__INST5_SEG4 = 0
|
||||
CLK_BASE__INST5_SEG5 = 0
|
||||
DCE_BASE__INST0_SEG0 = 0x00000012
|
||||
DCE_BASE__INST0_SEG1 = 0x000000C0
|
||||
DCE_BASE__INST0_SEG2 = 0x000034C0
|
||||
DCE_BASE__INST0_SEG3 = 0
|
||||
DCE_BASE__INST0_SEG4 = 0
|
||||
DCE_BASE__INST0_SEG5 = 0
|
||||
DCE_BASE__INST1_SEG0 = 0
|
||||
DCE_BASE__INST1_SEG1 = 0
|
||||
DCE_BASE__INST1_SEG2 = 0
|
||||
DCE_BASE__INST1_SEG3 = 0
|
||||
DCE_BASE__INST1_SEG4 = 0
|
||||
DCE_BASE__INST1_SEG5 = 0
|
||||
DCE_BASE__INST2_SEG0 = 0
|
||||
DCE_BASE__INST2_SEG1 = 0
|
||||
DCE_BASE__INST2_SEG2 = 0
|
||||
DCE_BASE__INST2_SEG3 = 0
|
||||
DCE_BASE__INST2_SEG4 = 0
|
||||
DCE_BASE__INST2_SEG5 = 0
|
||||
DCE_BASE__INST3_SEG0 = 0
|
||||
DCE_BASE__INST3_SEG1 = 0
|
||||
DCE_BASE__INST3_SEG2 = 0
|
||||
DCE_BASE__INST3_SEG3 = 0
|
||||
DCE_BASE__INST3_SEG4 = 0
|
||||
DCE_BASE__INST3_SEG5 = 0
|
||||
DCE_BASE__INST4_SEG0 = 0
|
||||
DCE_BASE__INST4_SEG1 = 0
|
||||
DCE_BASE__INST4_SEG2 = 0
|
||||
DCE_BASE__INST4_SEG3 = 0
|
||||
DCE_BASE__INST4_SEG4 = 0
|
||||
DCE_BASE__INST4_SEG5 = 0
|
||||
DCE_BASE__INST5_SEG0 = 0
|
||||
DCE_BASE__INST5_SEG1 = 0
|
||||
DCE_BASE__INST5_SEG2 = 0
|
||||
DCE_BASE__INST5_SEG3 = 0
|
||||
DCE_BASE__INST5_SEG4 = 0
|
||||
DCE_BASE__INST5_SEG5 = 0
|
||||
DF_BASE__INST0_SEG0 = 0x00007000
|
||||
DF_BASE__INST0_SEG1 = 0
|
||||
DF_BASE__INST0_SEG2 = 0
|
||||
DF_BASE__INST0_SEG3 = 0
|
||||
DF_BASE__INST0_SEG4 = 0
|
||||
DF_BASE__INST0_SEG5 = 0
|
||||
DF_BASE__INST1_SEG0 = 0
|
||||
DF_BASE__INST1_SEG1 = 0
|
||||
DF_BASE__INST1_SEG2 = 0
|
||||
DF_BASE__INST1_SEG3 = 0
|
||||
DF_BASE__INST1_SEG4 = 0
|
||||
DF_BASE__INST1_SEG5 = 0
|
||||
DF_BASE__INST2_SEG0 = 0
|
||||
DF_BASE__INST2_SEG1 = 0
|
||||
DF_BASE__INST2_SEG2 = 0
|
||||
DF_BASE__INST2_SEG3 = 0
|
||||
DF_BASE__INST2_SEG4 = 0
|
||||
DF_BASE__INST2_SEG5 = 0
|
||||
DF_BASE__INST3_SEG0 = 0
|
||||
DF_BASE__INST3_SEG1 = 0
|
||||
DF_BASE__INST3_SEG2 = 0
|
||||
DF_BASE__INST3_SEG3 = 0
|
||||
DF_BASE__INST3_SEG4 = 0
|
||||
DF_BASE__INST3_SEG5 = 0
|
||||
DF_BASE__INST4_SEG0 = 0
|
||||
DF_BASE__INST4_SEG1 = 0
|
||||
DF_BASE__INST4_SEG2 = 0
|
||||
DF_BASE__INST4_SEG3 = 0
|
||||
DF_BASE__INST4_SEG4 = 0
|
||||
DF_BASE__INST4_SEG5 = 0
|
||||
DF_BASE__INST5_SEG0 = 0
|
||||
DF_BASE__INST5_SEG1 = 0
|
||||
DF_BASE__INST5_SEG2 = 0
|
||||
DF_BASE__INST5_SEG3 = 0
|
||||
DF_BASE__INST5_SEG4 = 0
|
||||
DF_BASE__INST5_SEG5 = 0
|
||||
FUSE_BASE__INST0_SEG0 = 0x00017400
|
||||
FUSE_BASE__INST0_SEG1 = 0
|
||||
FUSE_BASE__INST0_SEG2 = 0
|
||||
FUSE_BASE__INST0_SEG3 = 0
|
||||
FUSE_BASE__INST0_SEG4 = 0
|
||||
FUSE_BASE__INST0_SEG5 = 0
|
||||
FUSE_BASE__INST1_SEG0 = 0
|
||||
FUSE_BASE__INST1_SEG1 = 0
|
||||
FUSE_BASE__INST1_SEG2 = 0
|
||||
FUSE_BASE__INST1_SEG3 = 0
|
||||
FUSE_BASE__INST1_SEG4 = 0
|
||||
FUSE_BASE__INST1_SEG5 = 0
|
||||
FUSE_BASE__INST2_SEG0 = 0
|
||||
FUSE_BASE__INST2_SEG1 = 0
|
||||
FUSE_BASE__INST2_SEG2 = 0
|
||||
FUSE_BASE__INST2_SEG3 = 0
|
||||
FUSE_BASE__INST2_SEG4 = 0
|
||||
FUSE_BASE__INST2_SEG5 = 0
|
||||
FUSE_BASE__INST3_SEG0 = 0
|
||||
FUSE_BASE__INST3_SEG1 = 0
|
||||
FUSE_BASE__INST3_SEG2 = 0
|
||||
FUSE_BASE__INST3_SEG3 = 0
|
||||
FUSE_BASE__INST3_SEG4 = 0
|
||||
FUSE_BASE__INST3_SEG5 = 0
|
||||
FUSE_BASE__INST4_SEG0 = 0
|
||||
FUSE_BASE__INST4_SEG1 = 0
|
||||
FUSE_BASE__INST4_SEG2 = 0
|
||||
FUSE_BASE__INST4_SEG3 = 0
|
||||
FUSE_BASE__INST4_SEG4 = 0
|
||||
FUSE_BASE__INST4_SEG5 = 0
|
||||
FUSE_BASE__INST5_SEG0 = 0
|
||||
FUSE_BASE__INST5_SEG1 = 0
|
||||
FUSE_BASE__INST5_SEG2 = 0
|
||||
FUSE_BASE__INST5_SEG3 = 0
|
||||
FUSE_BASE__INST5_SEG4 = 0
|
||||
FUSE_BASE__INST5_SEG5 = 0
|
||||
GC_BASE__INST0_SEG0 = 0x00002000
|
||||
GC_BASE__INST0_SEG1 = 0x0000A000
|
||||
GC_BASE__INST0_SEG2 = 0
|
||||
GC_BASE__INST0_SEG3 = 0
|
||||
GC_BASE__INST0_SEG4 = 0
|
||||
GC_BASE__INST0_SEG5 = 0
|
||||
GC_BASE__INST1_SEG0 = 0
|
||||
GC_BASE__INST1_SEG1 = 0
|
||||
GC_BASE__INST1_SEG2 = 0
|
||||
GC_BASE__INST1_SEG3 = 0
|
||||
GC_BASE__INST1_SEG4 = 0
|
||||
GC_BASE__INST1_SEG5 = 0
|
||||
GC_BASE__INST2_SEG0 = 0
|
||||
GC_BASE__INST2_SEG1 = 0
|
||||
GC_BASE__INST2_SEG2 = 0
|
||||
GC_BASE__INST2_SEG3 = 0
|
||||
GC_BASE__INST2_SEG4 = 0
|
||||
GC_BASE__INST2_SEG5 = 0
|
||||
GC_BASE__INST3_SEG0 = 0
|
||||
GC_BASE__INST3_SEG1 = 0
|
||||
GC_BASE__INST3_SEG2 = 0
|
||||
GC_BASE__INST3_SEG3 = 0
|
||||
GC_BASE__INST3_SEG4 = 0
|
||||
GC_BASE__INST3_SEG5 = 0
|
||||
GC_BASE__INST4_SEG0 = 0
|
||||
GC_BASE__INST4_SEG1 = 0
|
||||
GC_BASE__INST4_SEG2 = 0
|
||||
GC_BASE__INST4_SEG3 = 0
|
||||
GC_BASE__INST4_SEG4 = 0
|
||||
GC_BASE__INST4_SEG5 = 0
|
||||
GC_BASE__INST5_SEG0 = 0
|
||||
GC_BASE__INST5_SEG1 = 0
|
||||
GC_BASE__INST5_SEG2 = 0
|
||||
GC_BASE__INST5_SEG3 = 0
|
||||
GC_BASE__INST5_SEG4 = 0
|
||||
GC_BASE__INST5_SEG5 = 0
|
||||
HDP_BASE__INST0_SEG0 = 0x00000F20
|
||||
HDP_BASE__INST0_SEG1 = 0
|
||||
HDP_BASE__INST0_SEG2 = 0
|
||||
HDP_BASE__INST0_SEG3 = 0
|
||||
HDP_BASE__INST0_SEG4 = 0
|
||||
HDP_BASE__INST0_SEG5 = 0
|
||||
HDP_BASE__INST1_SEG0 = 0
|
||||
HDP_BASE__INST1_SEG1 = 0
|
||||
HDP_BASE__INST1_SEG2 = 0
|
||||
HDP_BASE__INST1_SEG3 = 0
|
||||
HDP_BASE__INST1_SEG4 = 0
|
||||
HDP_BASE__INST1_SEG5 = 0
|
||||
HDP_BASE__INST2_SEG0 = 0
|
||||
HDP_BASE__INST2_SEG1 = 0
|
||||
HDP_BASE__INST2_SEG2 = 0
|
||||
HDP_BASE__INST2_SEG3 = 0
|
||||
HDP_BASE__INST2_SEG4 = 0
|
||||
HDP_BASE__INST2_SEG5 = 0
|
||||
HDP_BASE__INST3_SEG0 = 0
|
||||
HDP_BASE__INST3_SEG1 = 0
|
||||
HDP_BASE__INST3_SEG2 = 0
|
||||
HDP_BASE__INST3_SEG3 = 0
|
||||
HDP_BASE__INST3_SEG4 = 0
|
||||
HDP_BASE__INST3_SEG5 = 0
|
||||
HDP_BASE__INST4_SEG0 = 0
|
||||
HDP_BASE__INST4_SEG1 = 0
|
||||
HDP_BASE__INST4_SEG2 = 0
|
||||
HDP_BASE__INST4_SEG3 = 0
|
||||
HDP_BASE__INST4_SEG4 = 0
|
||||
HDP_BASE__INST4_SEG5 = 0
|
||||
HDP_BASE__INST5_SEG0 = 0
|
||||
HDP_BASE__INST5_SEG1 = 0
|
||||
HDP_BASE__INST5_SEG2 = 0
|
||||
HDP_BASE__INST5_SEG3 = 0
|
||||
HDP_BASE__INST5_SEG4 = 0
|
||||
HDP_BASE__INST5_SEG5 = 0
|
||||
MMHUB_BASE__INST0_SEG0 = 0x0001A000
|
||||
MMHUB_BASE__INST0_SEG1 = 0
|
||||
MMHUB_BASE__INST0_SEG2 = 0
|
||||
MMHUB_BASE__INST0_SEG3 = 0
|
||||
MMHUB_BASE__INST0_SEG4 = 0
|
||||
MMHUB_BASE__INST0_SEG5 = 0
|
||||
MMHUB_BASE__INST1_SEG0 = 0
|
||||
MMHUB_BASE__INST1_SEG1 = 0
|
||||
MMHUB_BASE__INST1_SEG2 = 0
|
||||
MMHUB_BASE__INST1_SEG3 = 0
|
||||
MMHUB_BASE__INST1_SEG4 = 0
|
||||
MMHUB_BASE__INST1_SEG5 = 0
|
||||
MMHUB_BASE__INST2_SEG0 = 0
|
||||
MMHUB_BASE__INST2_SEG1 = 0
|
||||
MMHUB_BASE__INST2_SEG2 = 0
|
||||
MMHUB_BASE__INST2_SEG3 = 0
|
||||
MMHUB_BASE__INST2_SEG4 = 0
|
||||
MMHUB_BASE__INST2_SEG5 = 0
|
||||
MMHUB_BASE__INST3_SEG0 = 0
|
||||
MMHUB_BASE__INST3_SEG1 = 0
|
||||
MMHUB_BASE__INST3_SEG2 = 0
|
||||
MMHUB_BASE__INST3_SEG3 = 0
|
||||
MMHUB_BASE__INST3_SEG4 = 0
|
||||
MMHUB_BASE__INST3_SEG5 = 0
|
||||
MMHUB_BASE__INST4_SEG0 = 0
|
||||
MMHUB_BASE__INST4_SEG1 = 0
|
||||
MMHUB_BASE__INST4_SEG2 = 0
|
||||
MMHUB_BASE__INST4_SEG3 = 0
|
||||
MMHUB_BASE__INST4_SEG4 = 0
|
||||
MMHUB_BASE__INST4_SEG5 = 0
|
||||
MMHUB_BASE__INST5_SEG0 = 0
|
||||
MMHUB_BASE__INST5_SEG1 = 0
|
||||
MMHUB_BASE__INST5_SEG2 = 0
|
||||
MMHUB_BASE__INST5_SEG3 = 0
|
||||
MMHUB_BASE__INST5_SEG4 = 0
|
||||
MMHUB_BASE__INST5_SEG5 = 0
|
||||
MP0_BASE__INST0_SEG0 = 0x00016000
|
||||
MP0_BASE__INST0_SEG1 = 0
|
||||
MP0_BASE__INST0_SEG2 = 0
|
||||
MP0_BASE__INST0_SEG3 = 0
|
||||
MP0_BASE__INST0_SEG4 = 0
|
||||
MP0_BASE__INST0_SEG5 = 0
|
||||
MP0_BASE__INST1_SEG0 = 0
|
||||
MP0_BASE__INST1_SEG1 = 0
|
||||
MP0_BASE__INST1_SEG2 = 0
|
||||
MP0_BASE__INST1_SEG3 = 0
|
||||
MP0_BASE__INST1_SEG4 = 0
|
||||
MP0_BASE__INST1_SEG5 = 0
|
||||
MP0_BASE__INST2_SEG0 = 0
|
||||
MP0_BASE__INST2_SEG1 = 0
|
||||
MP0_BASE__INST2_SEG2 = 0
|
||||
MP0_BASE__INST2_SEG3 = 0
|
||||
MP0_BASE__INST2_SEG4 = 0
|
||||
MP0_BASE__INST2_SEG5 = 0
|
||||
MP0_BASE__INST3_SEG0 = 0
|
||||
MP0_BASE__INST3_SEG1 = 0
|
||||
MP0_BASE__INST3_SEG2 = 0
|
||||
MP0_BASE__INST3_SEG3 = 0
|
||||
MP0_BASE__INST3_SEG4 = 0
|
||||
MP0_BASE__INST3_SEG5 = 0
|
||||
MP0_BASE__INST4_SEG0 = 0
|
||||
MP0_BASE__INST4_SEG1 = 0
|
||||
MP0_BASE__INST4_SEG2 = 0
|
||||
MP0_BASE__INST4_SEG3 = 0
|
||||
MP0_BASE__INST4_SEG4 = 0
|
||||
MP0_BASE__INST4_SEG5 = 0
|
||||
MP0_BASE__INST5_SEG0 = 0
|
||||
MP0_BASE__INST5_SEG1 = 0
|
||||
MP0_BASE__INST5_SEG2 = 0
|
||||
MP0_BASE__INST5_SEG3 = 0
|
||||
MP0_BASE__INST5_SEG4 = 0
|
||||
MP0_BASE__INST5_SEG5 = 0
|
||||
MP1_BASE__INST0_SEG0 = 0x00016000
|
||||
MP1_BASE__INST0_SEG1 = 0
|
||||
MP1_BASE__INST0_SEG2 = 0
|
||||
MP1_BASE__INST0_SEG3 = 0
|
||||
MP1_BASE__INST0_SEG4 = 0
|
||||
MP1_BASE__INST0_SEG5 = 0
|
||||
MP1_BASE__INST1_SEG0 = 0
|
||||
MP1_BASE__INST1_SEG1 = 0
|
||||
MP1_BASE__INST1_SEG2 = 0
|
||||
MP1_BASE__INST1_SEG3 = 0
|
||||
MP1_BASE__INST1_SEG4 = 0
|
||||
MP1_BASE__INST1_SEG5 = 0
|
||||
MP1_BASE__INST2_SEG0 = 0
|
||||
MP1_BASE__INST2_SEG1 = 0
|
||||
MP1_BASE__INST2_SEG2 = 0
|
||||
MP1_BASE__INST2_SEG3 = 0
|
||||
MP1_BASE__INST2_SEG4 = 0
|
||||
MP1_BASE__INST2_SEG5 = 0
|
||||
MP1_BASE__INST3_SEG0 = 0
|
||||
MP1_BASE__INST3_SEG1 = 0
|
||||
MP1_BASE__INST3_SEG2 = 0
|
||||
MP1_BASE__INST3_SEG3 = 0
|
||||
MP1_BASE__INST3_SEG4 = 0
|
||||
MP1_BASE__INST3_SEG5 = 0
|
||||
MP1_BASE__INST4_SEG0 = 0
|
||||
MP1_BASE__INST4_SEG1 = 0
|
||||
MP1_BASE__INST4_SEG2 = 0
|
||||
MP1_BASE__INST4_SEG3 = 0
|
||||
MP1_BASE__INST4_SEG4 = 0
|
||||
MP1_BASE__INST4_SEG5 = 0
|
||||
MP1_BASE__INST5_SEG0 = 0
|
||||
MP1_BASE__INST5_SEG1 = 0
|
||||
MP1_BASE__INST5_SEG2 = 0
|
||||
MP1_BASE__INST5_SEG3 = 0
|
||||
MP1_BASE__INST5_SEG4 = 0
|
||||
MP1_BASE__INST5_SEG5 = 0
|
||||
NBIO_BASE__INST0_SEG0 = 0x00000000
|
||||
NBIO_BASE__INST0_SEG1 = 0x00000014
|
||||
NBIO_BASE__INST0_SEG2 = 0x00000D20
|
||||
NBIO_BASE__INST0_SEG3 = 0x00010400
|
||||
NBIO_BASE__INST0_SEG4 = 0
|
||||
NBIO_BASE__INST0_SEG5 = 0
|
||||
NBIO_BASE__INST1_SEG0 = 0
|
||||
NBIO_BASE__INST1_SEG1 = 0
|
||||
NBIO_BASE__INST1_SEG2 = 0
|
||||
NBIO_BASE__INST1_SEG3 = 0
|
||||
NBIO_BASE__INST1_SEG4 = 0
|
||||
NBIO_BASE__INST1_SEG5 = 0
|
||||
NBIO_BASE__INST2_SEG0 = 0
|
||||
NBIO_BASE__INST2_SEG1 = 0
|
||||
NBIO_BASE__INST2_SEG2 = 0
|
||||
NBIO_BASE__INST2_SEG3 = 0
|
||||
NBIO_BASE__INST2_SEG4 = 0
|
||||
NBIO_BASE__INST2_SEG5 = 0
|
||||
NBIO_BASE__INST3_SEG0 = 0
|
||||
NBIO_BASE__INST3_SEG1 = 0
|
||||
NBIO_BASE__INST3_SEG2 = 0
|
||||
NBIO_BASE__INST3_SEG3 = 0
|
||||
NBIO_BASE__INST3_SEG4 = 0
|
||||
NBIO_BASE__INST3_SEG5 = 0
|
||||
NBIO_BASE__INST4_SEG0 = 0
|
||||
NBIO_BASE__INST4_SEG1 = 0
|
||||
NBIO_BASE__INST4_SEG2 = 0
|
||||
NBIO_BASE__INST4_SEG3 = 0
|
||||
NBIO_BASE__INST4_SEG4 = 0
|
||||
NBIO_BASE__INST4_SEG5 = 0
|
||||
NBIO_BASE__INST5_SEG0 = 0
|
||||
NBIO_BASE__INST5_SEG1 = 0
|
||||
NBIO_BASE__INST5_SEG2 = 0
|
||||
NBIO_BASE__INST5_SEG3 = 0
|
||||
NBIO_BASE__INST5_SEG4 = 0
|
||||
NBIO_BASE__INST5_SEG5 = 0
|
||||
OSSSYS_BASE__INST0_SEG0 = 0x000010A0
|
||||
OSSSYS_BASE__INST0_SEG1 = 0
|
||||
OSSSYS_BASE__INST0_SEG2 = 0
|
||||
OSSSYS_BASE__INST0_SEG3 = 0
|
||||
OSSSYS_BASE__INST0_SEG4 = 0
|
||||
OSSSYS_BASE__INST0_SEG5 = 0
|
||||
OSSSYS_BASE__INST1_SEG0 = 0
|
||||
OSSSYS_BASE__INST1_SEG1 = 0
|
||||
OSSSYS_BASE__INST1_SEG2 = 0
|
||||
OSSSYS_BASE__INST1_SEG3 = 0
|
||||
OSSSYS_BASE__INST1_SEG4 = 0
|
||||
OSSSYS_BASE__INST1_SEG5 = 0
|
||||
OSSSYS_BASE__INST2_SEG0 = 0
|
||||
OSSSYS_BASE__INST2_SEG1 = 0
|
||||
OSSSYS_BASE__INST2_SEG2 = 0
|
||||
OSSSYS_BASE__INST2_SEG3 = 0
|
||||
OSSSYS_BASE__INST2_SEG4 = 0
|
||||
OSSSYS_BASE__INST2_SEG5 = 0
|
||||
OSSSYS_BASE__INST3_SEG0 = 0
|
||||
OSSSYS_BASE__INST3_SEG1 = 0
|
||||
OSSSYS_BASE__INST3_SEG2 = 0
|
||||
OSSSYS_BASE__INST3_SEG3 = 0
|
||||
OSSSYS_BASE__INST3_SEG4 = 0
|
||||
OSSSYS_BASE__INST3_SEG5 = 0
|
||||
OSSSYS_BASE__INST4_SEG0 = 0
|
||||
OSSSYS_BASE__INST4_SEG1 = 0
|
||||
OSSSYS_BASE__INST4_SEG2 = 0
|
||||
OSSSYS_BASE__INST4_SEG3 = 0
|
||||
OSSSYS_BASE__INST4_SEG4 = 0
|
||||
OSSSYS_BASE__INST4_SEG5 = 0
|
||||
OSSSYS_BASE__INST5_SEG0 = 0
|
||||
OSSSYS_BASE__INST5_SEG1 = 0
|
||||
OSSSYS_BASE__INST5_SEG2 = 0
|
||||
OSSSYS_BASE__INST5_SEG3 = 0
|
||||
OSSSYS_BASE__INST5_SEG4 = 0
|
||||
OSSSYS_BASE__INST5_SEG5 = 0
|
||||
SDMA0_BASE__INST0_SEG0 = 0x00001260
|
||||
SDMA0_BASE__INST0_SEG1 = 0
|
||||
SDMA0_BASE__INST0_SEG2 = 0
|
||||
SDMA0_BASE__INST0_SEG3 = 0
|
||||
SDMA0_BASE__INST0_SEG4 = 0
|
||||
SDMA0_BASE__INST0_SEG5 = 0
|
||||
SDMA0_BASE__INST1_SEG0 = 0
|
||||
SDMA0_BASE__INST1_SEG1 = 0
|
||||
SDMA0_BASE__INST1_SEG2 = 0
|
||||
SDMA0_BASE__INST1_SEG3 = 0
|
||||
SDMA0_BASE__INST1_SEG4 = 0
|
||||
SDMA0_BASE__INST1_SEG5 = 0
|
||||
SDMA0_BASE__INST2_SEG0 = 0
|
||||
SDMA0_BASE__INST2_SEG1 = 0
|
||||
SDMA0_BASE__INST2_SEG2 = 0
|
||||
SDMA0_BASE__INST2_SEG3 = 0
|
||||
SDMA0_BASE__INST2_SEG4 = 0
|
||||
SDMA0_BASE__INST2_SEG5 = 0
|
||||
SDMA0_BASE__INST3_SEG0 = 0
|
||||
SDMA0_BASE__INST3_SEG1 = 0
|
||||
SDMA0_BASE__INST3_SEG2 = 0
|
||||
SDMA0_BASE__INST3_SEG3 = 0
|
||||
SDMA0_BASE__INST3_SEG4 = 0
|
||||
SDMA0_BASE__INST3_SEG5 = 0
|
||||
SDMA0_BASE__INST4_SEG0 = 0
|
||||
SDMA0_BASE__INST4_SEG1 = 0
|
||||
SDMA0_BASE__INST4_SEG2 = 0
|
||||
SDMA0_BASE__INST4_SEG3 = 0
|
||||
SDMA0_BASE__INST4_SEG4 = 0
|
||||
SDMA0_BASE__INST4_SEG5 = 0
|
||||
SDMA0_BASE__INST5_SEG0 = 0
|
||||
SDMA0_BASE__INST5_SEG1 = 0
|
||||
SDMA0_BASE__INST5_SEG2 = 0
|
||||
SDMA0_BASE__INST5_SEG3 = 0
|
||||
SDMA0_BASE__INST5_SEG4 = 0
|
||||
SDMA0_BASE__INST5_SEG5 = 0
|
||||
SDMA1_BASE__INST0_SEG0 = 0x00001860
|
||||
SDMA1_BASE__INST0_SEG1 = 0
|
||||
SDMA1_BASE__INST0_SEG2 = 0
|
||||
SDMA1_BASE__INST0_SEG3 = 0
|
||||
SDMA1_BASE__INST0_SEG4 = 0
|
||||
SDMA1_BASE__INST0_SEG5 = 0
|
||||
SDMA1_BASE__INST1_SEG0 = 0
|
||||
SDMA1_BASE__INST1_SEG1 = 0
|
||||
SDMA1_BASE__INST1_SEG2 = 0
|
||||
SDMA1_BASE__INST1_SEG3 = 0
|
||||
SDMA1_BASE__INST1_SEG4 = 0
|
||||
SDMA1_BASE__INST1_SEG5 = 0
|
||||
SDMA1_BASE__INST2_SEG0 = 0
|
||||
SDMA1_BASE__INST2_SEG1 = 0
|
||||
SDMA1_BASE__INST2_SEG2 = 0
|
||||
SDMA1_BASE__INST2_SEG3 = 0
|
||||
SDMA1_BASE__INST2_SEG4 = 0
|
||||
SDMA1_BASE__INST2_SEG5 = 0
|
||||
SDMA1_BASE__INST3_SEG0 = 0
|
||||
SDMA1_BASE__INST3_SEG1 = 0
|
||||
SDMA1_BASE__INST3_SEG2 = 0
|
||||
SDMA1_BASE__INST3_SEG3 = 0
|
||||
SDMA1_BASE__INST3_SEG4 = 0
|
||||
SDMA1_BASE__INST3_SEG5 = 0
|
||||
SDMA1_BASE__INST4_SEG0 = 0
|
||||
SDMA1_BASE__INST4_SEG1 = 0
|
||||
SDMA1_BASE__INST4_SEG2 = 0
|
||||
SDMA1_BASE__INST4_SEG3 = 0
|
||||
SDMA1_BASE__INST4_SEG4 = 0
|
||||
SDMA1_BASE__INST4_SEG5 = 0
|
||||
SDMA1_BASE__INST5_SEG0 = 0
|
||||
SDMA1_BASE__INST5_SEG1 = 0
|
||||
SDMA1_BASE__INST5_SEG2 = 0
|
||||
SDMA1_BASE__INST5_SEG3 = 0
|
||||
SDMA1_BASE__INST5_SEG4 = 0
|
||||
SDMA1_BASE__INST5_SEG5 = 0
|
||||
SMUIO_BASE__INST0_SEG0 = 0x00016800
|
||||
SMUIO_BASE__INST0_SEG1 = 0x00016A00
|
||||
SMUIO_BASE__INST0_SEG2 = 0
|
||||
SMUIO_BASE__INST0_SEG3 = 0
|
||||
SMUIO_BASE__INST0_SEG4 = 0
|
||||
SMUIO_BASE__INST0_SEG5 = 0
|
||||
SMUIO_BASE__INST1_SEG0 = 0
|
||||
SMUIO_BASE__INST1_SEG1 = 0
|
||||
SMUIO_BASE__INST1_SEG2 = 0
|
||||
SMUIO_BASE__INST1_SEG3 = 0
|
||||
SMUIO_BASE__INST1_SEG4 = 0
|
||||
SMUIO_BASE__INST1_SEG5 = 0
|
||||
SMUIO_BASE__INST2_SEG0 = 0
|
||||
SMUIO_BASE__INST2_SEG1 = 0
|
||||
SMUIO_BASE__INST2_SEG2 = 0
|
||||
SMUIO_BASE__INST2_SEG3 = 0
|
||||
SMUIO_BASE__INST2_SEG4 = 0
|
||||
SMUIO_BASE__INST2_SEG5 = 0
|
||||
SMUIO_BASE__INST3_SEG0 = 0
|
||||
SMUIO_BASE__INST3_SEG1 = 0
|
||||
SMUIO_BASE__INST3_SEG2 = 0
|
||||
SMUIO_BASE__INST3_SEG3 = 0
|
||||
SMUIO_BASE__INST3_SEG4 = 0
|
||||
SMUIO_BASE__INST3_SEG5 = 0
|
||||
SMUIO_BASE__INST4_SEG0 = 0
|
||||
SMUIO_BASE__INST4_SEG1 = 0
|
||||
SMUIO_BASE__INST4_SEG2 = 0
|
||||
SMUIO_BASE__INST4_SEG3 = 0
|
||||
SMUIO_BASE__INST4_SEG4 = 0
|
||||
SMUIO_BASE__INST4_SEG5 = 0
|
||||
SMUIO_BASE__INST5_SEG0 = 0
|
||||
SMUIO_BASE__INST5_SEG1 = 0
|
||||
SMUIO_BASE__INST5_SEG2 = 0
|
||||
SMUIO_BASE__INST5_SEG3 = 0
|
||||
SMUIO_BASE__INST5_SEG4 = 0
|
||||
SMUIO_BASE__INST5_SEG5 = 0
|
||||
THM_BASE__INST0_SEG0 = 0x00016600
|
||||
THM_BASE__INST0_SEG1 = 0
|
||||
THM_BASE__INST0_SEG2 = 0
|
||||
THM_BASE__INST0_SEG3 = 0
|
||||
THM_BASE__INST0_SEG4 = 0
|
||||
THM_BASE__INST0_SEG5 = 0
|
||||
THM_BASE__INST1_SEG0 = 0
|
||||
THM_BASE__INST1_SEG1 = 0
|
||||
THM_BASE__INST1_SEG2 = 0
|
||||
THM_BASE__INST1_SEG3 = 0
|
||||
THM_BASE__INST1_SEG4 = 0
|
||||
THM_BASE__INST1_SEG5 = 0
|
||||
THM_BASE__INST2_SEG0 = 0
|
||||
THM_BASE__INST2_SEG1 = 0
|
||||
THM_BASE__INST2_SEG2 = 0
|
||||
THM_BASE__INST2_SEG3 = 0
|
||||
THM_BASE__INST2_SEG4 = 0
|
||||
THM_BASE__INST2_SEG5 = 0
|
||||
THM_BASE__INST3_SEG0 = 0
|
||||
THM_BASE__INST3_SEG1 = 0
|
||||
THM_BASE__INST3_SEG2 = 0
|
||||
THM_BASE__INST3_SEG3 = 0
|
||||
THM_BASE__INST3_SEG4 = 0
|
||||
THM_BASE__INST3_SEG5 = 0
|
||||
THM_BASE__INST4_SEG0 = 0
|
||||
THM_BASE__INST4_SEG1 = 0
|
||||
THM_BASE__INST4_SEG2 = 0
|
||||
THM_BASE__INST4_SEG3 = 0
|
||||
THM_BASE__INST4_SEG4 = 0
|
||||
THM_BASE__INST4_SEG5 = 0
|
||||
THM_BASE__INST5_SEG0 = 0
|
||||
THM_BASE__INST5_SEG1 = 0
|
||||
THM_BASE__INST5_SEG2 = 0
|
||||
THM_BASE__INST5_SEG3 = 0
|
||||
THM_BASE__INST5_SEG4 = 0
|
||||
THM_BASE__INST5_SEG5 = 0
|
||||
UMC_BASE__INST0_SEG0 = 0x00014000
|
||||
UMC_BASE__INST0_SEG1 = 0
|
||||
UMC_BASE__INST0_SEG2 = 0
|
||||
UMC_BASE__INST0_SEG3 = 0
|
||||
UMC_BASE__INST0_SEG4 = 0
|
||||
UMC_BASE__INST0_SEG5 = 0
|
||||
UMC_BASE__INST1_SEG0 = 0
|
||||
UMC_BASE__INST1_SEG1 = 0
|
||||
UMC_BASE__INST1_SEG2 = 0
|
||||
UMC_BASE__INST1_SEG3 = 0
|
||||
UMC_BASE__INST1_SEG4 = 0
|
||||
UMC_BASE__INST1_SEG5 = 0
|
||||
UMC_BASE__INST2_SEG0 = 0
|
||||
UMC_BASE__INST2_SEG1 = 0
|
||||
UMC_BASE__INST2_SEG2 = 0
|
||||
UMC_BASE__INST2_SEG3 = 0
|
||||
UMC_BASE__INST2_SEG4 = 0
|
||||
UMC_BASE__INST2_SEG5 = 0
|
||||
UMC_BASE__INST3_SEG0 = 0
|
||||
UMC_BASE__INST3_SEG1 = 0
|
||||
UMC_BASE__INST3_SEG2 = 0
|
||||
UMC_BASE__INST3_SEG3 = 0
|
||||
UMC_BASE__INST3_SEG4 = 0
|
||||
UMC_BASE__INST3_SEG5 = 0
|
||||
UMC_BASE__INST4_SEG0 = 0
|
||||
UMC_BASE__INST4_SEG1 = 0
|
||||
UMC_BASE__INST4_SEG2 = 0
|
||||
UMC_BASE__INST4_SEG3 = 0
|
||||
UMC_BASE__INST4_SEG4 = 0
|
||||
UMC_BASE__INST4_SEG5 = 0
|
||||
UMC_BASE__INST5_SEG0 = 0
|
||||
UMC_BASE__INST5_SEG1 = 0
|
||||
UMC_BASE__INST5_SEG2 = 0
|
||||
UMC_BASE__INST5_SEG3 = 0
|
||||
UMC_BASE__INST5_SEG4 = 0
|
||||
UMC_BASE__INST5_SEG5 = 0
|
||||
UVD_BASE__INST0_SEG0 = 0x00007800
|
||||
UVD_BASE__INST0_SEG1 = 0x00007E00
|
||||
UVD_BASE__INST0_SEG2 = 0
|
||||
UVD_BASE__INST0_SEG3 = 0
|
||||
UVD_BASE__INST0_SEG4 = 0
|
||||
UVD_BASE__INST0_SEG5 = 0
|
||||
UVD_BASE__INST1_SEG0 = 0
|
||||
UVD_BASE__INST1_SEG1 = 0x00009000
|
||||
UVD_BASE__INST1_SEG2 = 0
|
||||
UVD_BASE__INST1_SEG3 = 0
|
||||
UVD_BASE__INST1_SEG4 = 0
|
||||
UVD_BASE__INST1_SEG5 = 0
|
||||
UVD_BASE__INST2_SEG0 = 0
|
||||
UVD_BASE__INST2_SEG1 = 0
|
||||
UVD_BASE__INST2_SEG2 = 0
|
||||
UVD_BASE__INST2_SEG3 = 0
|
||||
UVD_BASE__INST2_SEG4 = 0
|
||||
UVD_BASE__INST2_SEG5 = 0
|
||||
UVD_BASE__INST3_SEG0 = 0
|
||||
UVD_BASE__INST3_SEG1 = 0
|
||||
UVD_BASE__INST3_SEG2 = 0
|
||||
UVD_BASE__INST3_SEG3 = 0
|
||||
UVD_BASE__INST3_SEG4 = 0
|
||||
UVD_BASE__INST3_SEG5 = 0
|
||||
UVD_BASE__INST4_SEG0 = 0
|
||||
UVD_BASE__INST4_SEG1 = 0
|
||||
UVD_BASE__INST4_SEG2 = 0
|
||||
UVD_BASE__INST4_SEG3 = 0
|
||||
UVD_BASE__INST4_SEG4 = 0
|
||||
UVD_BASE__INST4_SEG5 = 0
|
||||
UVD_BASE__INST5_SEG0 = 0
|
||||
UVD_BASE__INST5_SEG1 = 0
|
||||
UVD_BASE__INST5_SEG2 = 0
|
||||
UVD_BASE__INST5_SEG3 = 0
|
||||
UVD_BASE__INST5_SEG4 = 0
|
||||
UVD_BASE__INST5_SEG5 = 0
|
||||
VCE_BASE__INST0_SEG0 = 0x00008800
|
||||
VCE_BASE__INST0_SEG1 = 0
|
||||
VCE_BASE__INST0_SEG2 = 0
|
||||
VCE_BASE__INST0_SEG3 = 0
|
||||
VCE_BASE__INST0_SEG4 = 0
|
||||
VCE_BASE__INST0_SEG5 = 0
|
||||
VCE_BASE__INST1_SEG0 = 0
|
||||
VCE_BASE__INST1_SEG1 = 0
|
||||
VCE_BASE__INST1_SEG2 = 0
|
||||
VCE_BASE__INST1_SEG3 = 0
|
||||
VCE_BASE__INST1_SEG4 = 0
|
||||
VCE_BASE__INST1_SEG5 = 0
|
||||
VCE_BASE__INST2_SEG0 = 0
|
||||
VCE_BASE__INST2_SEG1 = 0
|
||||
VCE_BASE__INST2_SEG2 = 0
|
||||
VCE_BASE__INST2_SEG3 = 0
|
||||
VCE_BASE__INST2_SEG4 = 0
|
||||
VCE_BASE__INST2_SEG5 = 0
|
||||
VCE_BASE__INST3_SEG0 = 0
|
||||
VCE_BASE__INST3_SEG1 = 0
|
||||
VCE_BASE__INST3_SEG2 = 0
|
||||
VCE_BASE__INST3_SEG3 = 0
|
||||
VCE_BASE__INST3_SEG4 = 0
|
||||
VCE_BASE__INST3_SEG5 = 0
|
||||
VCE_BASE__INST4_SEG0 = 0
|
||||
VCE_BASE__INST4_SEG1 = 0
|
||||
VCE_BASE__INST4_SEG2 = 0
|
||||
VCE_BASE__INST4_SEG3 = 0
|
||||
VCE_BASE__INST4_SEG4 = 0
|
||||
VCE_BASE__INST4_SEG5 = 0
|
||||
VCE_BASE__INST5_SEG0 = 0
|
||||
VCE_BASE__INST5_SEG1 = 0
|
||||
VCE_BASE__INST5_SEG2 = 0
|
||||
VCE_BASE__INST5_SEG3 = 0
|
||||
VCE_BASE__INST5_SEG4 = 0
|
||||
VCE_BASE__INST5_SEG5 = 0
|
||||
XDMA_BASE__INST0_SEG0 = 0x00003400
|
||||
XDMA_BASE__INST0_SEG1 = 0
|
||||
XDMA_BASE__INST0_SEG2 = 0
|
||||
XDMA_BASE__INST0_SEG3 = 0
|
||||
XDMA_BASE__INST0_SEG4 = 0
|
||||
XDMA_BASE__INST0_SEG5 = 0
|
||||
XDMA_BASE__INST1_SEG0 = 0
|
||||
XDMA_BASE__INST1_SEG1 = 0
|
||||
XDMA_BASE__INST1_SEG2 = 0
|
||||
XDMA_BASE__INST1_SEG3 = 0
|
||||
XDMA_BASE__INST1_SEG4 = 0
|
||||
XDMA_BASE__INST1_SEG5 = 0
|
||||
XDMA_BASE__INST2_SEG0 = 0
|
||||
XDMA_BASE__INST2_SEG1 = 0
|
||||
XDMA_BASE__INST2_SEG2 = 0
|
||||
XDMA_BASE__INST2_SEG3 = 0
|
||||
XDMA_BASE__INST2_SEG4 = 0
|
||||
XDMA_BASE__INST2_SEG5 = 0
|
||||
XDMA_BASE__INST3_SEG0 = 0
|
||||
XDMA_BASE__INST3_SEG1 = 0
|
||||
XDMA_BASE__INST3_SEG2 = 0
|
||||
XDMA_BASE__INST3_SEG3 = 0
|
||||
XDMA_BASE__INST3_SEG4 = 0
|
||||
XDMA_BASE__INST3_SEG5 = 0
|
||||
XDMA_BASE__INST4_SEG0 = 0
|
||||
XDMA_BASE__INST4_SEG1 = 0
|
||||
XDMA_BASE__INST4_SEG2 = 0
|
||||
XDMA_BASE__INST4_SEG3 = 0
|
||||
XDMA_BASE__INST4_SEG4 = 0
|
||||
XDMA_BASE__INST4_SEG5 = 0
|
||||
XDMA_BASE__INST5_SEG0 = 0
|
||||
XDMA_BASE__INST5_SEG1 = 0
|
||||
XDMA_BASE__INST5_SEG2 = 0
|
||||
XDMA_BASE__INST5_SEG3 = 0
|
||||
XDMA_BASE__INST5_SEG4 = 0
|
||||
XDMA_BASE__INST5_SEG5 = 0
|
||||
RSMU_BASE__INST0_SEG0 = 0x00012000
|
||||
RSMU_BASE__INST0_SEG1 = 0
|
||||
RSMU_BASE__INST0_SEG2 = 0
|
||||
RSMU_BASE__INST0_SEG3 = 0
|
||||
RSMU_BASE__INST0_SEG4 = 0
|
||||
RSMU_BASE__INST0_SEG5 = 0
|
||||
RSMU_BASE__INST1_SEG0 = 0
|
||||
RSMU_BASE__INST1_SEG1 = 0
|
||||
RSMU_BASE__INST1_SEG2 = 0
|
||||
RSMU_BASE__INST1_SEG3 = 0
|
||||
RSMU_BASE__INST1_SEG4 = 0
|
||||
RSMU_BASE__INST1_SEG5 = 0
|
||||
RSMU_BASE__INST2_SEG0 = 0
|
||||
RSMU_BASE__INST2_SEG1 = 0
|
||||
RSMU_BASE__INST2_SEG2 = 0
|
||||
RSMU_BASE__INST2_SEG3 = 0
|
||||
RSMU_BASE__INST2_SEG4 = 0
|
||||
RSMU_BASE__INST2_SEG5 = 0
|
||||
RSMU_BASE__INST3_SEG0 = 0
|
||||
RSMU_BASE__INST3_SEG1 = 0
|
||||
RSMU_BASE__INST3_SEG2 = 0
|
||||
RSMU_BASE__INST3_SEG3 = 0
|
||||
RSMU_BASE__INST3_SEG4 = 0
|
||||
RSMU_BASE__INST3_SEG5 = 0
|
||||
RSMU_BASE__INST4_SEG0 = 0
|
||||
RSMU_BASE__INST4_SEG1 = 0
|
||||
RSMU_BASE__INST4_SEG2 = 0
|
||||
RSMU_BASE__INST4_SEG3 = 0
|
||||
RSMU_BASE__INST4_SEG4 = 0
|
||||
RSMU_BASE__INST4_SEG5 = 0
|
||||
RSMU_BASE__INST5_SEG0 = 0
|
||||
RSMU_BASE__INST5_SEG1 = 0
|
||||
RSMU_BASE__INST5_SEG2 = 0
|
||||
RSMU_BASE__INST5_SEG3 = 0
|
||||
RSMU_BASE__INST5_SEG4 = 0
|
||||
RSMU_BASE__INST5_SEG5 = 0
|
||||
Reference in New Issue
Block a user