forked from IQ.Lvbs/IQ.Pilot
IQ.Pilot Release Commit @ 0798119
This commit is contained in:
IQ.Lvbs history cleanup
43
tinygrad_repo/tinygrad/runtime/autogen/nv_regs/__init__.py
Normal file
43
tinygrad_repo/tinygrad/runtime/autogen/nv_regs/__init__.py
Normal file
@@ -0,0 +1,43 @@
|
||||
import re, pathlib
|
||||
from tinygrad.runtime.autogen import load, nv_src
|
||||
|
||||
swref_path, hwref_path = "{}/src/common/inc/swref/published", "{}/kernel-open/nvidia-uvm/hwref"
|
||||
swref = {
|
||||
"dev_therm": ["gb202"], "dev_vm": ["tu102", "gh100"], **{k:["tu102"] for k in ["dev_fb", "dev_bus"]},
|
||||
**{k:["ga102"] for k in ["dev_gc6_island", "dev_gsp", "dev_riscv_pri", "dev_fbif_v4", "dev_falcon_second_pri", "dev_sec_pri"]},
|
||||
"dev_falcon_v4": ["ga102", "gh100"], "dev_fsp_pri": ["gh100"]
|
||||
}
|
||||
hwref = {"dev_mmu": ["tu102", "gh100"]}
|
||||
__all__ = ["nv_ref", *swref.keys(), *hwref.keys()]
|
||||
has_addendum = (("ga102", "dev_gc6_island"), ("ga102", "dev_falcon_v4"))
|
||||
|
||||
def __getattr__(nm):
|
||||
arch_map = {"tu102":"turing", "ga102":"ampere", "gh100":"hopper", "gb202":"blackwell"}
|
||||
regs_off = {'NV_PFALCON_FALCON': 0x0, 'NV_PGSP_FALCON': 0x0, 'NV_PSEC_FALCON': 0x0, 'NV_PRISCV_RISCV': 0x1000, 'NV_PGC6_AON': 0x0, 'NV_PFSP': 0x0,
|
||||
'NV_PGC6_BSI': 0x0, 'NV_PFALCON_FBIF': 0x600, 'NV_PFALCON2_FALCON': 0x1000, 'NV_PBUS': 0x0, 'NV_PFB': 0x0, 'NV_PMC': 0x0, 'NV_PGSP_QUEUE': 0x0,
|
||||
'NV_VIRTUAL_FUNCTION':0xb80000, "NV_THERM": 0x0}
|
||||
|
||||
def genreg(_, files, **kwargs):
|
||||
out = []
|
||||
for (file, arch) in [(file, "" if (a:=file.split('/')[-2]) == "published" else a) for file in files]:
|
||||
lines = ((p:=pathlib.Path(file)).read_text() + ((p.parent/f"{nm}_addendum.h").read_text() if (arch, nm) in has_addendum else "")).splitlines()
|
||||
def extract(pat): return (m.groups() for l in lines if (m:=re.match(pat, l)))
|
||||
bitfields = {k:f"({lo}, {hi})" for k,hi,lo in extract(r'#define\s+(\w+)\s+([0-9\+\-\*\(\)]+):([0-9\+\-\*\(\)]+)')}
|
||||
regs = {}
|
||||
for l in lines:
|
||||
def off(name): return next((o for p,o in regs_off.items() if name.startswith(p)), None)
|
||||
def fields(name): return "{" + ", ".join(f"{k[len(name)+1:].lower()!r}: {v}" for k, v in bitfields.items() if k.startswith(name+"_")) + "}"
|
||||
if (m:=re.match(r'#define\s+(\w+)\s*\(\s*(\w+)\s*\)\s*(.+)', l)) and off(m.group(1)) is not None:
|
||||
regs[m.group(1)] = f"(0x{off(m.group(1)):X}, lambda {m.group(2)}: " + re.sub(r' */\*.*\*/', '', m.group(3)) + f", {fields(m.group(1))})"
|
||||
elif (m:=re.match(r'#define\s+(\w+)\s+([0-9A-Fa-fx]+)(?![^\n]*:)', l)):
|
||||
if off(m.group(1)) is None or any(m.group(1).startswith(r+'_') for r in regs): regs[m.group(1)] = m.group(2)
|
||||
else: regs[m.group(1)] = f"(0x{off(m.group(1)):X}, {m.group(2)}, {fields(m.group(1))})"
|
||||
elif (m:=re.match(r'#define\s+(\w+)\s*/\* ----G \*/\s*$', l)): regs[m.group(1)] = f"(None, None, {fields(m.group(1))})" # groups (for MMU)
|
||||
out.extend([f"{arch or 'regs'} = {{", *[f" {k!r}: {v}," for k,v in regs.items()], "}"])
|
||||
return "\n".join(out)
|
||||
|
||||
if nm == "nv_ref": return load(f"nv_regs/{nm}", [f"{swref_path}/{nm}.h"], gen=genreg, srcs=nv_src["nv_570"])
|
||||
if nm in __all__:
|
||||
path, arches = (swref_path, swref[nm]) if nm in swref else (hwref_path, hwref[nm])
|
||||
return load(f"nv_regs/{nm}", [f"{path}/{arch_map[arch]}/{arch}/{nm}.h" for arch in arches], gen=genreg, srcs=nv_src["nv_570"])
|
||||
raise AttributeError(f"no such autogen: {nm}")
|
||||
36
tinygrad_repo/tinygrad/runtime/autogen/nv_regs/dev_bus.py
Normal file
36
tinygrad_repo/tinygrad/runtime/autogen/nv_regs/dev_bus.py
Normal file
@@ -0,0 +1,36 @@
|
||||
tu102 = {
|
||||
'NV_PBUS_VBIOS_SCRATCH': (0x0, lambda i: (0x00001400+(i)*4), {}),
|
||||
'NV_PBUS_SW_SCRATCH': (0x0, lambda i: (0x00001400+(i)*4), {}),
|
||||
'NV_PBUS_IFR_FMT_FIXED0': (0x0, 0x00000000, {'signature': (0, 31)}),
|
||||
'NV_PBUS_IFR_FMT_FIXED0_SIGNATURE_VALUE': 0x4947564E,
|
||||
'NV_PBUS_IFR_FMT_FIXED1': (0x0, 0x00000004, {'versionsw': (8, 15), 'fixed_data_size': (16, 30)}),
|
||||
'NV_PBUS_IFR_FMT_FIXED2': (0x0, 0x00000008, {'total_data_size': (0, 19)}),
|
||||
'NV_PBUS_BAR1_BLOCK': (0x0, 0x00001704, {'map': (0, 29), 'ptr': (0, 27), 'target': (28, 29), 'mode': (31, 31)}),
|
||||
'NV_PBUS_BAR1_BLOCK_PTR_0': 0x00000000,
|
||||
'NV_PBUS_BAR1_BLOCK_TARGET_VID_MEM': 0x00000000,
|
||||
'NV_PBUS_BAR1_BLOCK_TARGET_SYS_MEM_COHERENT': 0x00000002,
|
||||
'NV_PBUS_BAR1_BLOCK_TARGET_SYS_MEM_NONCOHERENT': 0x00000003,
|
||||
'NV_PBUS_BAR1_BLOCK_MODE_PHYSICAL': 0x00000000,
|
||||
'NV_PBUS_BAR1_BLOCK_MODE_VIRTUAL': 0x00000001,
|
||||
'NV_PBUS_BAR1_BLOCK_PTR_SHIFT': 12,
|
||||
'NV_PBUS_BAR2_BLOCK': (0x0, 0x00001714, {'map': (0, 29), 'ptr': (0, 27), 'target': (28, 29), 'debug_cya': (30, 30), 'mode': (31, 31), 'reserved': (30, 30)}),
|
||||
'NV_PBUS_BAR2_BLOCK_PTR_0': 0x00000000,
|
||||
'NV_PBUS_BAR2_BLOCK_TARGET_VID_MEM': 0x00000000,
|
||||
'NV_PBUS_BAR2_BLOCK_TARGET_SYS_MEM_COHERENT': 0x00000002,
|
||||
'NV_PBUS_BAR2_BLOCK_TARGET_SYS_MEM_NONCOHERENT': 0x00000003,
|
||||
'NV_PBUS_BAR2_BLOCK_DEBUG_CYA_OFF': 0x00000001,
|
||||
'NV_PBUS_BAR2_BLOCK_DEBUG_CYA_ON': 0x00000000,
|
||||
'NV_PBUS_BAR2_BLOCK_DEBUG_CYA_INIT': 0x00000001,
|
||||
'NV_PBUS_BAR2_BLOCK_MODE_PHYSICAL': 0x00000000,
|
||||
'NV_PBUS_BAR2_BLOCK_MODE_VIRTUAL': 0x00000001,
|
||||
'NV_PBUS_BAR2_BLOCK_PTR_SHIFT': 12,
|
||||
'NV_PBUS_BAR2_BLOCK_RESERVED_DEFAULT': 0x00000001,
|
||||
'NV_PBUS_BIND_STATUS_BAR1_PENDING_EMPTY': (0x0, 0x00000000, {}),
|
||||
'NV_PBUS_BIND_STATUS_BAR1_PENDING_BUSY': (0x0, 0x00000001, {}),
|
||||
'NV_PBUS_BIND_STATUS_BAR1_OUTSTANDING_FALSE': (0x0, 0x00000000, {}),
|
||||
'NV_PBUS_BIND_STATUS_BAR1_OUTSTANDING_TRUE': (0x0, 0x00000001, {}),
|
||||
'NV_PBUS_BIND_STATUS_BAR2_PENDING_EMPTY': (0x0, 0x00000000, {}),
|
||||
'NV_PBUS_BIND_STATUS_BAR2_PENDING_BUSY': (0x0, 0x00000001, {}),
|
||||
'NV_PBUS_BIND_STATUS_BAR2_OUTSTANDING_FALSE': (0x0, 0x00000000, {}),
|
||||
'NV_PBUS_BIND_STATUS_BAR2_OUTSTANDING_TRUE': (0x0, 0x00000001, {}),
|
||||
}
|
||||
@@ -0,0 +1,10 @@
|
||||
ga102 = {
|
||||
'NV_FALCON2_GSP_BASE': 0x00111000,
|
||||
'NV_FALCON2_NVDEC0_BASE': 0x00849c00,
|
||||
'NV_FALCON2_SEC_BASE': 0x00841000,
|
||||
'NV_PFALCON2_FALCON_MOD_SEL': (0x1000, 0x00000180, {'algo': (0, 7)}),
|
||||
'NV_PFALCON2_FALCON_MOD_SEL_ALGO_RSA3K': 0x00000001,
|
||||
'NV_PFALCON2_FALCON_BROM_CURR_UCODE_ID': (0x1000, 0x00000198, {'val': (0, 7)}),
|
||||
'NV_PFALCON2_FALCON_BROM_ENGIDMASK': (0x1000, 0x0000019c, {}),
|
||||
'NV_PFALCON2_FALCON_BROM_PARAADDR': (0x1000, lambda i: (0x00000210+(i)*4), {}),
|
||||
}
|
||||
113
tinygrad_repo/tinygrad/runtime/autogen/nv_regs/dev_falcon_v4.py
Normal file
113
tinygrad_repo/tinygrad/runtime/autogen/nv_regs/dev_falcon_v4.py
Normal file
@@ -0,0 +1,113 @@
|
||||
ga102 = {
|
||||
'NV_PFALCON_FALCON_IRQSCLR': (0x0, 0x00000004, {'halt': (4, 4), 'swgen0': (6, 6)}),
|
||||
'NV_PFALCON_FALCON_IRQSCLR_HALT_SET': 0x00000001,
|
||||
'NV_PFALCON_FALCON_IRQSCLR_SWGEN0_SET': 0x00000001,
|
||||
'NV_PFALCON_FALCON_IRQSTAT': (0x0, 0x00000008, {'halt': (4, 4), 'swgen0': (6, 6)}),
|
||||
'NV_PFALCON_FALCON_IRQSTAT_HALT_TRUE': 0x00000001,
|
||||
'NV_PFALCON_FALCON_IRQSTAT_SWGEN0_TRUE': 0x00000001,
|
||||
'NV_PFALCON_FALCON_INTR_RETRIGGER': (0x0, lambda i: (0x000003e8+(i)*4), {'trigger': (0, 0)}),
|
||||
'NV_PFALCON_FALCON_INTR_RETRIGGER__SIZE_1': 2,
|
||||
'NV_PFALCON_FALCON_INTR_RETRIGGER_TRIGGER_TRUE': 0x00000001,
|
||||
'NV_PFALCON_FALCON_IRQMSET': (0x0, 0x00000010, {}),
|
||||
'NV_PFALCON_FALCON_IRQMCLR': (0x0, 0x00000014, {}),
|
||||
'NV_PFALCON_FALCON_IRQMASK': (0x0, 0x00000018, {}),
|
||||
'NV_PFALCON_FALCON_IRQDEST': (0x0, 0x0000001c, {}),
|
||||
'NV_PFALCON_FALCON_MAILBOX0': (0x0, 0x00000040, {}),
|
||||
'NV_PFALCON_FALCON_MAILBOX1': (0x0, 0x00000044, {}),
|
||||
'NV_PFALCON_FALCON_DMACTL': (0x0, 0x0000010c, {'require_ctx': (0, 0), 'dmem_scrubbing': (1, 1), 'imem_scrubbing': (2, 2)}),
|
||||
'NV_PFALCON_FALCON_DMACTL_REQUIRE_CTX_FALSE': 0x00000000,
|
||||
'NV_PFALCON_FALCON_DMACTL_DMEM_SCRUBBING_DONE': 0x00000000,
|
||||
'NV_PFALCON_FALCON_DMACTL_IMEM_SCRUBBING_DONE': 0x00000000,
|
||||
'NV_PFALCON_FALCON_DMATRFBASE': (0x0, 0x00000110, {'base': (0, 31)}),
|
||||
'NV_PFALCON_FALCON_DMATRFMOFFS': (0x0, 0x00000114, {'offs': (0, 23)}),
|
||||
'NV_PFALCON_FALCON_DMATRFCMD': (0x0, 0x00000118, {'full': (0, 0), 'idle': (1, 1), 'sec': (2, 3), 'imem': (4, 4), 'write': (5, 5), 'size': (8, 10), 'ctxdma': (12, 14), 'set_dmtag': (16, 16)}),
|
||||
'NV_PFALCON_FALCON_DMATRFCMD_FULL_TRUE': 0x00000001,
|
||||
'NV_PFALCON_FALCON_DMATRFCMD_FULL_FALSE': 0x00000000,
|
||||
'NV_PFALCON_FALCON_DMATRFCMD_IDLE_TRUE': 0x00000001,
|
||||
'NV_PFALCON_FALCON_DMATRFCMD_IDLE_FALSE': 0x00000000,
|
||||
'NV_PFALCON_FALCON_DMATRFCMD_IMEM_TRUE': 0x00000001,
|
||||
'NV_PFALCON_FALCON_DMATRFCMD_IMEM_FALSE': 0x00000000,
|
||||
'NV_PFALCON_FALCON_DMATRFCMD_WRITE_TRUE': 0x00000001,
|
||||
'NV_PFALCON_FALCON_DMATRFCMD_WRITE_FALSE': 0x00000000,
|
||||
'NV_PFALCON_FALCON_DMATRFCMD_SIZE_256B': 0x00000006,
|
||||
'NV_PFALCON_FALCON_DMATRFCMD_SET_DMTAG_TRUE': 0x00000001,
|
||||
'NV_PFALCON_FALCON_DMATRFFBOFFS': (0x0, 0x0000011c, {'offs': (0, 31)}),
|
||||
'NV_PFALCON_FALCON_DMATRFBASE1': (0x0, 0x00000128, {'base': (0, 8)}),
|
||||
'NV_PFALCON_FALCON_IMEMC': (0x0, lambda i: (0x00000180+(i)*16), {'offs': (2, 7), 'blk': (8, 23), 'aincw': (24, 24), 'secure': (28, 28)}),
|
||||
'NV_PFALCON_FALCON_IMEMC_AINCW_TRUE': 0x00000001,
|
||||
'NV_PFALCON_FALCON_IMEMC_AINCW_FALSE': 0x00000000,
|
||||
'NV_PFALCON_FALCON_IMEMD': (0x0, lambda i: (0x00000184+(i)*16), {'data': (0, 31)}),
|
||||
'NV_PFALCON_FALCON_IMEMT': (0x0, lambda i: (0x00000188+(i)*16), {'tag': (0, 15)}),
|
||||
'NV_PFALCON_FALCON_DMEMC': (0x0, lambda i: (0x000001c0+(i)*8), {'offs': (2, 7), 'blk': (8, 23), 'aincw': (24, 24)}),
|
||||
'NV_PFALCON_FALCON_DMEMC_AINCW_TRUE': 0x00000001,
|
||||
'NV_PFALCON_FALCON_DMEMC_AINCW_FALSE': 0x00000000,
|
||||
'NV_PFALCON_FALCON_DMEMD': (0x0, lambda i: (0x000001c4+(i)*8), {'data': (0, 31)}),
|
||||
'NV_PFALCON_FALCON_HWCFG': (0x0, 0x00000108, {'imem_size': (0, 8)}),
|
||||
'NV_PFALCON_FALCON_HWCFG2': (0x0, 0x000000f4, {'riscv': (10, 10), 'mem_scrubbing': (12, 12), 'reset_ready': (31, 31)}),
|
||||
'NV_PFALCON_FALCON_HWCFG2_RISCV_ENABLE': 0x00000001,
|
||||
'NV_PFALCON_FALCON_HWCFG2_MEM_SCRUBBING_DONE': 0x00000000,
|
||||
'NV_PFALCON_FALCON_OS': (0x0, 0x00000080, {}),
|
||||
'NV_PFALCON_FALCON_RM': (0x0, 0x00000084, {}),
|
||||
'NV_PFALCON_FALCON_DEBUGINFO': (0x0, 0x00000094, {}),
|
||||
'NV_PFALCON_FALCON_CPUCTL': (0x0, 0x00000100, {'startcpu': (1, 1), 'halted': (4, 4), 'alias_en': (6, 6), 'alias_startcpu': (1, 1)}),
|
||||
'NV_PFALCON_FALCON_CPUCTL_STARTCPU_TRUE': 0x00000001,
|
||||
'NV_PFALCON_FALCON_CPUCTL_STARTCPU_FALSE': 0x00000000,
|
||||
'NV_PFALCON_FALCON_CPUCTL_HALTED_TRUE': 0x00000001,
|
||||
'NV_PFALCON_FALCON_CPUCTL_ALIAS_EN_TRUE': 0x00000001,
|
||||
'NV_PFALCON_FALCON_CPUCTL_ALIAS_EN_FALSE': 0x00000000,
|
||||
'NV_PFALCON_FALCON_CPUCTL_ALIAS': 0x00000130,
|
||||
'NV_PFALCON_FALCON_CPUCTL_ALIAS_STARTCPU_TRUE': 0x00000001,
|
||||
'NV_PFALCON_FALCON_CPUCTL_ALIAS_STARTCPU_FALSE': 0x00000000,
|
||||
'NV_PFALCON_FALCON_BOOTVEC': (0x0, 0x00000104, {}),
|
||||
'NV_PFALCON_FALCON_HWCFG2_RESET_READY_TRUE': 0x00000001,
|
||||
'NV_PFALCON_FALCON_HWCFG2_RESET_READY_FALSE': 0x00000000,
|
||||
}
|
||||
gh100 = {
|
||||
'NV_PFALCON_FALCON_MAILBOX0': (0x0, 0x00000040, {'data': (0, 31)}),
|
||||
'NV_PFALCON_FALCON_MAILBOX0_DATA_INIT': 0x00000000,
|
||||
'NV_PFALCON_FALCON_MAILBOX1': (0x0, 0x00000044, {'data': (0, 31)}),
|
||||
'NV_PFALCON_FALCON_MAILBOX1_DATA_INIT': 0x00000000,
|
||||
'NV_PFALCON_FALCON_OS': (0x0, 0x00000080, {'version': (0, 31)}),
|
||||
'NV_PFALCON_FALCON_OS__DEVICE_MAP': 0x00000013,
|
||||
'NV_PFALCON_FALCON_OS_VERSION_INIT': 0x00000000,
|
||||
'NV_PFALCON_FALCON_HWCFG2': (0x0, 0x000000f4, {'sha': (0, 0), 'bmem': (1, 1), 'pkcboot': (2, 2), 'dbgmode': (3, 3), 'kmem': (4, 4), 'hscode_revocation': (5, 5), 'strap_fun': (6, 6), 'vhr': (7, 7), 'hs': (8, 8), 'securebus': (9, 9), 'riscv': (10, 10), 'riscv_pl3_disable': (11, 11), 'mem_scrubbing': (12, 12), 'riscv_br_priv_lockdown': (13, 13), 'boot_from_hs': (14, 14), 'riscv_br_adpair': (15, 15), 'scp': (16, 16), 'gdma': (17, 17), 'se_lite': (18, 18), 'prgn_rsvd_fuse': (24, 31)}),
|
||||
'NV_PFALCON_FALCON_HWCFG2_SHA_ENABLE': 0x00000001,
|
||||
'NV_PFALCON_FALCON_HWCFG2_SHA_DISABLE': 0x00000000,
|
||||
'NV_PFALCON_FALCON_HWCFG2_BMEM_ENABLE': 0x00000001,
|
||||
'NV_PFALCON_FALCON_HWCFG2_BMEM_DISABLE': 0x00000000,
|
||||
'NV_PFALCON_FALCON_HWCFG2_PKCBOOT_ENABLE': 0x00000001,
|
||||
'NV_PFALCON_FALCON_HWCFG2_PKCBOOT_DISABLE': 0x00000000,
|
||||
'NV_PFALCON_FALCON_HWCFG2_DBGMODE_ENABLE': 0x00000001,
|
||||
'NV_PFALCON_FALCON_HWCFG2_DBGMODE_DISABLE': 0x00000000,
|
||||
'NV_PFALCON_FALCON_HWCFG2_KMEM_ENABLE': 0x00000001,
|
||||
'NV_PFALCON_FALCON_HWCFG2_KMEM_DISABLE': 0x00000000,
|
||||
'NV_PFALCON_FALCON_HWCFG2_HSCODE_REVOCATION_ENABLE': 0x00000001,
|
||||
'NV_PFALCON_FALCON_HWCFG2_HSCODE_REVOCATION_DISABLE': 0x00000000,
|
||||
'NV_PFALCON_FALCON_HWCFG2_STRAP_FUN_ENABLE': 0x00000001,
|
||||
'NV_PFALCON_FALCON_HWCFG2_STRAP_FUN_DISABLE': 0x00000000,
|
||||
'NV_PFALCON_FALCON_HWCFG2_VHR_ENABLE': 0x00000001,
|
||||
'NV_PFALCON_FALCON_HWCFG2_VHR_DISABLE': 0x00000000,
|
||||
'NV_PFALCON_FALCON_HWCFG2_HS_ENABLE': 0x00000001,
|
||||
'NV_PFALCON_FALCON_HWCFG2_HS_DISABLE': 0x00000000,
|
||||
'NV_PFALCON_FALCON_HWCFG2_SECUREBUS_ENABLE': 0x00000001,
|
||||
'NV_PFALCON_FALCON_HWCFG2_SECUREBUS_DISABLE': 0x00000000,
|
||||
'NV_PFALCON_FALCON_HWCFG2_RISCV_ENABLE': 0x00000001,
|
||||
'NV_PFALCON_FALCON_HWCFG2_RISCV_DISABLE': 0x00000000,
|
||||
'NV_PFALCON_FALCON_HWCFG2_RISCV_PL3_DISABLE_TRUE': 0x00000001,
|
||||
'NV_PFALCON_FALCON_HWCFG2_RISCV_PL3_DISABLE_FALSE': 0x00000000,
|
||||
'NV_PFALCON_FALCON_HWCFG2_MEM_SCRUBBING_PENDING': 0x00000001,
|
||||
'NV_PFALCON_FALCON_HWCFG2_MEM_SCRUBBING_DONE': 0x00000000,
|
||||
'NV_PFALCON_FALCON_HWCFG2_RISCV_BR_PRIV_LOCKDOWN_LOCK': 0x00000001,
|
||||
'NV_PFALCON_FALCON_HWCFG2_RISCV_BR_PRIV_LOCKDOWN_UNLOCK': 0x00000000,
|
||||
'NV_PFALCON_FALCON_HWCFG2_BOOT_FROM_HS_TRUE': 0x00000001,
|
||||
'NV_PFALCON_FALCON_HWCFG2_BOOT_FROM_HS_FALSE': 0x00000000,
|
||||
'NV_PFALCON_FALCON_HWCFG2_RISCV_BR_ADPAIR_ENABLE': 0x00000001,
|
||||
'NV_PFALCON_FALCON_HWCFG2_RISCV_BR_ADPAIR_DISABLE': 0x00000000,
|
||||
'NV_PFALCON_FALCON_HWCFG2_SCP_ENABLE': 0x00000001,
|
||||
'NV_PFALCON_FALCON_HWCFG2_SCP_DISABLE': 0x00000000,
|
||||
'NV_PFALCON_FALCON_HWCFG2_GDMA_ENABLE': 0x00000001,
|
||||
'NV_PFALCON_FALCON_HWCFG2_GDMA_DISABLE': 0x00000000,
|
||||
'NV_PFALCON_FALCON_HWCFG2_SE_LITE_ENABLE': 0x00000001,
|
||||
'NV_PFALCON_FALCON_HWCFG2_SE_LITE_DISABLE': 0x00000000,
|
||||
'NV_PFALCON_FALCON_HWCFG2_PRGN_RSVD_FUSE_DEFAULT': 0x00000000,
|
||||
}
|
||||
27
tinygrad_repo/tinygrad/runtime/autogen/nv_regs/dev_fb.py
Normal file
27
tinygrad_repo/tinygrad/runtime/autogen/nv_regs/dev_fb.py
Normal file
@@ -0,0 +1,27 @@
|
||||
tu102 = {
|
||||
'NV_PFB_NISO_ACCESS_COUNTER_NOTIFY_BUFFER_INFO': (0x0, 0x00100A18, {'full': (0, 0)}),
|
||||
'NV_PFB_NISO_ACCESS_COUNTER_NOTIFY_BUFFER_INFO_FULL_FALSE': 0x0,
|
||||
'NV_PFB_NISO_ACCESS_COUNTER_NOTIFY_BUFFER_INFO_FULL_TRUE': 0x1,
|
||||
'NV_PFB_PRI_MMU_INT_VECTOR_FAULT_NOTIFY_REPLAYABLE': (0x0, 64, {}),
|
||||
'NV_PFB_PRI_MMU_INT_VECTOR_FAULT_NOTIFY_NON_REPLAYABLE': (0x0, 132, {}),
|
||||
'NV_PFB_PRI_MMU_WPR2_ADDR_LO': (0x0, 0x001FA824, {'val': (4, 31)}),
|
||||
'NV_PFB_PRI_MMU_WPR2_ADDR_LO_ALIGNMENT': 0x0000000c,
|
||||
'NV_PFB_PRI_MMU_WPR2_ADDR_HI': (0x0, 0x001FA828, {'val': (4, 31)}),
|
||||
'NV_PFB_PRI_MMU_WPR2_ADDR_HI_ALIGNMENT': 0x0000000c,
|
||||
'NV_PFB_PRI_MMU_FAULT_BUFFER_SIZE_VAL_RESET': (0x0, 0x00000000, {}),
|
||||
'NV_PFB_PRI_MMU_FAULT_BUFFER_SIZE_OVERFLOW_INTR_DISABLE': (0x0, 0x00000000, {}),
|
||||
'NV_PFB_PRI_MMU_FAULT_BUFFER_SIZE_OVERFLOW_INTR_ENABLE': (0x0, 0x00000001, {}),
|
||||
'NV_PFB_PRI_MMU_FAULT_BUFFER_SIZE_SET_DEFAULT_NO': (0x0, 0x00000000, {}),
|
||||
'NV_PFB_PRI_MMU_FAULT_BUFFER_SIZE_SET_DEFAULT_YES': (0x0, 0x00000001, {}),
|
||||
'NV_PFB_PRI_MMU_FAULT_BUFFER_SIZE_ENABLE_FALSE': (0x0, 0x00000000, {}),
|
||||
'NV_PFB_PRI_MMU_FAULT_BUFFER_SIZE_ENABLE_TRUE': (0x0, 0x00000001, {}),
|
||||
'NV_PFB_PRI_MMU_L2TLB_ECC_UNCORRECTED_ERR_COUNT': (0x0, 0x00100E78, {'total': (0, 15), 'unique': (16, 31)}),
|
||||
'NV_PFB_PRI_MMU_L2TLB_ECC_UNCORRECTED_ERR_COUNT_TOTAL_INIT': 0,
|
||||
'NV_PFB_PRI_MMU_L2TLB_ECC_UNCORRECTED_ERR_COUNT_UNIQUE_INIT': 0,
|
||||
'NV_PFB_PRI_MMU_HUBTLB_ECC_UNCORRECTED_ERR_COUNT': (0x0, 0x00100E8C, {'total': (0, 15), 'unique': (16, 31)}),
|
||||
'NV_PFB_PRI_MMU_HUBTLB_ECC_UNCORRECTED_ERR_COUNT_TOTAL_INIT': 0,
|
||||
'NV_PFB_PRI_MMU_HUBTLB_ECC_UNCORRECTED_ERR_COUNT_UNIQUE_INIT': 0,
|
||||
'NV_PFB_PRI_MMU_FILLUNIT_ECC_UNCORRECTED_ERR_COUNT': (0x0, 0x00100EA0, {'total': (0, 15), 'unique': (16, 31)}),
|
||||
'NV_PFB_PRI_MMU_FILLUNIT_ECC_UNCORRECTED_ERR_COUNT_TOTAL_INIT': 0,
|
||||
'NV_PFB_PRI_MMU_FILLUNIT_ECC_UNCORRECTED_ERR_COUNT_UNIQUE_INIT': 0,
|
||||
}
|
||||
@@ -0,0 +1,8 @@
|
||||
ga102 = {
|
||||
'NV_PFALCON_FBIF_TRANSCFG': (0x600, lambda i: (0x00000000+(i)*4), {'target': (0, 1), 'mem_type': (2, 2)}),
|
||||
'NV_PFALCON_FBIF_TRANSCFG__SIZE_1': 8,
|
||||
'NV_PFALCON_FBIF_TRANSCFG_TARGET_COHERENT_SYSMEM': 0x00000001,
|
||||
'NV_PFALCON_FBIF_TRANSCFG_MEM_TYPE_PHYSICAL': 0x00000001,
|
||||
'NV_PFALCON_FBIF_CTL': (0x600, 0x00000024, {'allow_phys_no_ctx': (7, 7)}),
|
||||
'NV_PFALCON_FBIF_CTL_ALLOW_PHYS_NO_CTX_ALLOW': 0x00000001,
|
||||
}
|
||||
@@ -0,0 +1,33 @@
|
||||
gh100 = {
|
||||
'NV_PFSP_EMEMC': (0x0, lambda i: (0x008F2ac0+(i)*8), {'offs': (2, 7), 'blk': (8, 15), 'aincw': (24, 24), 'aincr': (25, 25)}),
|
||||
'NV_PFSP_EMEMC__SIZE_1': 8,
|
||||
'NV_PFSP_EMEMC_OFFS_INIT': 0x00000000,
|
||||
'NV_PFSP_EMEMC_BLK_INIT': 0x00000000,
|
||||
'NV_PFSP_EMEMC_AINCW_INIT': 0x00000000,
|
||||
'NV_PFSP_EMEMC_AINCW_TRUE': 0x00000001,
|
||||
'NV_PFSP_EMEMC_AINCW_FALSE': 0x00000000,
|
||||
'NV_PFSP_EMEMC_AINCR_INIT': 0x00000000,
|
||||
'NV_PFSP_EMEMC_AINCR_TRUE': 0x00000001,
|
||||
'NV_PFSP_EMEMC_AINCR_FALSE': 0x00000000,
|
||||
'NV_PFSP_EMEMD': (0x0, lambda i: (0x008F2ac4+(i)*8), {'data': (0, 31)}),
|
||||
'NV_PFSP_EMEMD__SIZE_1': 8,
|
||||
'NV_PFSP_MSGQ_HEAD': (0x0, lambda i: (0x008F2c80+(i)*8), {'val': (0, 31)}),
|
||||
'NV_PFSP_MSGQ_HEAD__SIZE_1': 8,
|
||||
'NV_PFSP_MSGQ_HEAD_VAL_INIT': 0x00000000,
|
||||
'NV_PFSP_MSGQ_TAIL': (0x0, lambda i: (0x008F2c84+(i)*8), {'val': (0, 31)}),
|
||||
'NV_PFSP_MSGQ_TAIL__SIZE_1': 8,
|
||||
'NV_PFSP_MSGQ_TAIL_VAL_INIT': 0x00000000,
|
||||
'NV_PFSP_QUEUE_HEAD': (0x0, lambda i: (0x008F2c00+(i)*8), {'address': (0, 31)}),
|
||||
'NV_PFSP_QUEUE_HEAD__SIZE_1': 8,
|
||||
'NV_PFSP_QUEUE_HEAD_ADDRESS_INIT': 0x00000000,
|
||||
'NV_PFSP_QUEUE_TAIL': (0x0, lambda i: (0x008F2c04+(i)*8), {'address': (0, 31)}),
|
||||
'NV_PFSP_QUEUE_TAIL__SIZE_1': 8,
|
||||
'NV_PFSP_QUEUE_TAIL_ADDRESS_INIT': 0x00000000,
|
||||
'NV_PFSP_FALCON_COMMON_SCRATCH_GROUP_2': (0x0, lambda i: (0x008f0320+(i)*4), {'val': (0, 31)}),
|
||||
'NV_PFSP_FALCON_COMMON_SCRATCH_GROUP_2__SIZE_1': 4,
|
||||
'NV_PFSP_FALCON_COMMON_SCRATCH_GROUP_2__DEVICE_MAP': 0x00000016,
|
||||
'NV_PFSP_FALCON_COMMON_SCRATCH_GROUP_2_VAL_INIT': 0x00000000,
|
||||
'NV_PFSP_FALCON_COMMON_SCRATCH_GROUP_3': (0x0, lambda i: (0x008f0330+(i)*4), {'val': (0, 31)}),
|
||||
'NV_PFSP_FALCON_COMMON_SCRATCH_GROUP_3__SIZE_1': 4,
|
||||
'NV_PFSP_FALCON_COMMON_SCRATCH_GROUP_3_VAL_INIT': 0x00000000,
|
||||
}
|
||||
@@ -0,0 +1,14 @@
|
||||
ga102 = {
|
||||
'NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_PRIV_LEVEL_MASK': (0x0, 0x00118128, {'read_protection': (0, 3), 'read_protection_level0': (0, 0)}),
|
||||
'NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE': 0x00000001,
|
||||
'NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE': 0x00000000,
|
||||
'NV_PGC6_AON_SECURE_SCRATCH_GROUP_03': (0x0, lambda i: (0x00118214+(i)*4), {}),
|
||||
'NV_PGC6_AON_SECURE_SCRATCH_GROUP_05': (0x0, lambda i: (0x00118234+(i)*4), {'priv_level_mask_read_protection': (0, 3), 'priv_level_mask_read_protection_level0': (0, 0), '0_gfw_boot_progress': (0, 7)}),
|
||||
'NV_PGC6_AON_SECURE_SCRATCH_GROUP_42': (0x0, 0x001183a4, {}),
|
||||
'NV_PGC6_BSI_SECURE_SCRATCH_14': (0x0, 0x001180f8, {'boot_stage_3_handoff': (26, 26)}),
|
||||
'NV_PGC6_AON_FRTS_INPUT_WPR_SIZE_SECURE_SCRATCH_GROUP_03_0_WPR_SIZE_1MB_IN_4K': (0x0, 0x100, {}),
|
||||
'NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_0_GFW_BOOT_PROGRESS_COMPLETED': 0x000000FF,
|
||||
'NV_USABLE_FB_SIZE_IN_MB_VALUE_INIT': 0,
|
||||
'NV_PGC6_BSI_SECURE_SCRATCH_14_BOOT_STAGE_3_HANDOFF_VALUE_INIT': 0x0,
|
||||
'NV_PGC6_BSI_SECURE_SCRATCH_14_BOOT_STAGE_3_HANDOFF_VALUE_DONE': 0x1,
|
||||
}
|
||||
10
tinygrad_repo/tinygrad/runtime/autogen/nv_regs/dev_gsp.py
Normal file
10
tinygrad_repo/tinygrad/runtime/autogen/nv_regs/dev_gsp.py
Normal file
@@ -0,0 +1,10 @@
|
||||
ga102 = {
|
||||
'NV_PGSP_FALCON_MAILBOX0': (0x0, 0x110040, {'data': (0, 31)}),
|
||||
'NV_PGSP_FALCON_MAILBOX1': (0x0, 0x110044, {'data': (0, 31)}),
|
||||
'NV_PGSP_FALCON_ENGINE': (0x0, 0x1103c0, {'reset': (0, 0)}),
|
||||
'NV_PGSP_FALCON_ENGINE_RESET_TRUE': 0x00000001,
|
||||
'NV_PGSP_FALCON_ENGINE_RESET_FALSE': 0x00000000,
|
||||
'NV_PGSP_MAILBOX__SIZE_1': 4,
|
||||
'NV_PGSP_QUEUE_HEAD': (0x0, lambda i: (0x110c00+(i)*8), {'address': (0, 31)}),
|
||||
'NV_PGSP_QUEUE_HEAD__SIZE_1': 8,
|
||||
}
|
||||
895
tinygrad_repo/tinygrad/runtime/autogen/nv_regs/dev_mmu.py
Normal file
895
tinygrad_repo/tinygrad/runtime/autogen/nv_regs/dev_mmu.py
Normal file
@@ -0,0 +1,895 @@
|
||||
tu102 = {
|
||||
'NV_MMU_PDE': (None, None, {'aperture_big': ((0*32+0), (0*32+1)), 'size': ((0*32+2), (0*32+3)), 'address_big_sys': ((0*32+4), (0*32+31)), 'address_big_vid': ((0*32+4), (0*32+31-3)), 'address_big_vid_peer': ((0*32+32-3), (0*32+31)), 'aperture_small': ((1*32+0), (1*32+1)), 'vol_small': ((1*32+2), (1*32+2)), 'vol_big': ((1*32+3), (1*32+3)), 'address_small_sys': ((1*32+4), (1*32+31)), 'address_small_vid': ((1*32+4), (1*32+31-3)), 'address_small_vid_peer': ((1*32+32-3), (1*32+31))}),
|
||||
'NV_MMU_PDE_APERTURE_BIG_INVALID': 0x00000000,
|
||||
'NV_MMU_PDE_APERTURE_BIG_VIDEO_MEMORY': 0x00000001,
|
||||
'NV_MMU_PDE_APERTURE_BIG_SYSTEM_COHERENT_MEMORY': 0x00000002,
|
||||
'NV_MMU_PDE_APERTURE_BIG_SYSTEM_NON_COHERENT_MEMORY': 0x00000003,
|
||||
'NV_MMU_PDE_SIZE_FULL': 0x00000000,
|
||||
'NV_MMU_PDE_SIZE_HALF': 0x00000001,
|
||||
'NV_MMU_PDE_SIZE_QUARTER': 0x00000002,
|
||||
'NV_MMU_PDE_SIZE_EIGHTH': 0x00000003,
|
||||
'NV_MMU_PDE_ADDRESS_BIG_VID_PEER_0': 0x00000000,
|
||||
'NV_MMU_PDE_APERTURE_SMALL_INVALID': 0x00000000,
|
||||
'NV_MMU_PDE_APERTURE_SMALL_VIDEO_MEMORY': 0x00000001,
|
||||
'NV_MMU_PDE_APERTURE_SMALL_SYSTEM_COHERENT_MEMORY': 0x00000002,
|
||||
'NV_MMU_PDE_APERTURE_SMALL_SYSTEM_NON_COHERENT_MEMORY': 0x00000003,
|
||||
'NV_MMU_PDE_VOL_SMALL_TRUE': 0x00000001,
|
||||
'NV_MMU_PDE_VOL_SMALL_FALSE': 0x00000000,
|
||||
'NV_MMU_PDE_VOL_BIG_TRUE': 0x00000001,
|
||||
'NV_MMU_PDE_VOL_BIG_FALSE': 0x00000000,
|
||||
'NV_MMU_PDE_ADDRESS_SMALL_VID_PEER_0': 0x00000000,
|
||||
'NV_MMU_PDE_ADDRESS_SHIFT': 0x0000000c,
|
||||
'NV_MMU_PDE__SIZE': 8,
|
||||
'NV_MMU_PTE': (None, None, {'valid': ((0*32+0), (0*32+0)), 'privilege': ((0*32+1), (0*32+1)), 'read_only': ((0*32+2), (0*32+2)), 'encrypted': ((0*32+3), (0*32+3)), 'address_sys': ((0*32+4), (0*32+31)), 'address_vid': ((0*32+4), (0*32+31-3)), 'address_vid_peer': ((0*32+32-3), (0*32+31)), 'vol': ((1*32+0), (1*32+0)), 'aperture': ((1*32+1), (1*32+2)), 'lock': ((1*32+3), (1*32+3)), 'atomic_disable': ((1*32+3), (1*32+3)), 'comptagline': ((1*32+12), (1*32+20+11)), 'read_disable': ((1*32+30), (1*32+30)), 'write_disable': ((1*32+31), (1*32+31)), 'kind': ((1*32+4), (1*32+11))}),
|
||||
'NV_MMU_PTE_VALID_TRUE': 0x1,
|
||||
'NV_MMU_PTE_VALID_FALSE': 0x0,
|
||||
'NV_MMU_PTE_PRIVILEGE_TRUE': 0x1,
|
||||
'NV_MMU_PTE_PRIVILEGE_FALSE': 0x0,
|
||||
'NV_MMU_PTE_READ_ONLY_TRUE': 0x1,
|
||||
'NV_MMU_PTE_READ_ONLY_FALSE': 0x0,
|
||||
'NV_MMU_PTE_ENCRYPTED_TRUE': 0x00000001,
|
||||
'NV_MMU_PTE_ENCRYPTED_FALSE': 0x00000000,
|
||||
'NV_MMU_PTE_ADDRESS_VID_PEER_0': 0x00000000,
|
||||
'NV_MMU_PTE_ADDRESS_VID_PEER_1': 0x00000001,
|
||||
'NV_MMU_PTE_ADDRESS_VID_PEER_2': 0x00000002,
|
||||
'NV_MMU_PTE_ADDRESS_VID_PEER_3': 0x00000003,
|
||||
'NV_MMU_PTE_ADDRESS_VID_PEER_4': 0x00000004,
|
||||
'NV_MMU_PTE_ADDRESS_VID_PEER_5': 0x00000005,
|
||||
'NV_MMU_PTE_ADDRESS_VID_PEER_6': 0x00000006,
|
||||
'NV_MMU_PTE_ADDRESS_VID_PEER_7': 0x00000007,
|
||||
'NV_MMU_PTE_VOL_TRUE': 0x00000001,
|
||||
'NV_MMU_PTE_VOL_FALSE': 0x00000000,
|
||||
'NV_MMU_PTE_APERTURE_VIDEO_MEMORY': 0x00000000,
|
||||
'NV_MMU_PTE_APERTURE_PEER_MEMORY': 0x00000001,
|
||||
'NV_MMU_PTE_APERTURE_SYSTEM_COHERENT_MEMORY': 0x00000002,
|
||||
'NV_MMU_PTE_APERTURE_SYSTEM_NON_COHERENT_MEMORY': 0x00000003,
|
||||
'NV_MMU_PTE_LOCK_TRUE': 0x1,
|
||||
'NV_MMU_PTE_LOCK_FALSE': 0x0,
|
||||
'NV_MMU_PTE_ATOMIC_DISABLE_TRUE': 0x1,
|
||||
'NV_MMU_PTE_ATOMIC_DISABLE_FALSE': 0x0,
|
||||
'NV_MMU_PTE_READ_DISABLE_TRUE': 0x1,
|
||||
'NV_MMU_PTE_READ_DISABLE_FALSE': 0x0,
|
||||
'NV_MMU_PTE_WRITE_DISABLE_TRUE': 0x1,
|
||||
'NV_MMU_PTE_WRITE_DISABLE_FALSE': 0x0,
|
||||
'NV_MMU_PTE_ADDRESS_SHIFT': 0x0000000c,
|
||||
'NV_MMU_PTE__SIZE': 8,
|
||||
'NV_MMU_PTE_COMPTAGS_NONE': 0x0,
|
||||
'NV_MMU_PTE_COMPTAGS_1': 0x1,
|
||||
'NV_MMU_PTE_COMPTAGS_2': 0x2,
|
||||
'NV_MMU_PTE_KIND_INVALID': 0x07,
|
||||
'NV_MMU_PTE_KIND_PITCH': 0x00,
|
||||
'NV_MMU_PTE_KIND_GENERIC_MEMORY': 0x06,
|
||||
'NV_MMU_PTE_KIND_Z16': 0x01,
|
||||
'NV_MMU_PTE_KIND_S8': 0x02,
|
||||
'NV_MMU_PTE_KIND_S8Z24': 0x03,
|
||||
'NV_MMU_PTE_KIND_ZF32_X24S8': 0x04,
|
||||
'NV_MMU_PTE_KIND_Z24S8': 0x05,
|
||||
'NV_MMU_PTE_KIND_GENERIC_MEMORY_COMPRESSIBLE': 0x08,
|
||||
'NV_MMU_PTE_KIND_GENERIC_MEMORY_COMPRESSIBLE_DISABLE_PLC': 0x09,
|
||||
'NV_MMU_PTE_KIND_S8_COMPRESSIBLE_DISABLE_PLC': 0x0A,
|
||||
'NV_MMU_PTE_KIND_Z16_COMPRESSIBLE_DISABLE_PLC': 0x0B,
|
||||
'NV_MMU_PTE_KIND_S8Z24_COMPRESSIBLE_DISABLE_PLC': 0x0C,
|
||||
'NV_MMU_PTE_KIND_ZF32_X24S8_COMPRESSIBLE_DISABLE_PLC': 0x0D,
|
||||
'NV_MMU_PTE_KIND_Z24S8_COMPRESSIBLE_DISABLE_PLC': 0x0E,
|
||||
'NV_MMU_PTE_KIND_SMSKED_MESSAGE': 0x0F,
|
||||
'NV_MMU_PTE_KIND_Z16_2C': 0x2a,
|
||||
'NV_MMU_PTE_KIND_Z16_MS2_2C': 0x11,
|
||||
'NV_MMU_PTE_KIND_Z16_MS4_2C': 0xC3,
|
||||
'NV_MMU_PTE_KIND_Z16_MS8_2C': 0x46,
|
||||
'NV_MMU_PTE_KIND_Z16_MS16_2C': 0x6c,
|
||||
'NV_MMU_PTE_KIND_Z16_2Z': 0x6b,
|
||||
'NV_MMU_PTE_KIND_Z16_MS2_2Z': 0x10,
|
||||
'NV_MMU_PTE_KIND_Z16_MS4_2Z': 0x60,
|
||||
'NV_MMU_PTE_KIND_Z16_MS8_2Z': 0x61,
|
||||
'NV_MMU_PTE_KIND_Z16_MS16_2Z': 0x62,
|
||||
'NV_MMU_PTE_KIND_Z16_2CZ': 0x36,
|
||||
'NV_MMU_PTE_KIND_Z16_MS2_2CZ': 0x37,
|
||||
'NV_MMU_PTE_KIND_Z16_MS4_2CZ': 0x38,
|
||||
'NV_MMU_PTE_KIND_Z16_MS8_2CZ': 0x39,
|
||||
'NV_MMU_PTE_KIND_Z16_MS16_2CZ': 0x5f,
|
||||
'NV_MMU_PTE_KIND_S8Z24_1Z': 0x12,
|
||||
'NV_MMU_PTE_KIND_S8Z24_MS2_1Z': 0x13,
|
||||
'NV_MMU_PTE_KIND_S8Z24_MS4_1Z': 0x14,
|
||||
'NV_MMU_PTE_KIND_S8Z24_MS8_1Z': 0x15,
|
||||
'NV_MMU_PTE_KIND_S8Z24_MS16_1Z': 0x16,
|
||||
'NV_MMU_PTE_KIND_S8Z24_2CZ': 0x17,
|
||||
'NV_MMU_PTE_KIND_S8Z24_MS2_2CZ': 0x18,
|
||||
'NV_MMU_PTE_KIND_S8Z24_MS4_2CZ': 0x19,
|
||||
'NV_MMU_PTE_KIND_S8Z24_MS8_2CZ': 0x1a,
|
||||
'NV_MMU_PTE_KIND_S8Z24_MS16_2CZ': 0x1b,
|
||||
'NV_MMU_PTE_KIND_S8Z24_2CS': 0x1c,
|
||||
'NV_MMU_PTE_KIND_S8Z24_MS2_2CS': 0x1d,
|
||||
'NV_MMU_PTE_KIND_S8Z24_MS4_2CS': 0x1e,
|
||||
'NV_MMU_PTE_KIND_S8Z24_MS8_2CS': 0x1f,
|
||||
'NV_MMU_PTE_KIND_S8Z24_MS16_2CS': 0x20,
|
||||
'NV_MMU_PTE_KIND_S8Z24_4CSZV': 0x21,
|
||||
'NV_MMU_PTE_KIND_S8Z24_MS2_4CSZV': 0x22,
|
||||
'NV_MMU_PTE_KIND_S8Z24_MS4_4CSZV': 0x23,
|
||||
'NV_MMU_PTE_KIND_S8Z24_MS8_4CSZV': 0x24,
|
||||
'NV_MMU_PTE_KIND_S8Z24_MS16_4CSZV': 0x25,
|
||||
'NV_MMU_PTE_KIND_V8Z24_MS4_VC12': 0x26,
|
||||
'NV_MMU_PTE_KIND_V8Z24_MS4_VC4': 0x27,
|
||||
'NV_MMU_PTE_KIND_V8Z24_MS8_VC8': 0x28,
|
||||
'NV_MMU_PTE_KIND_V8Z24_MS8_VC24': 0x29,
|
||||
'NV_MMU_PTE_KIND_V8Z24_MS4_VC12_1ZV': 0x2e,
|
||||
'NV_MMU_PTE_KIND_V8Z24_MS4_VC4_1ZV': 0x2f,
|
||||
'NV_MMU_PTE_KIND_V8Z24_MS8_VC8_1ZV': 0x30,
|
||||
'NV_MMU_PTE_KIND_V8Z24_MS8_VC24_1ZV': 0x31,
|
||||
'NV_MMU_PTE_KIND_V8Z24_MS4_VC12_2CS': 0x32,
|
||||
'NV_MMU_PTE_KIND_V8Z24_MS4_VC4_2CS': 0x33,
|
||||
'NV_MMU_PTE_KIND_V8Z24_MS8_VC8_2CS': 0x34,
|
||||
'NV_MMU_PTE_KIND_V8Z24_MS8_VC24_2CS': 0x35,
|
||||
'NV_MMU_PTE_KIND_V8Z24_MS4_VC12_2CZV': 0x3a,
|
||||
'NV_MMU_PTE_KIND_V8Z24_MS4_VC4_2CZV': 0x3b,
|
||||
'NV_MMU_PTE_KIND_V8Z24_MS8_VC8_2CZV': 0x3c,
|
||||
'NV_MMU_PTE_KIND_V8Z24_MS8_VC24_2CZV': 0x3d,
|
||||
'NV_MMU_PTE_KIND_V8Z24_MS4_VC12_2ZV': 0x3e,
|
||||
'NV_MMU_PTE_KIND_V8Z24_MS4_VC4_2ZV': 0x3f,
|
||||
'NV_MMU_PTE_KIND_V8Z24_MS8_VC8_2ZV': 0x40,
|
||||
'NV_MMU_PTE_KIND_V8Z24_MS8_VC24_2ZV': 0x41,
|
||||
'NV_MMU_PTE_KIND_V8Z24_MS4_VC12_4CSZV': 0x42,
|
||||
'NV_MMU_PTE_KIND_V8Z24_MS4_VC4_4CSZV': 0x43,
|
||||
'NV_MMU_PTE_KIND_V8Z24_MS8_VC8_4CSZV': 0x44,
|
||||
'NV_MMU_PTE_KIND_V8Z24_MS8_VC24_4CSZV': 0x45,
|
||||
'NV_MMU_PTE_KIND_Z24S8_1Z': 0x47,
|
||||
'NV_MMU_PTE_KIND_Z24S8_MS2_1Z': 0x48,
|
||||
'NV_MMU_PTE_KIND_Z24S8_MS4_1Z': 0x49,
|
||||
'NV_MMU_PTE_KIND_Z24S8_MS8_1Z': 0x4a,
|
||||
'NV_MMU_PTE_KIND_Z24S8_MS16_1Z': 0x4b,
|
||||
'NV_MMU_PTE_KIND_Z24S8_2CS': 0x4c,
|
||||
'NV_MMU_PTE_KIND_Z24S8_MS2_2CS': 0x4d,
|
||||
'NV_MMU_PTE_KIND_Z24S8_MS4_2CS': 0x4e,
|
||||
'NV_MMU_PTE_KIND_Z24S8_MS8_2CS': 0x4f,
|
||||
'NV_MMU_PTE_KIND_Z24S8_MS16_2CS': 0x50,
|
||||
'NV_MMU_PTE_KIND_Z24S8_2CZ': 0x51,
|
||||
'NV_MMU_PTE_KIND_Z24S8_MS2_2CZ': 0x52,
|
||||
'NV_MMU_PTE_KIND_Z24S8_MS4_2CZ': 0x53,
|
||||
'NV_MMU_PTE_KIND_Z24S8_MS8_2CZ': 0x54,
|
||||
'NV_MMU_PTE_KIND_Z24S8_MS16_2CZ': 0x55,
|
||||
'NV_MMU_PTE_KIND_Z24S8_4CSZV': 0x56,
|
||||
'NV_MMU_PTE_KIND_Z24S8_MS2_4CSZV': 0x57,
|
||||
'NV_MMU_PTE_KIND_Z24S8_MS4_4CSZV': 0x58,
|
||||
'NV_MMU_PTE_KIND_Z24S8_MS8_4CSZV': 0x59,
|
||||
'NV_MMU_PTE_KIND_Z24S8_MS16_4CSZV': 0x5a,
|
||||
'NV_MMU_PTE_KIND_Z24V8_MS4_VC12': 0x5b,
|
||||
'NV_MMU_PTE_KIND_Z24V8_MS4_VC4': 0x5c,
|
||||
'NV_MMU_PTE_KIND_Z24V8_MS8_VC8': 0x5d,
|
||||
'NV_MMU_PTE_KIND_Z24V8_MS8_VC24': 0x5e,
|
||||
'NV_MMU_PTE_KIND_Z24V8_MS4_VC12_1ZV': 0x63,
|
||||
'NV_MMU_PTE_KIND_Z24V8_MS4_VC4_1ZV': 0x64,
|
||||
'NV_MMU_PTE_KIND_Z24V8_MS8_VC8_1ZV': 0x65,
|
||||
'NV_MMU_PTE_KIND_Z24V8_MS8_VC24_1ZV': 0x66,
|
||||
'NV_MMU_PTE_KIND_Z24V8_MS4_VC12_2CS': 0x67,
|
||||
'NV_MMU_PTE_KIND_Z24V8_MS4_VC4_2CS': 0x68,
|
||||
'NV_MMU_PTE_KIND_Z24V8_MS8_VC8_2CS': 0x69,
|
||||
'NV_MMU_PTE_KIND_Z24V8_MS8_VC24_2CS': 0x6a,
|
||||
'NV_MMU_PTE_KIND_Z24V8_MS4_VC12_2CZV': 0x6f,
|
||||
'NV_MMU_PTE_KIND_Z24V8_MS4_VC4_2CZV': 0x70,
|
||||
'NV_MMU_PTE_KIND_Z24V8_MS8_VC8_2CZV': 0x71,
|
||||
'NV_MMU_PTE_KIND_Z24V8_MS8_VC24_2CZV': 0x72,
|
||||
'NV_MMU_PTE_KIND_Z24V8_MS4_VC12_2ZV': 0x73,
|
||||
'NV_MMU_PTE_KIND_Z24V8_MS4_VC4_2ZV': 0x74,
|
||||
'NV_MMU_PTE_KIND_Z24V8_MS8_VC8_2ZV': 0x75,
|
||||
'NV_MMU_PTE_KIND_Z24V8_MS8_VC24_2ZV': 0x76,
|
||||
'NV_MMU_PTE_KIND_Z24V8_MS4_VC12_4CSZV': 0x77,
|
||||
'NV_MMU_PTE_KIND_Z24V8_MS4_VC4_4CSZV': 0x78,
|
||||
'NV_MMU_PTE_KIND_Z24V8_MS8_VC8_4CSZV': 0x79,
|
||||
'NV_MMU_PTE_KIND_Z24V8_MS8_VC24_4CSZV': 0x7a,
|
||||
'NV_MMU_PTE_KIND_ZF32': 0x7b,
|
||||
'NV_MMU_PTE_KIND_ZF32_1Z': 0x7c,
|
||||
'NV_MMU_PTE_KIND_ZF32_MS2_1Z': 0x7d,
|
||||
'NV_MMU_PTE_KIND_ZF32_MS4_1Z': 0x7e,
|
||||
'NV_MMU_PTE_KIND_ZF32_MS8_1Z': 0x7f,
|
||||
'NV_MMU_PTE_KIND_ZF32_MS16_1Z': 0x80,
|
||||
'NV_MMU_PTE_KIND_ZF32_2CS': 0x81,
|
||||
'NV_MMU_PTE_KIND_ZF32_MS2_2CS': 0x82,
|
||||
'NV_MMU_PTE_KIND_ZF32_MS4_2CS': 0x83,
|
||||
'NV_MMU_PTE_KIND_ZF32_MS8_2CS': 0x84,
|
||||
'NV_MMU_PTE_KIND_ZF32_MS16_2CS': 0x85,
|
||||
'NV_MMU_PTE_KIND_ZF32_2CZ': 0x86,
|
||||
'NV_MMU_PTE_KIND_ZF32_MS2_2CZ': 0x87,
|
||||
'NV_MMU_PTE_KIND_ZF32_MS4_2CZ': 0x88,
|
||||
'NV_MMU_PTE_KIND_ZF32_MS8_2CZ': 0x89,
|
||||
'NV_MMU_PTE_KIND_ZF32_MS16_2CZ': 0x8a,
|
||||
'NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12': 0x8b,
|
||||
'NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4': 0x8c,
|
||||
'NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8': 0x8d,
|
||||
'NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC24': 0x8e,
|
||||
'NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12_1CS': 0x8f,
|
||||
'NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4_1CS': 0x90,
|
||||
'NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8_1CS': 0x91,
|
||||
'NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC24_1CS': 0x92,
|
||||
'NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12_1ZV': 0x97,
|
||||
'NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4_1ZV': 0x98,
|
||||
'NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8_1ZV': 0x99,
|
||||
'NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC24_1ZV': 0x9a,
|
||||
'NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12_1CZV': 0x9b,
|
||||
'NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4_1CZV': 0x9c,
|
||||
'NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8_1CZV': 0x9d,
|
||||
'NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC24_1CZV': 0x9e,
|
||||
'NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12_2CS': 0x9f,
|
||||
'NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4_2CS': 0xa0,
|
||||
'NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8_2CS': 0xa1,
|
||||
'NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC24_2CS': 0xa2,
|
||||
'NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12_2CSZV': 0xa3,
|
||||
'NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4_2CSZV': 0xa4,
|
||||
'NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8_2CSZV': 0xa5,
|
||||
'NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC24_2CSZV': 0xa6,
|
||||
'NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12': 0xa7,
|
||||
'NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4': 0xa8,
|
||||
'NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8': 0xa9,
|
||||
'NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC24': 0xaa,
|
||||
'NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12_1CS': 0xab,
|
||||
'NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4_1CS': 0xac,
|
||||
'NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8_1CS': 0xad,
|
||||
'NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC24_1CS': 0xae,
|
||||
'NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12_1ZV': 0xb3,
|
||||
'NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4_1ZV': 0xb4,
|
||||
'NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8_1ZV': 0xb5,
|
||||
'NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC24_1ZV': 0xb6,
|
||||
'NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12_1CZV': 0xb7,
|
||||
'NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4_1CZV': 0xb8,
|
||||
'NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8_1CZV': 0xb9,
|
||||
'NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC24_1CZV': 0xba,
|
||||
'NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12_2CS': 0xbb,
|
||||
'NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4_2CS': 0xbc,
|
||||
'NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8_2CS': 0xbd,
|
||||
'NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC24_2CS': 0xbe,
|
||||
'NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12_2CSZV': 0xbf,
|
||||
'NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4_2CSZV': 0xc0,
|
||||
'NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8_2CSZV': 0xc1,
|
||||
'NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC24_2CSZV': 0xc2,
|
||||
'NV_MMU_PTE_KIND_ZF32_X24S8_1CS': 0xc4,
|
||||
'NV_MMU_PTE_KIND_ZF32_X24S8_MS2_1CS': 0xc5,
|
||||
'NV_MMU_PTE_KIND_ZF32_X24S8_MS4_1CS': 0xc6,
|
||||
'NV_MMU_PTE_KIND_ZF32_X24S8_MS8_1CS': 0xc7,
|
||||
'NV_MMU_PTE_KIND_ZF32_X24S8_MS16_1CS': 0xc8,
|
||||
'NV_MMU_PTE_KIND_ZF32_X24S8_2CSZV': 0xce,
|
||||
'NV_MMU_PTE_KIND_ZF32_X24S8_MS2_2CSZV': 0xcf,
|
||||
'NV_MMU_PTE_KIND_ZF32_X24S8_MS4_2CSZV': 0xd0,
|
||||
'NV_MMU_PTE_KIND_ZF32_X24S8_MS8_2CSZV': 0xd1,
|
||||
'NV_MMU_PTE_KIND_ZF32_X24S8_MS16_2CSZV': 0xd2,
|
||||
'NV_MMU_PTE_KIND_ZF32_X24S8_2CS': 0xd3,
|
||||
'NV_MMU_PTE_KIND_ZF32_X24S8_MS2_2CS': 0xd4,
|
||||
'NV_MMU_PTE_KIND_ZF32_X24S8_MS4_2CS': 0xd5,
|
||||
'NV_MMU_PTE_KIND_ZF32_X24S8_MS8_2CS': 0xd6,
|
||||
'NV_MMU_PTE_KIND_ZF32_X24S8_MS16_2CS': 0xd7,
|
||||
'NV_MMU_PTE_KIND_S8_2S': 0x2b,
|
||||
'NV_MMU_PTE_KIND_GENERIC_16BX2': 0xfe,
|
||||
'NV_MMU_PTE_KIND_C32_2C': 0xd8,
|
||||
'NV_MMU_PTE_KIND_C32_2CBR': 0xd9,
|
||||
'NV_MMU_PTE_KIND_C32_2CBA': 0xda,
|
||||
'NV_MMU_PTE_KIND_C32_2CRA': 0xdb,
|
||||
'NV_MMU_PTE_KIND_C32_2BRA': 0xdc,
|
||||
'NV_MMU_PTE_KIND_C32_MS2_2C': 0xdd,
|
||||
'NV_MMU_PTE_KIND_C32_MS2_2CBR': 0xde,
|
||||
'NV_MMU_PTE_KIND_C32_MS2_4CBRA': 0xcc,
|
||||
'NV_MMU_PTE_KIND_C32_MS4_2C': 0xdf,
|
||||
'NV_MMU_PTE_KIND_C32_MS4_2CBR': 0xe0,
|
||||
'NV_MMU_PTE_KIND_C32_MS4_2CBA': 0xe1,
|
||||
'NV_MMU_PTE_KIND_C32_MS4_2CRA': 0xe2,
|
||||
'NV_MMU_PTE_KIND_C32_MS4_2BRA': 0xe3,
|
||||
'NV_MMU_PTE_KIND_C32_MS4_4CBRA': 0x2c,
|
||||
'NV_MMU_PTE_KIND_C32_MS8_MS16_2C': 0xe4,
|
||||
'NV_MMU_PTE_KIND_C32_MS8_MS16_2CRA': 0xe5,
|
||||
'NV_MMU_PTE_KIND_C64_2C': 0xe6,
|
||||
'NV_MMU_PTE_KIND_C64_2CBR': 0xe7,
|
||||
'NV_MMU_PTE_KIND_C64_2CBA': 0xe8,
|
||||
'NV_MMU_PTE_KIND_C64_2CRA': 0xe9,
|
||||
'NV_MMU_PTE_KIND_C64_2BRA': 0xea,
|
||||
'NV_MMU_PTE_KIND_C64_MS2_2C': 0xeb,
|
||||
'NV_MMU_PTE_KIND_C64_MS2_2CBR': 0xec,
|
||||
'NV_MMU_PTE_KIND_C64_MS2_4CBRA': 0xcd,
|
||||
'NV_MMU_PTE_KIND_C64_MS4_2C': 0xed,
|
||||
'NV_MMU_PTE_KIND_C64_MS4_2CBR': 0xee,
|
||||
'NV_MMU_PTE_KIND_C64_MS4_2CBA': 0xef,
|
||||
'NV_MMU_PTE_KIND_C64_MS4_2CRA': 0xf0,
|
||||
'NV_MMU_PTE_KIND_C64_MS4_2BRA': 0xf1,
|
||||
'NV_MMU_PTE_KIND_C64_MS4_4CBRA': 0x2d,
|
||||
'NV_MMU_PTE_KIND_C64_MS8_MS16_2C': 0xf2,
|
||||
'NV_MMU_PTE_KIND_C64_MS8_MS16_2CRA': 0xf3,
|
||||
'NV_MMU_PTE_KIND_C128_2C': 0xf4,
|
||||
'NV_MMU_PTE_KIND_C128_2CR': 0xf5,
|
||||
'NV_MMU_PTE_KIND_C128_MS2_2C': 0xf6,
|
||||
'NV_MMU_PTE_KIND_C128_MS2_2CR': 0xf7,
|
||||
'NV_MMU_PTE_KIND_C128_MS4_2C': 0xf8,
|
||||
'NV_MMU_PTE_KIND_C128_MS4_2CR': 0xf9,
|
||||
'NV_MMU_PTE_KIND_C128_MS8_MS16_2C': 0xfa,
|
||||
'NV_MMU_PTE_KIND_C128_MS8_MS16_2CR': 0xfb,
|
||||
'NV_MMU_PTE_KIND_X8C24': 0xfc,
|
||||
'NV_MMU_PTE_KIND_PITCH_NO_SWIZZLE': 0xfd,
|
||||
'NV_MMU_PTE_KIND_SMHOST_MESSAGE': 0xcb,
|
||||
'NV_MMU_VER1_PDE': (None, None, {'aperture_big': ((0*32+0), (0*32+1)), 'size': ((0*32+2), (0*32+3)), 'address_big_sys': ((0*32+4), (0*32+31)), 'address_big_vid': ((0*32+4), (0*32+31-3)), 'address_big_vid_peer': ((0*32+32-3), (0*32+31)), 'aperture_small': ((1*32+0), (1*32+1)), 'vol_small': ((1*32+2), (1*32+2)), 'vol_big': ((1*32+3), (1*32+3)), 'address_small_sys': ((1*32+4), (1*32+31)), 'address_small_vid': ((1*32+4), (1*32+31-3)), 'address_small_vid_peer': ((1*32+32-3), (1*32+31))}),
|
||||
'NV_MMU_VER1_PDE_APERTURE_BIG_INVALID': 0x00000000,
|
||||
'NV_MMU_VER1_PDE_APERTURE_BIG_VIDEO_MEMORY': 0x00000001,
|
||||
'NV_MMU_VER1_PDE_APERTURE_BIG_SYSTEM_COHERENT_MEMORY': 0x00000002,
|
||||
'NV_MMU_VER1_PDE_APERTURE_BIG_SYSTEM_NON_COHERENT_MEMORY': 0x00000003,
|
||||
'NV_MMU_VER1_PDE_SIZE_FULL': 0x00000000,
|
||||
'NV_MMU_VER1_PDE_SIZE_HALF': 0x00000001,
|
||||
'NV_MMU_VER1_PDE_SIZE_QUARTER': 0x00000002,
|
||||
'NV_MMU_VER1_PDE_SIZE_EIGHTH': 0x00000003,
|
||||
'NV_MMU_VER1_PDE_ADDRESS_BIG_VID_PEER_0': 0x00000000,
|
||||
'NV_MMU_VER1_PDE_APERTURE_SMALL_INVALID': 0x00000000,
|
||||
'NV_MMU_VER1_PDE_APERTURE_SMALL_VIDEO_MEMORY': 0x00000001,
|
||||
'NV_MMU_VER1_PDE_APERTURE_SMALL_SYSTEM_COHERENT_MEMORY': 0x00000002,
|
||||
'NV_MMU_VER1_PDE_APERTURE_SMALL_SYSTEM_NON_COHERENT_MEMORY': 0x00000003,
|
||||
'NV_MMU_VER1_PDE_VOL_SMALL_TRUE': 0x00000001,
|
||||
'NV_MMU_VER1_PDE_VOL_SMALL_FALSE': 0x00000000,
|
||||
'NV_MMU_VER1_PDE_VOL_BIG_TRUE': 0x00000001,
|
||||
'NV_MMU_VER1_PDE_VOL_BIG_FALSE': 0x00000000,
|
||||
'NV_MMU_VER1_PDE_ADDRESS_SMALL_VID_PEER_0': 0x00000000,
|
||||
'NV_MMU_VER1_PDE_ADDRESS_SHIFT': 0x0000000c,
|
||||
'NV_MMU_VER1_PDE__SIZE': 8,
|
||||
'NV_MMU_VER1_PTE': (None, None, {'valid': ((0*32+0), (0*32+0)), 'privilege': ((0*32+1), (0*32+1)), 'read_only': ((0*32+2), (0*32+2)), 'encrypted': ((0*32+3), (0*32+3)), 'address_sys': ((0*32+4), (0*32+31)), 'address_vid': ((0*32+4), (0*32+31-3)), 'address_vid_peer': ((0*32+32-3), (0*32+31)), 'vol': ((1*32+0), (1*32+0)), 'aperture': ((1*32+1), (1*32+2)), 'atomic_disable': ((1*32+3), (1*32+3)), 'comptagline': ((1*32+12), (1*32+20+11)), 'kind': ((1*32+4), (1*32+11))}),
|
||||
'NV_MMU_VER1_PTE_VALID_TRUE': 0x1,
|
||||
'NV_MMU_VER1_PTE_VALID_FALSE': 0x0,
|
||||
'NV_MMU_VER1_PTE_PRIVILEGE_TRUE': 0x1,
|
||||
'NV_MMU_VER1_PTE_PRIVILEGE_FALSE': 0x0,
|
||||
'NV_MMU_VER1_PTE_READ_ONLY_TRUE': 0x1,
|
||||
'NV_MMU_VER1_PTE_READ_ONLY_FALSE': 0x0,
|
||||
'NV_MMU_VER1_PTE_ENCRYPTED_TRUE': 0x00000001,
|
||||
'NV_MMU_VER1_PTE_ENCRYPTED_FALSE': 0x00000000,
|
||||
'NV_MMU_VER1_PTE_ADDRESS_VID_PEER_0': 0x00000000,
|
||||
'NV_MMU_VER1_PTE_ADDRESS_VID_PEER_1': 0x00000001,
|
||||
'NV_MMU_VER1_PTE_ADDRESS_VID_PEER_2': 0x00000002,
|
||||
'NV_MMU_VER1_PTE_ADDRESS_VID_PEER_3': 0x00000003,
|
||||
'NV_MMU_VER1_PTE_ADDRESS_VID_PEER_4': 0x00000004,
|
||||
'NV_MMU_VER1_PTE_ADDRESS_VID_PEER_5': 0x00000005,
|
||||
'NV_MMU_VER1_PTE_ADDRESS_VID_PEER_6': 0x00000006,
|
||||
'NV_MMU_VER1_PTE_ADDRESS_VID_PEER_7': 0x00000007,
|
||||
'NV_MMU_VER1_PTE_VOL_TRUE': 0x00000001,
|
||||
'NV_MMU_VER1_PTE_VOL_FALSE': 0x00000000,
|
||||
'NV_MMU_VER1_PTE_APERTURE_VIDEO_MEMORY': 0x00000000,
|
||||
'NV_MMU_VER1_PTE_APERTURE_PEER_MEMORY': 0x00000001,
|
||||
'NV_MMU_VER1_PTE_APERTURE_SYSTEM_COHERENT_MEMORY': 0x00000002,
|
||||
'NV_MMU_VER1_PTE_APERTURE_SYSTEM_NON_COHERENT_MEMORY': 0x00000003,
|
||||
'NV_MMU_VER1_PTE_ATOMIC_DISABLE_TRUE': 0x1,
|
||||
'NV_MMU_VER1_PTE_ATOMIC_DISABLE_FALSE': 0x0,
|
||||
'NV_MMU_VER1_PTE_ADDRESS_SHIFT': 0x0000000c,
|
||||
'NV_MMU_VER1_PTE__SIZE': 8,
|
||||
'NV_MMU_VER1_PTE_COMPTAGS_NONE': 0x0,
|
||||
'NV_MMU_VER1_PTE_COMPTAGS_1': 0x1,
|
||||
'NV_MMU_VER1_PTE_COMPTAGS_2': 0x2,
|
||||
'NV_MMU_NEW_PDE': (None, None, {'is_pte': (0, 0), 'is_pde': (0, 0), 'valid': (0, 0), 'aperture': (1, 2), 'vol': (3, 3), 'no_ats': (5, 5), 'address_sys': (8, 53), 'address_vid': (8, (35-3)), 'address_vid_peer': ((36-3), 35)}),
|
||||
'NV_MMU_NEW_PDE_IS_PTE_TRUE': 0x1,
|
||||
'NV_MMU_NEW_PDE_IS_PTE_FALSE': 0x0,
|
||||
'NV_MMU_NEW_PDE_IS_PDE_TRUE': 0x0,
|
||||
'NV_MMU_NEW_PDE_IS_PDE_FALSE': 0x1,
|
||||
'NV_MMU_NEW_PDE_VALID_TRUE': 0x1,
|
||||
'NV_MMU_NEW_PDE_VALID_FALSE': 0x0,
|
||||
'NV_MMU_NEW_PDE_APERTURE_INVALID': 0x00000000,
|
||||
'NV_MMU_NEW_PDE_APERTURE_VIDEO_MEMORY': 0x00000001,
|
||||
'NV_MMU_NEW_PDE_APERTURE_SYSTEM_COHERENT_MEMORY': 0x00000002,
|
||||
'NV_MMU_NEW_PDE_APERTURE_SYSTEM_NON_COHERENT_MEMORY': 0x00000003,
|
||||
'NV_MMU_NEW_PDE_VOL_TRUE': 0x00000001,
|
||||
'NV_MMU_NEW_PDE_VOL_FALSE': 0x00000000,
|
||||
'NV_MMU_NEW_PDE_NO_ATS_TRUE': 0x1,
|
||||
'NV_MMU_NEW_PDE_NO_ATS_FALSE': 0x0,
|
||||
'NV_MMU_NEW_PDE_ADDRESS_VID_PEER_0': 0x00000000,
|
||||
'NV_MMU_NEW_PDE_ADDRESS_SHIFT': 0x0000000c,
|
||||
'NV_MMU_NEW_PDE__SIZE': 8,
|
||||
'NV_MMU_NEW_DUAL_PDE': (None, None, {'is_pte': (0, 0), 'is_pde': (0, 0), 'valid': (0, 0), 'aperture_big': (1, 2), 'vol_big': (3, 3), 'no_ats': (5, 5), 'address_big_sys': ((8-4), 53), 'address_big_vid': ((8-4), (35-3)), 'address_big_vid_peer': ((36-3), 35), 'aperture_small': (65, 66), 'vol_small': (67, 67), 'address_small_sys': (72, 117), 'address_small_vid': (72, (99-3)), 'address_small_vid_peer': ((100-3), 99)}),
|
||||
'NV_MMU_NEW_DUAL_PDE_IS_PTE_TRUE': 0x1,
|
||||
'NV_MMU_NEW_DUAL_PDE_IS_PTE_FALSE': 0x0,
|
||||
'NV_MMU_NEW_DUAL_PDE_IS_PDE_TRUE': 0x0,
|
||||
'NV_MMU_NEW_DUAL_PDE_IS_PDE_FALSE': 0x1,
|
||||
'NV_MMU_NEW_DUAL_PDE_VALID_TRUE': 0x1,
|
||||
'NV_MMU_NEW_DUAL_PDE_VALID_FALSE': 0x0,
|
||||
'NV_MMU_NEW_DUAL_PDE_APERTURE_BIG_INVALID': 0x00000000,
|
||||
'NV_MMU_NEW_DUAL_PDE_APERTURE_BIG_VIDEO_MEMORY': 0x00000001,
|
||||
'NV_MMU_NEW_DUAL_PDE_APERTURE_BIG_SYSTEM_COHERENT_MEMORY': 0x00000002,
|
||||
'NV_MMU_NEW_DUAL_PDE_APERTURE_BIG_SYSTEM_NON_COHERENT_MEMORY': 0x00000003,
|
||||
'NV_MMU_NEW_DUAL_PDE_VOL_BIG_TRUE': 0x00000001,
|
||||
'NV_MMU_NEW_DUAL_PDE_VOL_BIG_FALSE': 0x00000000,
|
||||
'NV_MMU_NEW_DUAL_PDE_NO_ATS_TRUE': 0x1,
|
||||
'NV_MMU_NEW_DUAL_PDE_NO_ATS_FALSE': 0x0,
|
||||
'NV_MMU_NEW_DUAL_PDE_ADDRESS_BIG_VID_PEER_0': 0x00000000,
|
||||
'NV_MMU_NEW_DUAL_PDE_APERTURE_SMALL_INVALID': 0x00000000,
|
||||
'NV_MMU_NEW_DUAL_PDE_APERTURE_SMALL_VIDEO_MEMORY': 0x00000001,
|
||||
'NV_MMU_NEW_DUAL_PDE_APERTURE_SMALL_SYSTEM_COHERENT_MEMORY': 0x00000002,
|
||||
'NV_MMU_NEW_DUAL_PDE_APERTURE_SMALL_SYSTEM_NON_COHERENT_MEMORY': 0x00000003,
|
||||
'NV_MMU_NEW_DUAL_PDE_VOL_SMALL_TRUE': 0x00000001,
|
||||
'NV_MMU_NEW_DUAL_PDE_VOL_SMALL_FALSE': 0x00000000,
|
||||
'NV_MMU_NEW_DUAL_PDE_ADDRESS_SMALL_VID_PEER_0': 0x00000000,
|
||||
'NV_MMU_NEW_DUAL_PDE_ADDRESS_SHIFT': 0x0000000c,
|
||||
'NV_MMU_NEW_DUAL_PDE_ADDRESS_BIG_SHIFT': 8,
|
||||
'NV_MMU_NEW_DUAL_PDE__SIZE': 16,
|
||||
'NV_MMU_NEW_PTE': (None, None, {'valid': (0, 0), 'aperture': (1, 2), 'vol': (3, 3), 'encrypted': (4, 4), 'privilege': (5, 5), 'read_only': (6, 6), 'atomic_disable': (7, 7), 'address_sys': (8, 53), 'address_vid': (8, (35-3)), 'address_vid_peer': ((36-3), 35), 'comptagline': (36, (20+35)), 'kind': (56, 63)}),
|
||||
'NV_MMU_NEW_PTE_VALID_TRUE': 0x1,
|
||||
'NV_MMU_NEW_PTE_VALID_FALSE': 0x0,
|
||||
'NV_MMU_NEW_PTE_APERTURE_VIDEO_MEMORY': 0x00000000,
|
||||
'NV_MMU_NEW_PTE_APERTURE_PEER_MEMORY': 0x00000001,
|
||||
'NV_MMU_NEW_PTE_APERTURE_SYSTEM_COHERENT_MEMORY': 0x00000002,
|
||||
'NV_MMU_NEW_PTE_APERTURE_SYSTEM_NON_COHERENT_MEMORY': 0x00000003,
|
||||
'NV_MMU_NEW_PTE_VOL_TRUE': 0x00000001,
|
||||
'NV_MMU_NEW_PTE_VOL_FALSE': 0x00000000,
|
||||
'NV_MMU_NEW_PTE_ENCRYPTED_TRUE': 0x00000001,
|
||||
'NV_MMU_NEW_PTE_ENCRYPTED_FALSE': 0x00000000,
|
||||
'NV_MMU_NEW_PTE_PRIVILEGE_TRUE': 0x1,
|
||||
'NV_MMU_NEW_PTE_PRIVILEGE_FALSE': 0x0,
|
||||
'NV_MMU_NEW_PTE_READ_ONLY_TRUE': 0x1,
|
||||
'NV_MMU_NEW_PTE_READ_ONLY_FALSE': 0x0,
|
||||
'NV_MMU_NEW_PTE_ATOMIC_DISABLE_TRUE': 0x1,
|
||||
'NV_MMU_NEW_PTE_ATOMIC_DISABLE_FALSE': 0x0,
|
||||
'NV_MMU_NEW_PTE_ADDRESS_VID_PEER_0': 0x00000000,
|
||||
'NV_MMU_NEW_PTE_ADDRESS_VID_PEER_1': 0x00000001,
|
||||
'NV_MMU_NEW_PTE_ADDRESS_VID_PEER_2': 0x00000002,
|
||||
'NV_MMU_NEW_PTE_ADDRESS_VID_PEER_3': 0x00000003,
|
||||
'NV_MMU_NEW_PTE_ADDRESS_VID_PEER_4': 0x00000004,
|
||||
'NV_MMU_NEW_PTE_ADDRESS_VID_PEER_5': 0x00000005,
|
||||
'NV_MMU_NEW_PTE_ADDRESS_VID_PEER_6': 0x00000006,
|
||||
'NV_MMU_NEW_PTE_ADDRESS_VID_PEER_7': 0x00000007,
|
||||
'NV_MMU_NEW_PTE_ADDRESS_SHIFT': 0x0000000c,
|
||||
'NV_MMU_NEW_PTE__SIZE': 8,
|
||||
'NV_MMU_VER2_PDE': (None, None, {'is_pte': (0, 0), 'is_pde': (0, 0), 'valid': (0, 0), 'aperture': (1, 2), 'vol': (3, 3), 'no_ats': (5, 5), 'address_sys': (8, 53), 'address_vid': (8, (35-3)), 'address_vid_peer': ((36-3), 35)}),
|
||||
'NV_MMU_VER2_PDE_IS_PTE_TRUE': 0x1,
|
||||
'NV_MMU_VER2_PDE_IS_PTE_FALSE': 0x0,
|
||||
'NV_MMU_VER2_PDE_IS_PDE_TRUE': 0x0,
|
||||
'NV_MMU_VER2_PDE_IS_PDE_FALSE': 0x1,
|
||||
'NV_MMU_VER2_PDE_VALID_TRUE': 0x1,
|
||||
'NV_MMU_VER2_PDE_VALID_FALSE': 0x0,
|
||||
'NV_MMU_VER2_PDE_APERTURE_INVALID': 0x00000000,
|
||||
'NV_MMU_VER2_PDE_APERTURE_VIDEO_MEMORY': 0x00000001,
|
||||
'NV_MMU_VER2_PDE_APERTURE_SYSTEM_COHERENT_MEMORY': 0x00000002,
|
||||
'NV_MMU_VER2_PDE_APERTURE_SYSTEM_NON_COHERENT_MEMORY': 0x00000003,
|
||||
'NV_MMU_VER2_PDE_VOL_TRUE': 0x00000001,
|
||||
'NV_MMU_VER2_PDE_VOL_FALSE': 0x00000000,
|
||||
'NV_MMU_VER2_PDE_NO_ATS_TRUE': 0x1,
|
||||
'NV_MMU_VER2_PDE_NO_ATS_FALSE': 0x0,
|
||||
'NV_MMU_VER2_PDE_ADDRESS_VID_PEER_0': 0x00000000,
|
||||
'NV_MMU_VER2_PDE_ADDRESS_SHIFT': 0x0000000c,
|
||||
'NV_MMU_VER2_PDE__SIZE': 8,
|
||||
'NV_MMU_VER2_DUAL_PDE': (None, None, {'is_pte': (0, 0), 'is_pde': (0, 0), 'valid': (0, 0), 'aperture_big': (1, 2), 'vol_big': (3, 3), 'no_ats': (5, 5), 'address_big_sys': ((8-4), 53), 'address_big_vid': ((8-4), (35-3)), 'address_big_vid_peer': ((36-3), 35), 'aperture_small': (65, 66), 'vol_small': (67, 67), 'address_small_sys': (72, 117), 'address_small_vid': (72, (99-3)), 'address_small_vid_peer': ((100-3), 99)}),
|
||||
'NV_MMU_VER2_DUAL_PDE_IS_PTE_TRUE': 0x1,
|
||||
'NV_MMU_VER2_DUAL_PDE_IS_PTE_FALSE': 0x0,
|
||||
'NV_MMU_VER2_DUAL_PDE_IS_PDE_TRUE': 0x0,
|
||||
'NV_MMU_VER2_DUAL_PDE_IS_PDE_FALSE': 0x1,
|
||||
'NV_MMU_VER2_DUAL_PDE_VALID_TRUE': 0x1,
|
||||
'NV_MMU_VER2_DUAL_PDE_VALID_FALSE': 0x0,
|
||||
'NV_MMU_VER2_DUAL_PDE_APERTURE_BIG_INVALID': 0x00000000,
|
||||
'NV_MMU_VER2_DUAL_PDE_APERTURE_BIG_VIDEO_MEMORY': 0x00000001,
|
||||
'NV_MMU_VER2_DUAL_PDE_APERTURE_BIG_SYSTEM_COHERENT_MEMORY': 0x00000002,
|
||||
'NV_MMU_VER2_DUAL_PDE_APERTURE_BIG_SYSTEM_NON_COHERENT_MEMORY': 0x00000003,
|
||||
'NV_MMU_VER2_DUAL_PDE_VOL_BIG_TRUE': 0x00000001,
|
||||
'NV_MMU_VER2_DUAL_PDE_VOL_BIG_FALSE': 0x00000000,
|
||||
'NV_MMU_VER2_DUAL_PDE_NO_ATS_TRUE': 0x1,
|
||||
'NV_MMU_VER2_DUAL_PDE_NO_ATS_FALSE': 0x0,
|
||||
'NV_MMU_VER2_DUAL_PDE_ADDRESS_BIG_VID_PEER_0': 0x00000000,
|
||||
'NV_MMU_VER2_DUAL_PDE_APERTURE_SMALL_INVALID': 0x00000000,
|
||||
'NV_MMU_VER2_DUAL_PDE_APERTURE_SMALL_VIDEO_MEMORY': 0x00000001,
|
||||
'NV_MMU_VER2_DUAL_PDE_APERTURE_SMALL_SYSTEM_COHERENT_MEMORY': 0x00000002,
|
||||
'NV_MMU_VER2_DUAL_PDE_APERTURE_SMALL_SYSTEM_NON_COHERENT_MEMORY': 0x00000003,
|
||||
'NV_MMU_VER2_DUAL_PDE_VOL_SMALL_TRUE': 0x00000001,
|
||||
'NV_MMU_VER2_DUAL_PDE_VOL_SMALL_FALSE': 0x00000000,
|
||||
'NV_MMU_VER2_DUAL_PDE_ADDRESS_SMALL_VID_PEER_0': 0x00000000,
|
||||
'NV_MMU_VER2_DUAL_PDE_ADDRESS_SHIFT': 0x0000000c,
|
||||
'NV_MMU_VER2_DUAL_PDE_ADDRESS_BIG_SHIFT': 8,
|
||||
'NV_MMU_VER2_DUAL_PDE__SIZE': 16,
|
||||
'NV_MMU_VER2_PTE': (None, None, {'valid': (0, 0), 'aperture': (1, 2), 'vol': (3, 3), 'encrypted': (4, 4), 'privilege': (5, 5), 'read_only': (6, 6), 'atomic_disable': (7, 7), 'address_sys': (8, 53), 'address_vid': (8, (35-3)), 'address_vid_peer': ((36-3), 35), 'comptagline': (36, (20+35)), 'kind': (56, 63)}),
|
||||
'NV_MMU_VER2_PTE_VALID_TRUE': 0x1,
|
||||
'NV_MMU_VER2_PTE_VALID_FALSE': 0x0,
|
||||
'NV_MMU_VER2_PTE_APERTURE_VIDEO_MEMORY': 0x00000000,
|
||||
'NV_MMU_VER2_PTE_APERTURE_PEER_MEMORY': 0x00000001,
|
||||
'NV_MMU_VER2_PTE_APERTURE_SYSTEM_COHERENT_MEMORY': 0x00000002,
|
||||
'NV_MMU_VER2_PTE_APERTURE_SYSTEM_NON_COHERENT_MEMORY': 0x00000003,
|
||||
'NV_MMU_VER2_PTE_VOL_TRUE': 0x00000001,
|
||||
'NV_MMU_VER2_PTE_VOL_FALSE': 0x00000000,
|
||||
'NV_MMU_VER2_PTE_ENCRYPTED_TRUE': 0x00000001,
|
||||
'NV_MMU_VER2_PTE_ENCRYPTED_FALSE': 0x00000000,
|
||||
'NV_MMU_VER2_PTE_PRIVILEGE_TRUE': 0x1,
|
||||
'NV_MMU_VER2_PTE_PRIVILEGE_FALSE': 0x0,
|
||||
'NV_MMU_VER2_PTE_READ_ONLY_TRUE': 0x1,
|
||||
'NV_MMU_VER2_PTE_READ_ONLY_FALSE': 0x0,
|
||||
'NV_MMU_VER2_PTE_ATOMIC_DISABLE_TRUE': 0x1,
|
||||
'NV_MMU_VER2_PTE_ATOMIC_DISABLE_FALSE': 0x0,
|
||||
'NV_MMU_VER2_PTE_ADDRESS_VID_PEER_0': 0x00000000,
|
||||
'NV_MMU_VER2_PTE_ADDRESS_VID_PEER_1': 0x00000001,
|
||||
'NV_MMU_VER2_PTE_ADDRESS_VID_PEER_2': 0x00000002,
|
||||
'NV_MMU_VER2_PTE_ADDRESS_VID_PEER_3': 0x00000003,
|
||||
'NV_MMU_VER2_PTE_ADDRESS_VID_PEER_4': 0x00000004,
|
||||
'NV_MMU_VER2_PTE_ADDRESS_VID_PEER_5': 0x00000005,
|
||||
'NV_MMU_VER2_PTE_ADDRESS_VID_PEER_6': 0x00000006,
|
||||
'NV_MMU_VER2_PTE_ADDRESS_VID_PEER_7': 0x00000007,
|
||||
'NV_MMU_VER2_PTE_ADDRESS_SHIFT': 0x0000000c,
|
||||
'NV_MMU_VER2_PTE__SIZE': 8,
|
||||
'NV_MMU_CLIENT': (None, None, {'kind': (0, 2)}),
|
||||
'NV_MMU_CLIENT_KIND_Z16': 0x1,
|
||||
'NV_MMU_CLIENT_KIND_S8': 0x2,
|
||||
'NV_MMU_CLIENT_KIND_S8Z24': 0x3,
|
||||
'NV_MMU_CLIENT_KIND_ZF32_X24S8': 0x4,
|
||||
'NV_MMU_CLIENT_KIND_Z24S8': 0x5,
|
||||
'NV_MMU_CLIENT_KIND_GENERIC_MEMORY': 0x6,
|
||||
'NV_MMU_CLIENT_KIND_INVALID': 0x7,
|
||||
}
|
||||
gh100 = {
|
||||
'NV_MMU_PDE': (None, None, {'aperture_big': ((0*32+0), (0*32+1)), 'size': ((0*32+2), (0*32+3)), 'address_big_sys': ((0*32+4), (0*32+31)), 'address_big_vid': ((0*32+4), (0*32+31-3)), 'address_big_vid_peer': ((0*32+32-3), (0*32+31)), 'aperture_small': ((1*32+0), (1*32+1)), 'vol_small': ((1*32+2), (1*32+2)), 'vol_big': ((1*32+3), (1*32+3)), 'address_small_sys': ((1*32+4), (1*32+31)), 'address_small_vid': ((1*32+4), (1*32+31-3)), 'address_small_vid_peer': ((1*32+32-3), (1*32+31))}),
|
||||
'NV_MMU_PDE_APERTURE_BIG_INVALID': 0x00000000,
|
||||
'NV_MMU_PDE_APERTURE_BIG_VIDEO_MEMORY': 0x00000001,
|
||||
'NV_MMU_PDE_APERTURE_BIG_SYSTEM_COHERENT_MEMORY': 0x00000002,
|
||||
'NV_MMU_PDE_APERTURE_BIG_SYSTEM_NON_COHERENT_MEMORY': 0x00000003,
|
||||
'NV_MMU_PDE_SIZE_FULL': 0x00000000,
|
||||
'NV_MMU_PDE_SIZE_HALF': 0x00000001,
|
||||
'NV_MMU_PDE_SIZE_QUARTER': 0x00000002,
|
||||
'NV_MMU_PDE_SIZE_EIGHTH': 0x00000003,
|
||||
'NV_MMU_PDE_ADDRESS_BIG_VID_PEER_0': 0x00000000,
|
||||
'NV_MMU_PDE_APERTURE_SMALL_INVALID': 0x00000000,
|
||||
'NV_MMU_PDE_APERTURE_SMALL_VIDEO_MEMORY': 0x00000001,
|
||||
'NV_MMU_PDE_APERTURE_SMALL_SYSTEM_COHERENT_MEMORY': 0x00000002,
|
||||
'NV_MMU_PDE_APERTURE_SMALL_SYSTEM_NON_COHERENT_MEMORY': 0x00000003,
|
||||
'NV_MMU_PDE_VOL_SMALL_TRUE': 0x00000001,
|
||||
'NV_MMU_PDE_VOL_SMALL_FALSE': 0x00000000,
|
||||
'NV_MMU_PDE_VOL_BIG_TRUE': 0x00000001,
|
||||
'NV_MMU_PDE_VOL_BIG_FALSE': 0x00000000,
|
||||
'NV_MMU_PDE_ADDRESS_SMALL_VID_PEER_0': 0x00000000,
|
||||
'NV_MMU_PDE_ADDRESS_SHIFT': 0x0000000c,
|
||||
'NV_MMU_PDE__SIZE': 8,
|
||||
'NV_MMU_PTE': (None, None, {'valid': ((0*32+0), (0*32+0)), 'privilege': ((0*32+1), (0*32+1)), 'read_only': ((0*32+2), (0*32+2)), 'encrypted': ((0*32+3), (0*32+3)), 'address_sys': ((0*32+4), (0*32+31)), 'address_vid': ((0*32+4), (0*32+31-3)), 'address_vid_peer': ((0*32+32-3), (0*32+31)), 'vol': ((1*32+0), (1*32+0)), 'aperture': ((1*32+1), (1*32+2)), 'lock': ((1*32+3), (1*32+3)), 'atomic_disable': ((1*32+3), (1*32+3)), 'comptagline': ((1*32+12), (1*32+20+11)), 'read_disable': ((1*32+30), (1*32+30)), 'write_disable': ((1*32+31), (1*32+31)), 'kind': ((1*32+4), (1*32+7))}),
|
||||
'NV_MMU_PTE_VALID_TRUE': 0x1,
|
||||
'NV_MMU_PTE_VALID_FALSE': 0x0,
|
||||
'NV_MMU_PTE_PRIVILEGE_TRUE': 0x1,
|
||||
'NV_MMU_PTE_PRIVILEGE_FALSE': 0x0,
|
||||
'NV_MMU_PTE_READ_ONLY_TRUE': 0x1,
|
||||
'NV_MMU_PTE_READ_ONLY_FALSE': 0x0,
|
||||
'NV_MMU_PTE_ENCRYPTED_TRUE': 0x00000001,
|
||||
'NV_MMU_PTE_ENCRYPTED_FALSE': 0x00000000,
|
||||
'NV_MMU_PTE_ADDRESS_VID_PEER_0': 0x00000000,
|
||||
'NV_MMU_PTE_ADDRESS_VID_PEER_1': 0x00000001,
|
||||
'NV_MMU_PTE_ADDRESS_VID_PEER_2': 0x00000002,
|
||||
'NV_MMU_PTE_ADDRESS_VID_PEER_3': 0x00000003,
|
||||
'NV_MMU_PTE_ADDRESS_VID_PEER_4': 0x00000004,
|
||||
'NV_MMU_PTE_ADDRESS_VID_PEER_5': 0x00000005,
|
||||
'NV_MMU_PTE_ADDRESS_VID_PEER_6': 0x00000006,
|
||||
'NV_MMU_PTE_ADDRESS_VID_PEER_7': 0x00000007,
|
||||
'NV_MMU_PTE_VOL_TRUE': 0x00000001,
|
||||
'NV_MMU_PTE_VOL_FALSE': 0x00000000,
|
||||
'NV_MMU_PTE_APERTURE_VIDEO_MEMORY': 0x00000000,
|
||||
'NV_MMU_PTE_APERTURE_PEER_MEMORY': 0x00000001,
|
||||
'NV_MMU_PTE_APERTURE_SYSTEM_COHERENT_MEMORY': 0x00000002,
|
||||
'NV_MMU_PTE_APERTURE_SYSTEM_NON_COHERENT_MEMORY': 0x00000003,
|
||||
'NV_MMU_PTE_LOCK_TRUE': 0x1,
|
||||
'NV_MMU_PTE_LOCK_FALSE': 0x0,
|
||||
'NV_MMU_PTE_ATOMIC_DISABLE_TRUE': 0x1,
|
||||
'NV_MMU_PTE_ATOMIC_DISABLE_FALSE': 0x0,
|
||||
'NV_MMU_PTE_READ_DISABLE_TRUE': 0x1,
|
||||
'NV_MMU_PTE_READ_DISABLE_FALSE': 0x0,
|
||||
'NV_MMU_PTE_WRITE_DISABLE_TRUE': 0x1,
|
||||
'NV_MMU_PTE_WRITE_DISABLE_FALSE': 0x0,
|
||||
'NV_MMU_PTE_ADDRESS_SHIFT': 0x0000000c,
|
||||
'NV_MMU_PTE__SIZE': 8,
|
||||
'NV_MMU_PTE_COMPTAGS_NONE': 0x0,
|
||||
'NV_MMU_PTE_COMPTAGS_1': 0x1,
|
||||
'NV_MMU_PTE_COMPTAGS_2': 0x2,
|
||||
'NV_MMU_PTE_KIND_INVALID': 0x07,
|
||||
'NV_MMU_PTE_KIND_PITCH': 0x00,
|
||||
'NV_MMU_PTE_KIND_GENERIC_MEMORY': 0x6,
|
||||
'NV_MMU_PTE_KIND_Z16': 0x1,
|
||||
'NV_MMU_PTE_KIND_S8': 0x2,
|
||||
'NV_MMU_PTE_KIND_S8Z24': 0x3,
|
||||
'NV_MMU_PTE_KIND_ZF32_X24S8': 0x4,
|
||||
'NV_MMU_PTE_KIND_Z24S8': 0x5,
|
||||
'NV_MMU_PTE_KIND_GENERIC_MEMORY_COMPRESSIBLE': 0x8,
|
||||
'NV_MMU_PTE_KIND_GENERIC_MEMORY_COMPRESSIBLE_DISABLE_PLC': 0x9,
|
||||
'NV_MMU_PTE_KIND_S8_COMPRESSIBLE_DISABLE_PLC': 0xA,
|
||||
'NV_MMU_PTE_KIND_Z16_COMPRESSIBLE_DISABLE_PLC': 0xB,
|
||||
'NV_MMU_PTE_KIND_S8Z24_COMPRESSIBLE_DISABLE_PLC': 0xC,
|
||||
'NV_MMU_PTE_KIND_ZF32_X24S8_COMPRESSIBLE_DISABLE_PLC': 0xD,
|
||||
'NV_MMU_PTE_KIND_Z24S8_COMPRESSIBLE_DISABLE_PLC': 0xE,
|
||||
'NV_MMU_PTE_KIND_SMSKED_MESSAGE': 0xF,
|
||||
'NV_MMU_VER1_PDE': (None, None, {'aperture_big': ((0*32+0), (0*32+1)), 'size': ((0*32+2), (0*32+3)), 'address_big_sys': ((0*32+4), (0*32+31)), 'address_big_vid': ((0*32+4), (0*32+31-3)), 'address_big_vid_peer': ((0*32+32-3), (0*32+31)), 'aperture_small': ((1*32+0), (1*32+1)), 'vol_small': ((1*32+2), (1*32+2)), 'vol_big': ((1*32+3), (1*32+3)), 'address_small_sys': ((1*32+4), (1*32+31)), 'address_small_vid': ((1*32+4), (1*32+31-3)), 'address_small_vid_peer': ((1*32+32-3), (1*32+31))}),
|
||||
'NV_MMU_VER1_PDE_APERTURE_BIG_INVALID': 0x00000000,
|
||||
'NV_MMU_VER1_PDE_APERTURE_BIG_VIDEO_MEMORY': 0x00000001,
|
||||
'NV_MMU_VER1_PDE_APERTURE_BIG_SYSTEM_COHERENT_MEMORY': 0x00000002,
|
||||
'NV_MMU_VER1_PDE_APERTURE_BIG_SYSTEM_NON_COHERENT_MEMORY': 0x00000003,
|
||||
'NV_MMU_VER1_PDE_SIZE_FULL': 0x00000000,
|
||||
'NV_MMU_VER1_PDE_SIZE_HALF': 0x00000001,
|
||||
'NV_MMU_VER1_PDE_SIZE_QUARTER': 0x00000002,
|
||||
'NV_MMU_VER1_PDE_SIZE_EIGHTH': 0x00000003,
|
||||
'NV_MMU_VER1_PDE_ADDRESS_BIG_VID_PEER_0': 0x00000000,
|
||||
'NV_MMU_VER1_PDE_APERTURE_SMALL_INVALID': 0x00000000,
|
||||
'NV_MMU_VER1_PDE_APERTURE_SMALL_VIDEO_MEMORY': 0x00000001,
|
||||
'NV_MMU_VER1_PDE_APERTURE_SMALL_SYSTEM_COHERENT_MEMORY': 0x00000002,
|
||||
'NV_MMU_VER1_PDE_APERTURE_SMALL_SYSTEM_NON_COHERENT_MEMORY': 0x00000003,
|
||||
'NV_MMU_VER1_PDE_VOL_SMALL_TRUE': 0x00000001,
|
||||
'NV_MMU_VER1_PDE_VOL_SMALL_FALSE': 0x00000000,
|
||||
'NV_MMU_VER1_PDE_VOL_BIG_TRUE': 0x00000001,
|
||||
'NV_MMU_VER1_PDE_VOL_BIG_FALSE': 0x00000000,
|
||||
'NV_MMU_VER1_PDE_ADDRESS_SMALL_VID_PEER_0': 0x00000000,
|
||||
'NV_MMU_VER1_PDE_ADDRESS_SHIFT': 0x0000000c,
|
||||
'NV_MMU_VER1_PDE__SIZE': 8,
|
||||
'NV_MMU_VER1_PTE': (None, None, {'valid': ((0*32+0), (0*32+0)), 'privilege': ((0*32+1), (0*32+1)), 'read_only': ((0*32+2), (0*32+2)), 'encrypted': ((0*32+3), (0*32+3)), 'address_sys': ((0*32+4), (0*32+31)), 'address_vid': ((0*32+4), (0*32+31-3)), 'address_vid_peer': ((0*32+32-3), (0*32+31)), 'vol': ((1*32+0), (1*32+0)), 'aperture': ((1*32+1), (1*32+2)), 'atomic_disable': ((1*32+3), (1*32+3)), 'comptagline': ((1*32+12), (1*32+20+11)), 'kind': ((1*32+4), (1*32+11))}),
|
||||
'NV_MMU_VER1_PTE_VALID_TRUE': 0x1,
|
||||
'NV_MMU_VER1_PTE_VALID_FALSE': 0x0,
|
||||
'NV_MMU_VER1_PTE_PRIVILEGE_TRUE': 0x1,
|
||||
'NV_MMU_VER1_PTE_PRIVILEGE_FALSE': 0x0,
|
||||
'NV_MMU_VER1_PTE_READ_ONLY_TRUE': 0x1,
|
||||
'NV_MMU_VER1_PTE_READ_ONLY_FALSE': 0x0,
|
||||
'NV_MMU_VER1_PTE_ENCRYPTED_TRUE': 0x00000001,
|
||||
'NV_MMU_VER1_PTE_ENCRYPTED_FALSE': 0x00000000,
|
||||
'NV_MMU_VER1_PTE_ADDRESS_VID_PEER_0': 0x00000000,
|
||||
'NV_MMU_VER1_PTE_ADDRESS_VID_PEER_1': 0x00000001,
|
||||
'NV_MMU_VER1_PTE_ADDRESS_VID_PEER_2': 0x00000002,
|
||||
'NV_MMU_VER1_PTE_ADDRESS_VID_PEER_3': 0x00000003,
|
||||
'NV_MMU_VER1_PTE_ADDRESS_VID_PEER_4': 0x00000004,
|
||||
'NV_MMU_VER1_PTE_ADDRESS_VID_PEER_5': 0x00000005,
|
||||
'NV_MMU_VER1_PTE_ADDRESS_VID_PEER_6': 0x00000006,
|
||||
'NV_MMU_VER1_PTE_ADDRESS_VID_PEER_7': 0x00000007,
|
||||
'NV_MMU_VER1_PTE_VOL_TRUE': 0x00000001,
|
||||
'NV_MMU_VER1_PTE_VOL_FALSE': 0x00000000,
|
||||
'NV_MMU_VER1_PTE_APERTURE_VIDEO_MEMORY': 0x00000000,
|
||||
'NV_MMU_VER1_PTE_APERTURE_PEER_MEMORY': 0x00000001,
|
||||
'NV_MMU_VER1_PTE_APERTURE_SYSTEM_COHERENT_MEMORY': 0x00000002,
|
||||
'NV_MMU_VER1_PTE_APERTURE_SYSTEM_NON_COHERENT_MEMORY': 0x00000003,
|
||||
'NV_MMU_VER1_PTE_ATOMIC_DISABLE_TRUE': 0x1,
|
||||
'NV_MMU_VER1_PTE_ATOMIC_DISABLE_FALSE': 0x0,
|
||||
'NV_MMU_VER1_PTE_ADDRESS_SHIFT': 0x0000000c,
|
||||
'NV_MMU_VER1_PTE__SIZE': 8,
|
||||
'NV_MMU_VER1_PTE_COMPTAGS_NONE': 0x0,
|
||||
'NV_MMU_VER1_PTE_COMPTAGS_1': 0x1,
|
||||
'NV_MMU_VER1_PTE_COMPTAGS_2': 0x2,
|
||||
'NV_MMU_NEW_PDE': (None, None, {'is_pte': (0, 0), 'is_pde': (0, 0), 'valid': (0, 0), 'aperture': (1, 2), 'vol': (3, 3), 'no_ats': (5, 5), 'address_sys': (8, 53), 'address_vid': (8, (35-3)), 'address_vid_peer': ((36-3), 35)}),
|
||||
'NV_MMU_NEW_PDE_IS_PTE_TRUE': 0x1,
|
||||
'NV_MMU_NEW_PDE_IS_PTE_FALSE': 0x0,
|
||||
'NV_MMU_NEW_PDE_IS_PDE_TRUE': 0x0,
|
||||
'NV_MMU_NEW_PDE_IS_PDE_FALSE': 0x1,
|
||||
'NV_MMU_NEW_PDE_VALID_TRUE': 0x1,
|
||||
'NV_MMU_NEW_PDE_VALID_FALSE': 0x0,
|
||||
'NV_MMU_NEW_PDE_APERTURE_INVALID': 0x00000000,
|
||||
'NV_MMU_NEW_PDE_APERTURE_VIDEO_MEMORY': 0x00000001,
|
||||
'NV_MMU_NEW_PDE_APERTURE_SYSTEM_COHERENT_MEMORY': 0x00000002,
|
||||
'NV_MMU_NEW_PDE_APERTURE_SYSTEM_NON_COHERENT_MEMORY': 0x00000003,
|
||||
'NV_MMU_NEW_PDE_VOL_TRUE': 0x00000001,
|
||||
'NV_MMU_NEW_PDE_VOL_FALSE': 0x00000000,
|
||||
'NV_MMU_NEW_PDE_NO_ATS_TRUE': 0x1,
|
||||
'NV_MMU_NEW_PDE_NO_ATS_FALSE': 0x0,
|
||||
'NV_MMU_NEW_PDE_ADDRESS_VID_PEER_0': 0x00000000,
|
||||
'NV_MMU_NEW_PDE_ADDRESS_SHIFT': 0x0000000c,
|
||||
'NV_MMU_NEW_PDE__SIZE': 8,
|
||||
'NV_MMU_NEW_DUAL_PDE': (None, None, {'is_pte': (0, 0), 'is_pde': (0, 0), 'valid': (0, 0), 'aperture_big': (1, 2), 'vol_big': (3, 3), 'no_ats': (5, 5), 'address_big_sys': ((8-4), 53), 'address_big_vid': ((8-4), (35-3)), 'address_big_vid_peer': ((36-3), 35), 'aperture_small': (65, 66), 'vol_small': (67, 67), 'address_small_sys': (72, 117), 'address_small_vid': (72, (99-3)), 'address_small_vid_peer': ((100-3), 99)}),
|
||||
'NV_MMU_NEW_DUAL_PDE_IS_PTE_TRUE': 0x1,
|
||||
'NV_MMU_NEW_DUAL_PDE_IS_PTE_FALSE': 0x0,
|
||||
'NV_MMU_NEW_DUAL_PDE_IS_PDE_TRUE': 0x0,
|
||||
'NV_MMU_NEW_DUAL_PDE_IS_PDE_FALSE': 0x1,
|
||||
'NV_MMU_NEW_DUAL_PDE_VALID_TRUE': 0x1,
|
||||
'NV_MMU_NEW_DUAL_PDE_VALID_FALSE': 0x0,
|
||||
'NV_MMU_NEW_DUAL_PDE_APERTURE_BIG_INVALID': 0x00000000,
|
||||
'NV_MMU_NEW_DUAL_PDE_APERTURE_BIG_VIDEO_MEMORY': 0x00000001,
|
||||
'NV_MMU_NEW_DUAL_PDE_APERTURE_BIG_SYSTEM_COHERENT_MEMORY': 0x00000002,
|
||||
'NV_MMU_NEW_DUAL_PDE_APERTURE_BIG_SYSTEM_NON_COHERENT_MEMORY': 0x00000003,
|
||||
'NV_MMU_NEW_DUAL_PDE_VOL_BIG_TRUE': 0x00000001,
|
||||
'NV_MMU_NEW_DUAL_PDE_VOL_BIG_FALSE': 0x00000000,
|
||||
'NV_MMU_NEW_DUAL_PDE_NO_ATS_TRUE': 0x1,
|
||||
'NV_MMU_NEW_DUAL_PDE_NO_ATS_FALSE': 0x0,
|
||||
'NV_MMU_NEW_DUAL_PDE_ADDRESS_BIG_VID_PEER_0': 0x00000000,
|
||||
'NV_MMU_NEW_DUAL_PDE_APERTURE_SMALL_INVALID': 0x00000000,
|
||||
'NV_MMU_NEW_DUAL_PDE_APERTURE_SMALL_VIDEO_MEMORY': 0x00000001,
|
||||
'NV_MMU_NEW_DUAL_PDE_APERTURE_SMALL_SYSTEM_COHERENT_MEMORY': 0x00000002,
|
||||
'NV_MMU_NEW_DUAL_PDE_APERTURE_SMALL_SYSTEM_NON_COHERENT_MEMORY': 0x00000003,
|
||||
'NV_MMU_NEW_DUAL_PDE_VOL_SMALL_TRUE': 0x00000001,
|
||||
'NV_MMU_NEW_DUAL_PDE_VOL_SMALL_FALSE': 0x00000000,
|
||||
'NV_MMU_NEW_DUAL_PDE_ADDRESS_SMALL_VID_PEER_0': 0x00000000,
|
||||
'NV_MMU_NEW_DUAL_PDE_ADDRESS_SHIFT': 0x0000000c,
|
||||
'NV_MMU_NEW_DUAL_PDE_ADDRESS_BIG_SHIFT': 8,
|
||||
'NV_MMU_NEW_DUAL_PDE__SIZE': 16,
|
||||
'NV_MMU_NEW_PTE': (None, None, {'valid': (0, 0), 'aperture': (1, 2), 'vol': (3, 3), 'encrypted': (4, 4), 'privilege': (5, 5), 'read_only': (6, 6), 'atomic_disable': (7, 7), 'address_sys': (8, 53), 'address_vid': (8, (35-3)), 'address_vid_peer': ((36-3), 35), 'comptagline': (36, (20+35)), 'kind': (56, 63)}),
|
||||
'NV_MMU_NEW_PTE_VALID_TRUE': 0x1,
|
||||
'NV_MMU_NEW_PTE_VALID_FALSE': 0x0,
|
||||
'NV_MMU_NEW_PTE_APERTURE_VIDEO_MEMORY': 0x00000000,
|
||||
'NV_MMU_NEW_PTE_APERTURE_PEER_MEMORY': 0x00000001,
|
||||
'NV_MMU_NEW_PTE_APERTURE_SYSTEM_COHERENT_MEMORY': 0x00000002,
|
||||
'NV_MMU_NEW_PTE_APERTURE_SYSTEM_NON_COHERENT_MEMORY': 0x00000003,
|
||||
'NV_MMU_NEW_PTE_VOL_TRUE': 0x00000001,
|
||||
'NV_MMU_NEW_PTE_VOL_FALSE': 0x00000000,
|
||||
'NV_MMU_NEW_PTE_ENCRYPTED_TRUE': 0x00000001,
|
||||
'NV_MMU_NEW_PTE_ENCRYPTED_FALSE': 0x00000000,
|
||||
'NV_MMU_NEW_PTE_PRIVILEGE_TRUE': 0x1,
|
||||
'NV_MMU_NEW_PTE_PRIVILEGE_FALSE': 0x0,
|
||||
'NV_MMU_NEW_PTE_READ_ONLY_TRUE': 0x1,
|
||||
'NV_MMU_NEW_PTE_READ_ONLY_FALSE': 0x0,
|
||||
'NV_MMU_NEW_PTE_ATOMIC_DISABLE_TRUE': 0x1,
|
||||
'NV_MMU_NEW_PTE_ATOMIC_DISABLE_FALSE': 0x0,
|
||||
'NV_MMU_NEW_PTE_ADDRESS_VID_PEER_0': 0x00000000,
|
||||
'NV_MMU_NEW_PTE_ADDRESS_VID_PEER_1': 0x00000001,
|
||||
'NV_MMU_NEW_PTE_ADDRESS_VID_PEER_2': 0x00000002,
|
||||
'NV_MMU_NEW_PTE_ADDRESS_VID_PEER_3': 0x00000003,
|
||||
'NV_MMU_NEW_PTE_ADDRESS_VID_PEER_4': 0x00000004,
|
||||
'NV_MMU_NEW_PTE_ADDRESS_VID_PEER_5': 0x00000005,
|
||||
'NV_MMU_NEW_PTE_ADDRESS_VID_PEER_6': 0x00000006,
|
||||
'NV_MMU_NEW_PTE_ADDRESS_VID_PEER_7': 0x00000007,
|
||||
'NV_MMU_NEW_PTE_ADDRESS_SHIFT': 0x0000000c,
|
||||
'NV_MMU_NEW_PTE__SIZE': 8,
|
||||
'NV_MMU_VER2_PDE': (None, None, {'is_pte': (0, 0), 'is_pde': (0, 0), 'valid': (0, 0), 'aperture': (1, 2), 'vol': (3, 3), 'no_ats': (5, 5), 'address_sys': (8, 53), 'address_vid': (8, (35-3)), 'address_vid_peer': ((36-3), 35)}),
|
||||
'NV_MMU_VER2_PDE_IS_PTE_TRUE': 0x1,
|
||||
'NV_MMU_VER2_PDE_IS_PTE_FALSE': 0x0,
|
||||
'NV_MMU_VER2_PDE_IS_PDE_TRUE': 0x0,
|
||||
'NV_MMU_VER2_PDE_IS_PDE_FALSE': 0x1,
|
||||
'NV_MMU_VER2_PDE_VALID_TRUE': 0x1,
|
||||
'NV_MMU_VER2_PDE_VALID_FALSE': 0x0,
|
||||
'NV_MMU_VER2_PDE_APERTURE_INVALID': 0x00000000,
|
||||
'NV_MMU_VER2_PDE_APERTURE_VIDEO_MEMORY': 0x00000001,
|
||||
'NV_MMU_VER2_PDE_APERTURE_SYSTEM_COHERENT_MEMORY': 0x00000002,
|
||||
'NV_MMU_VER2_PDE_APERTURE_SYSTEM_NON_COHERENT_MEMORY': 0x00000003,
|
||||
'NV_MMU_VER2_PDE_VOL_TRUE': 0x00000001,
|
||||
'NV_MMU_VER2_PDE_VOL_FALSE': 0x00000000,
|
||||
'NV_MMU_VER2_PDE_NO_ATS_TRUE': 0x1,
|
||||
'NV_MMU_VER2_PDE_NO_ATS_FALSE': 0x0,
|
||||
'NV_MMU_VER2_PDE_ADDRESS_VID_PEER_0': 0x00000000,
|
||||
'NV_MMU_VER2_PDE_ADDRESS_SHIFT': 0x0000000c,
|
||||
'NV_MMU_VER2_PDE__SIZE': 8,
|
||||
'NV_MMU_VER2_DUAL_PDE': (None, None, {'is_pte': (0, 0), 'is_pde': (0, 0), 'valid': (0, 0), 'aperture_big': (1, 2), 'vol_big': (3, 3), 'no_ats': (5, 5), 'address_big_sys': ((8-4), 53), 'address_big_vid': ((8-4), (35-3)), 'address_big_vid_peer': ((36-3), 35), 'aperture_small': (65, 66), 'vol_small': (67, 67), 'address_small_sys': (72, 117), 'address_small_vid': (72, (99-3)), 'address_small_vid_peer': ((100-3), 99)}),
|
||||
'NV_MMU_VER2_DUAL_PDE_IS_PTE_TRUE': 0x1,
|
||||
'NV_MMU_VER2_DUAL_PDE_IS_PTE_FALSE': 0x0,
|
||||
'NV_MMU_VER2_DUAL_PDE_IS_PDE_TRUE': 0x0,
|
||||
'NV_MMU_VER2_DUAL_PDE_IS_PDE_FALSE': 0x1,
|
||||
'NV_MMU_VER2_DUAL_PDE_VALID_TRUE': 0x1,
|
||||
'NV_MMU_VER2_DUAL_PDE_VALID_FALSE': 0x0,
|
||||
'NV_MMU_VER2_DUAL_PDE_APERTURE_BIG_INVALID': 0x00000000,
|
||||
'NV_MMU_VER2_DUAL_PDE_APERTURE_BIG_VIDEO_MEMORY': 0x00000001,
|
||||
'NV_MMU_VER2_DUAL_PDE_APERTURE_BIG_SYSTEM_COHERENT_MEMORY': 0x00000002,
|
||||
'NV_MMU_VER2_DUAL_PDE_APERTURE_BIG_SYSTEM_NON_COHERENT_MEMORY': 0x00000003,
|
||||
'NV_MMU_VER2_DUAL_PDE_VOL_BIG_TRUE': 0x00000001,
|
||||
'NV_MMU_VER2_DUAL_PDE_VOL_BIG_FALSE': 0x00000000,
|
||||
'NV_MMU_VER2_DUAL_PDE_NO_ATS_TRUE': 0x1,
|
||||
'NV_MMU_VER2_DUAL_PDE_NO_ATS_FALSE': 0x0,
|
||||
'NV_MMU_VER2_DUAL_PDE_ADDRESS_BIG_VID_PEER_0': 0x00000000,
|
||||
'NV_MMU_VER2_DUAL_PDE_APERTURE_SMALL_INVALID': 0x00000000,
|
||||
'NV_MMU_VER2_DUAL_PDE_APERTURE_SMALL_VIDEO_MEMORY': 0x00000001,
|
||||
'NV_MMU_VER2_DUAL_PDE_APERTURE_SMALL_SYSTEM_COHERENT_MEMORY': 0x00000002,
|
||||
'NV_MMU_VER2_DUAL_PDE_APERTURE_SMALL_SYSTEM_NON_COHERENT_MEMORY': 0x00000003,
|
||||
'NV_MMU_VER2_DUAL_PDE_VOL_SMALL_TRUE': 0x00000001,
|
||||
'NV_MMU_VER2_DUAL_PDE_VOL_SMALL_FALSE': 0x00000000,
|
||||
'NV_MMU_VER2_DUAL_PDE_ADDRESS_SMALL_VID_PEER_0': 0x00000000,
|
||||
'NV_MMU_VER2_DUAL_PDE_ADDRESS_SHIFT': 0x0000000c,
|
||||
'NV_MMU_VER2_DUAL_PDE_ADDRESS_BIG_SHIFT': 8,
|
||||
'NV_MMU_VER2_DUAL_PDE__SIZE': 16,
|
||||
'NV_MMU_VER2_PTE': (None, None, {'valid': (0, 0), 'aperture': (1, 2), 'vol': (3, 3), 'encrypted': (4, 4), 'privilege': (5, 5), 'read_only': (6, 6), 'atomic_disable': (7, 7), 'address_sys': (8, 53), 'address_vid': (8, (35-3)), 'address_vid_peer': ((36-3), 35), 'comptagline': (36, (20+35)), 'kind': (56, 63)}),
|
||||
'NV_MMU_VER2_PTE_VALID_TRUE': 0x1,
|
||||
'NV_MMU_VER2_PTE_VALID_FALSE': 0x0,
|
||||
'NV_MMU_VER2_PTE_APERTURE_VIDEO_MEMORY': 0x00000000,
|
||||
'NV_MMU_VER2_PTE_APERTURE_PEER_MEMORY': 0x00000001,
|
||||
'NV_MMU_VER2_PTE_APERTURE_SYSTEM_COHERENT_MEMORY': 0x00000002,
|
||||
'NV_MMU_VER2_PTE_APERTURE_SYSTEM_NON_COHERENT_MEMORY': 0x00000003,
|
||||
'NV_MMU_VER2_PTE_VOL_TRUE': 0x00000001,
|
||||
'NV_MMU_VER2_PTE_VOL_FALSE': 0x00000000,
|
||||
'NV_MMU_VER2_PTE_ENCRYPTED_TRUE': 0x00000001,
|
||||
'NV_MMU_VER2_PTE_ENCRYPTED_FALSE': 0x00000000,
|
||||
'NV_MMU_VER2_PTE_PRIVILEGE_TRUE': 0x1,
|
||||
'NV_MMU_VER2_PTE_PRIVILEGE_FALSE': 0x0,
|
||||
'NV_MMU_VER2_PTE_READ_ONLY_TRUE': 0x1,
|
||||
'NV_MMU_VER2_PTE_READ_ONLY_FALSE': 0x0,
|
||||
'NV_MMU_VER2_PTE_ATOMIC_DISABLE_TRUE': 0x1,
|
||||
'NV_MMU_VER2_PTE_ATOMIC_DISABLE_FALSE': 0x0,
|
||||
'NV_MMU_VER2_PTE_ADDRESS_VID_PEER_0': 0x00000000,
|
||||
'NV_MMU_VER2_PTE_ADDRESS_VID_PEER_1': 0x00000001,
|
||||
'NV_MMU_VER2_PTE_ADDRESS_VID_PEER_2': 0x00000002,
|
||||
'NV_MMU_VER2_PTE_ADDRESS_VID_PEER_3': 0x00000003,
|
||||
'NV_MMU_VER2_PTE_ADDRESS_VID_PEER_4': 0x00000004,
|
||||
'NV_MMU_VER2_PTE_ADDRESS_VID_PEER_5': 0x00000005,
|
||||
'NV_MMU_VER2_PTE_ADDRESS_VID_PEER_6': 0x00000006,
|
||||
'NV_MMU_VER2_PTE_ADDRESS_VID_PEER_7': 0x00000007,
|
||||
'NV_MMU_VER2_PTE_ADDRESS_SHIFT': 0x0000000c,
|
||||
'NV_MMU_VER2_PTE__SIZE': 8,
|
||||
'NV_MMU_VER3_PDE': (None, None, {'is_pte': (0, 0), 'valid': (0, 0), 'aperture': (1, 2), 'pcf': (3, 5), 'address': (12, 51)}),
|
||||
'NV_MMU_VER3_PDE_IS_PTE_TRUE': 0x1,
|
||||
'NV_MMU_VER3_PDE_IS_PTE_FALSE': 0x0,
|
||||
'NV_MMU_VER3_PDE_VALID_TRUE': 0x1,
|
||||
'NV_MMU_VER3_PDE_VALID_FALSE': 0x0,
|
||||
'NV_MMU_VER3_PDE_APERTURE_INVALID': 0x00000000,
|
||||
'NV_MMU_VER3_PDE_APERTURE_VIDEO_MEMORY': 0x00000001,
|
||||
'NV_MMU_VER3_PDE_APERTURE_SYSTEM_COHERENT_MEMORY': 0x00000002,
|
||||
'NV_MMU_VER3_PDE_APERTURE_SYSTEM_NON_COHERENT_MEMORY': 0x00000003,
|
||||
'NV_MMU_VER3_PDE_PCF_VALID_CACHED_ATS_ALLOWED__OR__INVALID_ATS_ALLOWED': 0x00000000,
|
||||
'NV_MMU_VER3_PDE_PCF_VALID_CACHED_ATS_ALLOWED': 0x00000000,
|
||||
'NV_MMU_VER3_PDE_PCF_INVALID_ATS_ALLOWED': 0x00000000,
|
||||
'NV_MMU_VER3_PDE_PCF_VALID_UNCACHED_ATS_ALLOWED__OR__SPARSE_ATS_ALLOWED': 0x00000001,
|
||||
'NV_MMU_VER3_PDE_PCF_VALID_UNCACHED_ATS_ALLOWED': 0x00000001,
|
||||
'NV_MMU_VER3_PDE_PCF_SPARSE_ATS_ALLOWED': 0x00000001,
|
||||
'NV_MMU_VER3_PDE_PCF_VALID_CACHED_ATS_NOT_ALLOWED__OR__INVALID_ATS_NOT_ALLOWED': 0x00000002,
|
||||
'NV_MMU_VER3_PDE_PCF_VALID_CACHED_ATS_NOT_ALLOWED': 0x00000002,
|
||||
'NV_MMU_VER3_PDE_PCF_INVALID_ATS_NOT_ALLOWED': 0x00000002,
|
||||
'NV_MMU_VER3_PDE_PCF_VALID_UNCACHED_ATS_NOT_ALLOWED__OR__SPARSE_ATS_NOT_ALLOWED': 0x00000003,
|
||||
'NV_MMU_VER3_PDE_PCF_VALID_UNCACHED_ATS_NOT_ALLOWED': 0x00000003,
|
||||
'NV_MMU_VER3_PDE_PCF_SPARSE_ATS_NOT_ALLOWED': 0x00000003,
|
||||
'NV_MMU_VER3_PDE_ADDRESS_SHIFT': 0x0000000c,
|
||||
'NV_MMU_VER3_PDE__SIZE': 8,
|
||||
'NV_MMU_VER3_DUAL_PDE': (None, None, {'is_pte': (0, 0), 'valid': (0, 0), 'aperture_big': (1, 2), 'pcf_big': (3, 5), 'address_big': (8, 51), 'aperture_small': (65, 66), 'pcf_small': (67, 69), 'address_small': (76, 115)}),
|
||||
'NV_MMU_VER3_DUAL_PDE_IS_PTE_TRUE': 0x1,
|
||||
'NV_MMU_VER3_DUAL_PDE_IS_PTE_FALSE': 0x0,
|
||||
'NV_MMU_VER3_DUAL_PDE_VALID_TRUE': 0x1,
|
||||
'NV_MMU_VER3_DUAL_PDE_VALID_FALSE': 0x0,
|
||||
'NV_MMU_VER3_DUAL_PDE_APERTURE_BIG_INVALID': 0x00000000,
|
||||
'NV_MMU_VER3_DUAL_PDE_APERTURE_BIG_VIDEO_MEMORY': 0x00000001,
|
||||
'NV_MMU_VER3_DUAL_PDE_APERTURE_BIG_SYSTEM_COHERENT_MEMORY': 0x00000002,
|
||||
'NV_MMU_VER3_DUAL_PDE_APERTURE_BIG_SYSTEM_NON_COHERENT_MEMORY': 0x00000003,
|
||||
'NV_MMU_VER3_DUAL_PDE_PCF_BIG_VALID_CACHED_ATS_ALLOWED__OR__INVALID_ATS_ALLOWED': 0x00000000,
|
||||
'NV_MMU_VER3_DUAL_PDE_PCF_BIG_VALID_CACHED_ATS_ALLOWED': 0x00000000,
|
||||
'NV_MMU_VER3_DUAL_PDE_PCF_BIG_INVALID_ATS_ALLOWED': 0x00000000,
|
||||
'NV_MMU_VER3_DUAL_PDE_PCF_BIG_VALID_UNCACHED_ATS_ALLOWED__OR__SPARSE_ATS_ALLOWED': 0x00000001,
|
||||
'NV_MMU_VER3_DUAL_PDE_PCF_BIG_VALID_UNCACHED_ATS_ALLOWED': 0x00000001,
|
||||
'NV_MMU_VER3_DUAL_PDE_PCF_BIG_SPARSE_ATS_ALLOWED': 0x00000001,
|
||||
'NV_MMU_VER3_DUAL_PDE_PCF_BIG_VALID_CACHED_ATS_NOT_ALLOWED__OR__INVALID_ATS_NOT_ALLOWED': 0x00000002,
|
||||
'NV_MMU_VER3_DUAL_PDE_PCF_BIG_VALID_CACHED_ATS_NOT_ALLOWED': 0x00000002,
|
||||
'NV_MMU_VER3_DUAL_PDE_PCF_BIG_INVALID_ATS_NOT_ALLOWED': 0x00000002,
|
||||
'NV_MMU_VER3_DUAL_PDE_PCF_BIG_VALID_UNCACHED_ATS_NOT_ALLOWED__OR__SPARSE_ATS_NOT_ALLOWED': 0x00000003,
|
||||
'NV_MMU_VER3_DUAL_PDE_PCF_BIG_VALID_UNCACHED_ATS_NOT_ALLOWED': 0x00000003,
|
||||
'NV_MMU_VER3_DUAL_PDE_PCF_BIG_SPARSE_ATS_NOT_ALLOWED': 0x00000003,
|
||||
'NV_MMU_VER3_DUAL_PDE_APERTURE_SMALL_INVALID': 0x00000000,
|
||||
'NV_MMU_VER3_DUAL_PDE_APERTURE_SMALL_VIDEO_MEMORY': 0x00000001,
|
||||
'NV_MMU_VER3_DUAL_PDE_APERTURE_SMALL_SYSTEM_COHERENT_MEMORY': 0x00000002,
|
||||
'NV_MMU_VER3_DUAL_PDE_APERTURE_SMALL_SYSTEM_NON_COHERENT_MEMORY': 0x00000003,
|
||||
'NV_MMU_VER3_DUAL_PDE_PCF_SMALL_VALID_CACHED_ATS_ALLOWED__OR__INVALID_ATS_ALLOWED': 0x00000000,
|
||||
'NV_MMU_VER3_DUAL_PDE_PCF_SMALL_VALID_CACHED_ATS_ALLOWED': 0x00000000,
|
||||
'NV_MMU_VER3_DUAL_PDE_PCF_SMALL_INVALID_ATS_ALLOWED': 0x00000000,
|
||||
'NV_MMU_VER3_DUAL_PDE_PCF_SMALL_VALID_UNCACHED_ATS_ALLOWED__OR__SPARSE_ATS_ALLOWED': 0x00000001,
|
||||
'NV_MMU_VER3_DUAL_PDE_PCF_SMALL_VALID_UNCACHED_ATS_ALLOWED': 0x00000001,
|
||||
'NV_MMU_VER3_DUAL_PDE_PCF_SMALL_SPARSE_ATS_ALLOWED': 0x00000001,
|
||||
'NV_MMU_VER3_DUAL_PDE_PCF_SMALL_VALID_CACHED_ATS_NOT_ALLOWED__OR__INVALID_ATS_NOT_ALLOWED': 0x00000002,
|
||||
'NV_MMU_VER3_DUAL_PDE_PCF_SMALL_VALID_CACHED_ATS_NOT_ALLOWED': 0x00000002,
|
||||
'NV_MMU_VER3_DUAL_PDE_PCF_SMALL_INVALID_ATS_NOT_ALLOWED': 0x00000002,
|
||||
'NV_MMU_VER3_DUAL_PDE_PCF_SMALL_VALID_UNCACHED_ATS_NOT_ALLOWED__OR__SPARSE_ATS_NOT_ALLOWED': 0x00000003,
|
||||
'NV_MMU_VER3_DUAL_PDE_PCF_SMALL_VALID_UNCACHED_ATS_NOT_ALLOWED': 0x00000003,
|
||||
'NV_MMU_VER3_DUAL_PDE_PCF_SMALL_SPARSE_ATS_NOT_ALLOWED': 0x00000003,
|
||||
'NV_MMU_VER3_DUAL_PDE_ADDRESS_SHIFT': 0x0000000c,
|
||||
'NV_MMU_VER3_DUAL_PDE_ADDRESS_BIG_SHIFT': 8,
|
||||
'NV_MMU_VER3_DUAL_PDE__SIZE': 16,
|
||||
'NV_MMU_VER3_PTE': (None, None, {'valid': (0, 0), 'aperture': (1, 2), 'pcf': (3, 7), 'kind': (8, 11), 'address': (12, 51), 'address_sys': (12, 51), 'address_peer': (12, 51), 'address_vid': (12, 39), 'peer_id': ((64-3), 63)}),
|
||||
'NV_MMU_VER3_PTE_VALID_TRUE': 0x1,
|
||||
'NV_MMU_VER3_PTE_VALID_FALSE': 0x0,
|
||||
'NV_MMU_VER3_PTE_APERTURE_VIDEO_MEMORY': 0x00000000,
|
||||
'NV_MMU_VER3_PTE_APERTURE_PEER_MEMORY': 0x00000001,
|
||||
'NV_MMU_VER3_PTE_APERTURE_SYSTEM_COHERENT_MEMORY': 0x00000002,
|
||||
'NV_MMU_VER3_PTE_APERTURE_SYSTEM_NON_COHERENT_MEMORY': 0x00000003,
|
||||
'NV_MMU_VER3_PTE_PCF_INVALID': 0x00000000,
|
||||
'NV_MMU_VER3_PTE_PCF_SPARSE': 0x00000001,
|
||||
'NV_MMU_VER3_PTE_PCF_MAPPING_NOWHERE': 0x00000002,
|
||||
'NV_MMU_VER3_PTE_PCF_NO_VALID_4KB_PAGE': 0x00000003,
|
||||
'NV_MMU_VER3_PTE_PCF_REGULAR_RW_ATOMIC_CACHED_ACE': 0x00000000,
|
||||
'NV_MMU_VER3_PTE_PCF_REGULAR_RW_ATOMIC_UNCACHED_ACE': 0x00000001,
|
||||
'NV_MMU_VER3_PTE_PCF_PRIVILEGE_RW_ATOMIC_CACHED_ACE': 0x00000002,
|
||||
'NV_MMU_VER3_PTE_PCF_PRIVILEGE_RW_ATOMIC_UNCACHED_ACE': 0x00000003,
|
||||
'NV_MMU_VER3_PTE_PCF_REGULAR_RO_ATOMIC_CACHED_ACE': 0x00000004,
|
||||
'NV_MMU_VER3_PTE_PCF_REGULAR_RO_ATOMIC_UNCACHED_ACE': 0x00000005,
|
||||
'NV_MMU_VER3_PTE_PCF_PRIVILEGE_RO_ATOMIC_CACHED_ACE': 0x00000006,
|
||||
'NV_MMU_VER3_PTE_PCF_PRIVILEGE_RO_ATOMIC_UNCACHED_ACE': 0x00000007,
|
||||
'NV_MMU_VER3_PTE_PCF_REGULAR_RW_NO_ATOMIC_CACHED_ACE': 0x00000008,
|
||||
'NV_MMU_VER3_PTE_PCF_REGULAR_RW_NO_ATOMIC_UNCACHED_ACE': 0x00000009,
|
||||
'NV_MMU_VER3_PTE_PCF_PRIVILEGE_RW_NO_ATOMIC_CACHED_ACE': 0x0000000A,
|
||||
'NV_MMU_VER3_PTE_PCF_PRIVILEGE_RW_NO_ATOMIC_UNCACHED_ACE': 0x0000000B,
|
||||
'NV_MMU_VER3_PTE_PCF_REGULAR_RO_NO_ATOMIC_CACHED_ACE': 0x0000000C,
|
||||
'NV_MMU_VER3_PTE_PCF_REGULAR_RO_NO_ATOMIC_UNCACHED_ACE': 0x0000000D,
|
||||
'NV_MMU_VER3_PTE_PCF_PRIVILEGE_RO_NO_ATOMIC_CACHED_ACE': 0x0000000E,
|
||||
'NV_MMU_VER3_PTE_PCF_PRIVILEGE_RO_NO_ATOMIC_UNCACHED_ACE': 0x0000000F,
|
||||
'NV_MMU_VER3_PTE_PCF_REGULAR_RW_ATOMIC_CACHED_ACD': 0x00000010,
|
||||
'NV_MMU_VER3_PTE_PCF_REGULAR_RW_ATOMIC_UNCACHED_ACD': 0x00000011,
|
||||
'NV_MMU_VER3_PTE_PCF_PRIVILEGE_RW_ATOMIC_CACHED_ACD': 0x00000012,
|
||||
'NV_MMU_VER3_PTE_PCF_PRIVILEGE_RW_ATOMIC_UNCACHED_ACD': 0x00000013,
|
||||
'NV_MMU_VER3_PTE_PCF_REGULAR_RO_ATOMIC_CACHED_ACD': 0x00000014,
|
||||
'NV_MMU_VER3_PTE_PCF_REGULAR_RO_ATOMIC_UNCACHED_ACD': 0x00000015,
|
||||
'NV_MMU_VER3_PTE_PCF_PRIVILEGE_RO_ATOMIC_CACHED_ACD': 0x00000016,
|
||||
'NV_MMU_VER3_PTE_PCF_PRIVILEGE_RO_ATOMIC_UNCACHED_ACD': 0x00000017,
|
||||
'NV_MMU_VER3_PTE_PCF_REGULAR_RW_NO_ATOMIC_CACHED_ACD': 0x00000018,
|
||||
'NV_MMU_VER3_PTE_PCF_REGULAR_RW_NO_ATOMIC_UNCACHED_ACD': 0x00000019,
|
||||
'NV_MMU_VER3_PTE_PCF_PRIVILEGE_RW_NO_ATOMIC_CACHED_ACD': 0x0000001A,
|
||||
'NV_MMU_VER3_PTE_PCF_PRIVILEGE_RW_NO_ATOMIC_UNCACHED_ACD': 0x0000001B,
|
||||
'NV_MMU_VER3_PTE_PCF_REGULAR_RO_NO_ATOMIC_CACHED_ACD': 0x0000001C,
|
||||
'NV_MMU_VER3_PTE_PCF_REGULAR_RO_NO_ATOMIC_UNCACHED_ACD': 0x0000001D,
|
||||
'NV_MMU_VER3_PTE_PCF_PRIVILEGE_RO_NO_ATOMIC_CACHED_ACD': 0x0000001E,
|
||||
'NV_MMU_VER3_PTE_PCF_PRIVILEGE_RO_NO_ATOMIC_UNCACHED_ACD': 0x0000001F,
|
||||
'NV_MMU_VER3_PTE_PEER_ID_0': 0x00000000,
|
||||
'NV_MMU_VER3_PTE_PEER_ID_1': 0x00000001,
|
||||
'NV_MMU_VER3_PTE_PEER_ID_2': 0x00000002,
|
||||
'NV_MMU_VER3_PTE_PEER_ID_3': 0x00000003,
|
||||
'NV_MMU_VER3_PTE_PEER_ID_4': 0x00000004,
|
||||
'NV_MMU_VER3_PTE_PEER_ID_5': 0x00000005,
|
||||
'NV_MMU_VER3_PTE_PEER_ID_6': 0x00000006,
|
||||
'NV_MMU_VER3_PTE_PEER_ID_7': 0x00000007,
|
||||
'NV_MMU_VER3_PTE_ADDRESS_SHIFT': 0x0000000c,
|
||||
'NV_MMU_VER3_PTE__SIZE': 8,
|
||||
'NV_MMU_CLIENT': (None, None, {'kind': (0, 2)}),
|
||||
'NV_MMU_CLIENT_KIND_Z16': 0x1,
|
||||
'NV_MMU_CLIENT_KIND_S8': 0x2,
|
||||
'NV_MMU_CLIENT_KIND_S8Z24': 0x3,
|
||||
'NV_MMU_CLIENT_KIND_ZF32_X24S8': 0x4,
|
||||
'NV_MMU_CLIENT_KIND_Z24S8': 0x5,
|
||||
'NV_MMU_CLIENT_KIND_GENERIC_MEMORY': 0x6,
|
||||
'NV_MMU_CLIENT_KIND_INVALID': 0x7,
|
||||
}
|
||||
@@ -0,0 +1,14 @@
|
||||
ga102 = {
|
||||
'NV_FALCON2_GSP_BASE': 0x00111000,
|
||||
'NV_PRISCV_RISCV_IRQMASK': (0x1000, 0x00000528, {}),
|
||||
'NV_PRISCV_RISCV_IRQDEST': (0x1000, 0x0000052c, {}),
|
||||
'NV_PRISCV_RISCV_CPUCTL': (0x1000, 0x00000388, {'active_stat': (7, 7), 'halted': (4, 4)}),
|
||||
'NV_PRISCV_RISCV_CPUCTL_ACTIVE_STAT_ACTIVE': 0x00000001,
|
||||
'NV_PRISCV_RISCV_BCR_CTRL': (0x1000, 0x00000668, {'valid': (0, 0), 'core_select': (4, 4), 'brfetch': (8, 8)}),
|
||||
'NV_PRISCV_RISCV_BCR_CTRL_VALID_TRUE': 0x00000001,
|
||||
'NV_PRISCV_RISCV_BCR_CTRL_VALID_FALSE': 0x00000000,
|
||||
'NV_PRISCV_RISCV_BCR_CTRL_CORE_SELECT_FALCON': 0x00000000,
|
||||
'NV_PRISCV_RISCV_BCR_CTRL_CORE_SELECT_RISCV': 0x00000001,
|
||||
'NV_PRISCV_RISCV_BCR_CTRL_BRFETCH_TRUE': 0x00000001,
|
||||
'NV_PRISCV_RISCV_BCR_CTRL_BRFETCH_FALSE': 0x00000000,
|
||||
}
|
||||
@@ -0,0 +1,7 @@
|
||||
ga102 = {
|
||||
'NV_PSEC_FALCON_ENGINE': (0x0, 0x008403c0, {'reset': (0, 0)}),
|
||||
'NV_PSEC_FALCON_ENGINE_RESET_TRUE': 0x00000001,
|
||||
'NV_PSEC_FALCON_ENGINE_RESET_FALSE': 0x00000000,
|
||||
'NV_PSEC_MAILBOX__SIZE_1': 4,
|
||||
'NV_PSEC_MAILBOX_DATA_INIT': 0x00000000,
|
||||
}
|
||||
@@ -0,0 +1,4 @@
|
||||
gb202 = {
|
||||
'NV_THERM_I2CS_SCRATCH': (0x0, 0x00ad00bc, {'data': (0, 31)}),
|
||||
'NV_THERM_I2CS_SCRATCH_DATA_INIT': 0x00000000,
|
||||
}
|
||||
246
tinygrad_repo/tinygrad/runtime/autogen/nv_regs/dev_vm.py
Normal file
246
tinygrad_repo/tinygrad/runtime/autogen/nv_regs/dev_vm.py
Normal file
@@ -0,0 +1,246 @@
|
||||
tu102 = {
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_L2_SYSMEM_INVALIDATE': (0xB80000, 0x00000F00, {}),
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_L2_PEERMEM_INVALIDATE': (0xB80000, 0x00000F04, {}),
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP': (0xB80000, lambda i: (0x1600+(i)*4), {'value': (0, 31), 'en_set_value': (0, 31), 'en_clear_value': (0, 31)}),
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP__SIZE_1': 1,
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_SUBTREE': (0xB80000, lambda i: (i), {}),
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_SUBTREE__SIZE_1': 64,
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_SUBTREE_INTR_PENDING': 1,
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_SUBTREE_INTR_NOT_PENDING': 0,
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_SET': (0xB80000, lambda i: (0x1608+(i)*4), {'value': (0, 31)}),
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_SET__SIZE_1': 1,
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_SET_SUBTREE': (0xB80000, lambda i: (i), {}),
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_SET_SUBTREE__SIZE_1': 64,
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_SET_SUBTREE_ENABLE': 1,
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_SET_SUBTREE_ENABLED': 1,
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_SET_SUBTREE_DISABLED': 0,
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_CLEAR': (0xB80000, lambda i: (0x1610+(i)*4), {'value': (0, 31)}),
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_CLEAR__SIZE_1': 1,
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_CLEAR_SUBTREE': (0xB80000, lambda i: (i), {}),
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_CLEAR_SUBTREE__SIZE_1': 64,
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_CLEAR_SUBTREE_DISABLE': 1,
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_CLEAR_SUBTREE_ENABLED': 1,
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_CLEAR_SUBTREE_DISABLED': 0,
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF': (0xB80000, lambda i: (0x1000+(i)*4), {'value': (0, 31), 'en_set_value': (0, 31), 'en_clear_value': (0, 31), 'trigger_vector': (0, 11)}),
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF__SIZE_1': 8,
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF_VALUE_INIT': 0x00000000,
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF_EN_SET': (0xB80000, lambda i: (0x1200+(i)*4), {'value': (0, 31)}),
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF_EN_SET__SIZE_1': 8,
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF_EN_SET_VALUE_INIT': 0x00000000,
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF_EN_CLEAR': (0xB80000, lambda i: (0x1400+(i)*4), {'value': (0, 31)}),
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF_EN_CLEAR__SIZE_1': 8,
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF_EN_CLEAR_VALUE_INIT': 0x00000000,
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF_TRIGGER': 0x00001640,
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_TIMER': (0xB80000, 0x2300, {'nsec': (0, 31), 'usec': (10, 31)}),
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_TIMER_USEC_INIT': 0x0,
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_MMU_NON_REPLAY_FAULT_BUFFER': (0xB80000, 0, {}),
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_MMU_REPLAY_FAULT_BUFFER': (0xB80000, 1, {}),
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_LO': (0xB80000, lambda i: (0x00003000+(i)*32), {}),
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_LO__SIZE_1': 2,
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_HI': (0xB80000, lambda i: (0x00003004+(i)*32), {}),
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_HI__SIZE_1': 2,
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_GET': (0xB80000, lambda i: (0x00003008+(i)*32), {'ptr': (0, 19), 'getptr_corrupted': (30, 30), 'overflow': (31, 31)}),
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_GET__SIZE_1': 2,
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_GET_PTR_RESET': 0x00000000,
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_GET_GETPTR_CORRUPTED_NO': 0x00000000,
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_GET_GETPTR_CORRUPTED_YES': 0x00000001,
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_GET_GETPTR_CORRUPTED_CLEAR': 0x00000001,
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_GET_OVERFLOW_NO': 0x00000000,
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_GET_OVERFLOW_YES': 0x00000001,
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_GET_OVERFLOW_CLEAR': 0x00000001,
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_PUT': (0xB80000, lambda i: (0x0000300C+(i)*32), {'ptr': (0, 19), 'getptr_corrupted': (30, 30), 'overflow': (31, 31)}),
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_PUT__SIZE_1': 2,
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_PUT_PTR_RESET': 0x00000000,
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_PUT_GETPTR_CORRUPTED_NO': 0x00000000,
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_PUT_GETPTR_CORRUPTED_YES': 0x00000001,
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_PUT_OVERFLOW_NO': 0x00000000,
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_PUT_OVERFLOW_YES': 0x00000001,
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_SIZE': (0xB80000, lambda i: (0x00003010+(i)*32), {'val': (0, 19), 'overflow_intr': (29, 29), 'set_default': (30, 30), 'enable': (31, 31)}),
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_SIZE__SIZE_1': 2,
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_SIZE_VAL_RESET': 0x00000000,
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_SIZE_OVERFLOW_INTR_DISABLE': 0x00000000,
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_SIZE_OVERFLOW_INTR_ENABLE': 0x00000001,
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_SIZE_SET_DEFAULT_NO': 0x00000000,
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_SIZE_SET_DEFAULT_YES': 0x00000001,
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_SIZE_ENABLE_FALSE': 0x00000000,
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_SIZE_ENABLE_TRUE': 0x00000001,
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_MMU_PAGE_FAULT_CTRL': (0xB80000, 0x00003070, {}),
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_ADDR_LO': (0xB80000, 0x00003080, {}),
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_ADDR_HI': (0xB80000, 0x00003084, {}),
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_INST_LO': (0xB80000, 0x00003088, {}),
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_INST_HI': (0xB80000, 0x0000308C, {}),
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_INFO': (0xB80000, 0x00003090, {}),
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_STATUS': (0xB80000, 0x00003094, {}),
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_PDB': (0xB80000, 0x000030A0, {'aperture': (1, 1), 'addr': (4, 31)}),
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_PDB_APERTURE_INIT': 0x00000000,
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_PDB_APERTURE_VID_MEM': 0x00000000,
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_PDB_APERTURE_SYS_MEM': 0x00000001,
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_PDB_ADDR_INIT': 0x00000000,
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_PDB_ADDR_ALIGNMENT': 0x0000000c,
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_UPPER_PDB': (0xB80000, 0x000030A4, {'addr': (0, 19)}),
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_UPPER_PDB_ADDR_INIT': 0x00000000,
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE': (0xB80000, 0x000030B0, {'pdb_aperture': (1, 1), 'pdb_addr': (4, 31), 'upper_pdb_addr': (0, 19), 'all_va': (0, 0), 'all_pdb': (1, 1), 'hubtlb_only': (2, 2), 'replay': (3, 5), 'sys_membar': (6, 6), 'ack': (7, 8), 'cancel_client_id': (9, 14), 'cancel_gpc_id': (15, 19), 'cancel_client_type': (20, 20), 'use_pasid': (21, 21), 'use_size': (22, 22), 'prop_flush': (23, 23), 'cache_level': (24, 26), 'trigger': (31, 31)}),
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_ALL_VA_FALSE': 0x00000000,
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_ALL_VA_TRUE': 0x00000001,
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_ALL_PDB_FALSE': 0x00000000,
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_ALL_PDB_TRUE': 0x00000001,
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_HUBTLB_ONLY_FALSE': 0x00000000,
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_HUBTLB_ONLY_TRUE': 0x00000001,
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_REPLAY_NONE': 0x00000000,
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_REPLAY_START': 0x00000001,
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_REPLAY_START_ACK_ALL': 0x00000002,
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_REPLAY_CANCEL_TARGETED': 0x00000003,
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_REPLAY_CANCEL_GLOBAL': 0x00000004,
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_REPLAY_CANCEL_VA_GLOBAL': 0x00000005,
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_SYS_MEMBAR_FALSE': 0x00000000,
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_SYS_MEMBAR_TRUE': 0x00000001,
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_ACK_NONE_REQUIRED': 0x00000000,
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_ACK_INTRANODE': 0x00000002,
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_ACK_GLOBALLY': 0x00000001,
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_CANCEL_CLIENT_TYPE_GPC': 0x00000000,
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_CANCEL_CLIENT_TYPE_HUB': 0x00000001,
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_USE_PASID_FALSE': 0x00000000,
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_USE_PASID_TRUE': 0x00000001,
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_USE_SIZE_FALSE': 0x00000000,
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_USE_SIZE_TRUE': 0x00000001,
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_PROP_FLUSH_FALSE': 0x00000000,
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_PROP_FLUSH_TRUE': 0x00000001,
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_CACHE_LEVEL_ALL': 0x00000000,
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_CACHE_LEVEL_PTE_ONLY': 0x00000001,
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_CACHE_LEVEL_UP_TO_PDE0': 0x00000002,
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_CACHE_LEVEL_UP_TO_PDE1': 0x00000003,
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_CACHE_LEVEL_UP_TO_PDE2': 0x00000004,
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_CACHE_LEVEL_UP_TO_PDE3': 0x00000005,
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_CACHE_LEVEL_UP_TO_PDE4': 0x00000006,
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_CACHE_LEVEL_UP_TO_PDE5': 0x00000007,
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_CACHE_LEVEL_CANCEL_READ': 0x00000000,
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_CACHE_LEVEL_CANCEL_WRITE': 0x00000001,
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_CACHE_LEVEL_CANCEL_ATOMIC_STRONG': 0x00000002,
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_CACHE_LEVEL_CANCEL_RSVRVD': 0x00000003,
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_CACHE_LEVEL_CANCEL_ATOMIC_WEAK': 0x00000004,
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_CACHE_LEVEL_CANCEL_ATOMIC_ALL': 0x00000005,
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_CACHE_LEVEL_CANCEL_WRITE_AND_ATOMIC': 0x00000006,
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_CACHE_LEVEL_CANCEL_ALL': 0x00000007,
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_TRIGGER_FALSE': 0x00000000,
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_TRIGGER_TRUE': 0x00000001,
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_CONFIG': (0xB80000, 0x00003100, {'threshold': (0, 15), 'mimc_granularity': (16, 17), 'momc_granularity': (18, 19)}),
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_CONFIG_THRESHOLD_INIT': 0x00000080,
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_CONFIG_MIMC_GRANULARITY_INIT': 0x00000000,
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_CONFIG_MIMC_GRANULARITY_64K': 0x00000000,
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_CONFIG_MIMC_GRANULARITY_2M': 0x00000001,
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_CONFIG_MIMC_GRANULARITY_16M': 0x00000002,
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_CONFIG_MIMC_GRANULARITY_16G': 0x00000003,
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_CONFIG_MOMC_GRANULARITY_INIT': 0x00000000,
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_CONFIG_MOMC_GRANULARITY_64K': 0x00000000,
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_CONFIG_MOMC_GRANULARITY_2M': 0x00000001,
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_CONFIG_MOMC_GRANULARITY_16M': 0x00000002,
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_CONFIG_MOMC_GRANULARITY_16G': 0x00000003,
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_LO': (0xB80000, 0x00003108, {'en': (0, 0)}),
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_LO_EN_FALSE': 0x00000000,
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_LO_EN_TRUE': 0x00000001,
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_HI': (0xB80000, 0x0000310C, {}),
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_SIZE': (0xB80000, 0x00003110, {}),
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_GET': (0xB80000, 0x00003114, {}),
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_PUT': (0xB80000, 0x00003118, {}),
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_INFO': (0xB80000, 0x0000311C, {'full': (0, 0), 'pushed': (1, 1), 'write_nack': (24, 24)}),
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_INFO_FULL_FALSE': 0x0,
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_INFO_FULL_TRUE': 0x1,
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_INFO_PUSHED_FALSE': 0x0,
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_INFO_PUSHED_TRUE': 0x1,
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_INFO_WRITE_NACK_FALSE': 0x0,
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_INFO_WRITE_NACK_TRUE': 0x1,
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_MSIX_TABLE_ADDR_LO': (0xB80000, lambda i: (0x00010000+(i)*16), {}),
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_MSIX_TABLE_ADDR_LO__SIZE_1': 6,
|
||||
'NV_VIRTUAL_FUNCTION_TIME_0': (0xB80000, 0x30080, {'nsec': (5, 31)}),
|
||||
'NV_VIRTUAL_FUNCTION_TIME_1': (0xB80000, 0x30084, {'nsec': (0, 28)}),
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_DOORBELL': (0xB80000, 0x2200, {}),
|
||||
'NV_VIRTUAL_FUNCTION_DOORBELL': (0xB80000, 0x30090, {}),
|
||||
'NV_VIRTUAL_FUNCTION_ERR_CONT': (0xB80000, 0x30094, {}),
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_BAR1_BLOCK': (0xB80000, 0x00000F40, {'map': (0, 29), 'ptr': (0, 27), 'target': (28, 29), 'mode': (31, 31)}),
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_BAR1_BLOCK_PTR_0': 0x00000000,
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_BAR1_BLOCK_TARGET_VID_MEM': 0x00000000,
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_BAR1_BLOCK_TARGET_SYS_MEM_COHERENT': 0x00000002,
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_BAR1_BLOCK_TARGET_SYS_MEM_NONCOHERENT': 0x00000003,
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_BAR1_BLOCK_MODE_PHYSICAL': 0x00000000,
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_BAR1_BLOCK_MODE_VIRTUAL': 0x00000001,
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_BAR2_BLOCK': (0xB80000, 0x00000F48, {'map': (0, 29), 'ptr': (0, 27), 'target': (28, 29), 'debug_cya': (30, 30), 'mode': (31, 31)}),
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_BAR2_BLOCK_PTR_0': 0x00000000,
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_BAR2_BLOCK_TARGET_VID_MEM': 0x00000000,
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_BAR2_BLOCK_TARGET_SYS_MEM_COHERENT': 0x00000002,
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_BAR2_BLOCK_TARGET_SYS_MEM_NONCOHERENT': 0x00000003,
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_BAR2_BLOCK_DEBUG_CYA_OFF': 0x00000001,
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_BAR2_BLOCK_DEBUG_CYA_ON': 0x00000000,
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_BAR2_BLOCK_DEBUG_CYA_INIT': 0x00000001,
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_BAR2_BLOCK_MODE_PHYSICAL': 0x00000000,
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_BAR2_BLOCK_MODE_VIRTUAL': 0x00000001,
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_BIND_STATUS': (0xB80000, 0x00000F50, {'bar1_pending': (0, 0), 'bar1_outstanding': (1, 1), 'bar2_pending': (2, 2), 'bar2_outstanding': (3, 3)}),
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_BIND_STATUS_BAR1_PENDING_EMPTY': 0x00000000,
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_BIND_STATUS_BAR1_PENDING_BUSY': 0x00000001,
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_BIND_STATUS_BAR1_OUTSTANDING_FALSE': 0x00000000,
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_BIND_STATUS_BAR1_OUTSTANDING_TRUE': 0x00000001,
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_BIND_STATUS_BAR2_PENDING_EMPTY': 0x00000000,
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_BIND_STATUS_BAR2_PENDING_BUSY': 0x00000001,
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_BIND_STATUS_BAR2_OUTSTANDING_FALSE': 0x00000000,
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_BIND_STATUS_BAR2_OUTSTANDING_TRUE': 0x00000001,
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_MSIX_TABLE_VECTOR_CONTROL': (0xB80000, lambda i: (0x0001000C+(i)*16), {'mask_bit': (0, 0)}),
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_MSIX_TABLE_VECTOR_CONTROL__SIZE_1': 6,
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_MSIX_TABLE_VECTOR_CONTROL_MASK_BIT_UNMASKED': 0x00000000,
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_MSIX_TABLE_VECTOR_CONTROL_MASK_BIT_MASKED': 0x00000001,
|
||||
}
|
||||
gh100 = {
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_FUNC_L2_SYSMEM_INVALIDATE': (0xB80000, 0x00000F10, {'token': (0, (31-1)), 'completed_token': (0, (31-1)), 'completed_status': (31, 31)}),
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_FUNC_L2_SYSMEM_INVALIDATE_COMPLETED': 0x00000F14,
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_FUNC_L2_SYSMEM_INVALIDATE_COMPLETED_STATUS_BUSY': 0x00000001,
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_FUNC_L2_PEERMEM_INVALIDATE': (0xB80000, 0x00000F18, {'token': (0, (31-1)), 'completed_token': (0, (31-1)), 'completed_status': (31, 31)}),
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_FUNC_L2_PEERMEM_INVALIDATE_COMPLETED': 0x00000F1C,
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_FUNC_L2_PEERMEM_INVALIDATE_COMPLETED_STATUS_BUSY': 0x00000001,
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR2_BLOCK_LOW_ADDR': (0xB80000, 0x00000F70, {'mode': (9, 9), 'map': (10, 31), 'bar2_pending': (0, 0), 'bar2_outstanding': (1, 1), 'target': (10, 11), 'ptr': (12, 31)}),
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR2_BLOCK_LOW_ADDR_MODE_PHYSICAL': 0x00000000,
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_SUBTREE': (0xB80000, lambda i: (i), {}),
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF__SIZE_1': (0xB80000, 16, {}),
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF_EN_SET__SIZE_1': (0xB80000, 16, {}),
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF_EN_CLEAR__SIZE_1': (0xB80000, 16, {}),
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_TIMER': (0xB80000, lambda i: (0x2300+(i)*4), {}),
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_TIMER__SIZE_1': 2,
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_MSIX_TABLE_ADDR_LO': (0xB80000, lambda i: (0x00010000+(i)*16), {}),
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_MSIX_TABLE_ADDR_HI': (0xB80000, lambda i: (0x00010004+(i)*16), {}),
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_MSIX_TABLE_DATA': (0xB80000, lambda i: (0x00010008+(i)*16), {}),
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_MSIX_TABLE_VECTOR_CONTROL': (0xB80000, lambda i: (0x0001000C+(i)*16), {}),
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_MSIX_TABLE_VECTOR_CONTROL__SIZE_1': 9,
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_LO': (0xB80000, 0x00003108, {'base': (12, 31)}),
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_HI': (0xB80000, 0x0000310C, {}),
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_DOORBELL': (0xB80000, 0x2200, {}),
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF': (0xB80000, lambda i: (0x1000+(i)*4), {'value': (0, 31), 'en_set_value': (0, 31), 'en_clear_value': (0, 31)}),
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF_VALUE_INIT': 0x00000000,
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF_EN_SET': (0xB80000, lambda i: (0x1200+(i)*4), {'value': (0, 31)}),
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF_EN_SET_VALUE_INIT': 0x00000000,
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF_EN_CLEAR': (0xB80000, lambda i: (0x1400+(i)*4), {'value': (0, 31)}),
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF_EN_CLEAR_VALUE_INIT': 0x00000000,
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_MMU_PAGE_FAULT_CTRL': (0xB80000, 0x00003070, {}),
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR1_BLOCK_LOW_ADDR': (0xB80000, 0x00000F60, {'map': (10, 31), 'bar1_pending': (0, 0), 'bar1_outstanding': (1, 1), 'mode': (9, 9), 'target': (10, 11), 'ptr': (12, 31)}),
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR1_BLOCK_LOW_ADDR_BAR1_PENDING_EMPTY': 0x00000000,
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR1_BLOCK_LOW_ADDR_BAR1_PENDING_BUSY': 0x00000001,
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR1_BLOCK_LOW_ADDR_BAR1_OUTSTANDING_FALSE': 0x00000000,
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR1_BLOCK_LOW_ADDR_BAR1_OUTSTANDING_TRUE': 0x00000001,
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR1_BLOCK_LOW_ADDR_MODE_PHYSICAL': 0x00000000,
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR1_BLOCK_LOW_ADDR_MODE_VIRTUAL': 0x00000001,
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR1_BLOCK_LOW_ADDR_TARGET_VID_MEM': 0x00000000,
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR1_BLOCK_LOW_ADDR_TARGET_SYS_MEM_COHERENT': 0x00000002,
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR1_BLOCK_LOW_ADDR_TARGET_SYS_MEM_NONCOHERENT': 0x00000003,
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR1_BLOCK_LOW_ADDR_PTR_0': 0x00000000,
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR1_BLOCK_HIGH_ADDR': (0xB80000, 0x00000F64, {'ptr': (0, 31)}),
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR1_BLOCK_HIGH_ADDR_PTR_0': 0x00000000,
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR1_BLOCK_PTR_SHIFT': (0xB80000, 12, {}),
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR2_BLOCK_LOW_ADDR_BAR2_PENDING_EMPTY': 0x00000000,
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR2_BLOCK_LOW_ADDR_BAR2_PENDING_BUSY': 0x00000001,
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR2_BLOCK_LOW_ADDR_BAR2_OUTSTANDING_FALSE': 0x00000000,
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR2_BLOCK_LOW_ADDR_BAR2_OUTSTANDING_TRUE': 0x00000001,
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR2_BLOCK_LOW_ADDR_MODE_VIRTUAL': 0x00000001,
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR2_BLOCK_LOW_ADDR_TARGET_VID_MEM': 0x00000000,
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR2_BLOCK_LOW_ADDR_TARGET_SYS_MEM_COHERENT': 0x00000002,
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR2_BLOCK_LOW_ADDR_TARGET_SYS_MEM_NONCOHERENT': 0x00000003,
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR2_BLOCK_LOW_ADDR_PTR_0': 0x00000000,
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR2_BLOCK_HIGH_ADDR': (0xB80000, 0x00000F74, {'ptr': (0, (52-33))}),
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR2_BLOCK_HIGH_ADDR_PTR_0': 0x00000000,
|
||||
'NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR2_BLOCK_PTR_SHIFT': (0xB80000, 12, {}),
|
||||
}
|
||||
75
tinygrad_repo/tinygrad/runtime/autogen/nv_regs/nv_ref.py
Normal file
75
tinygrad_repo/tinygrad/runtime/autogen/nv_regs/nv_ref.py
Normal file
@@ -0,0 +1,75 @@
|
||||
regs = {
|
||||
'NV_CONFIG_PCI_NV_0': 0x00000000,
|
||||
'NV_CONFIG_PCI_NV_0_VENDOR_ID_NVIDIA': 0x000010DE,
|
||||
'NV_CONFIG_PCI_NV_1': 0x00000004,
|
||||
'NV_CONFIG_PCI_NV_1_IO_SPACE_DISABLED': 0x00000000,
|
||||
'NV_CONFIG_PCI_NV_1_IO_SPACE_ENABLED': 0x00000001,
|
||||
'NV_CONFIG_PCI_NV_1_MEMORY_SPACE_DISABLED': 0x00000000,
|
||||
'NV_CONFIG_PCI_NV_1_MEMORY_SPACE_ENABLED': 0x00000001,
|
||||
'NV_CONFIG_PCI_NV_1_BUS_MASTER_DISABLED': 0x00000000,
|
||||
'NV_CONFIG_PCI_NV_1_BUS_MASTER_ENABLED': 0x00000001,
|
||||
'NV_CONFIG_PCI_NV_2': 0x00000008,
|
||||
'NV_CONFIG_PCI_NV_3': 0x0000000C,
|
||||
'NV_CONFIG_PCI_NV_3_LATENCY_TIMER_0_CLOCKS': 0x00000000,
|
||||
'NV_CONFIG_PCI_NV_3_LATENCY_TIMER_8_CLOCKS': 0x00000001,
|
||||
'NV_CONFIG_PCI_NV_3_LATENCY_TIMER_240_CLOCKS': 0x0000001E,
|
||||
'NV_CONFIG_PCI_NV_3_LATENCY_TIMER_248_CLOCKS': 0x0000001F,
|
||||
'NV_CONFIG_PCI_NV_4': 0x00000010,
|
||||
'NV_CONFIG_PCI_NV_5': 0x00000014,
|
||||
'NV_CONFIG_PCI_NV_5_ADDRESS_TYPE_64_BIT': 0x00000002,
|
||||
'NV_CONFIG_PCI_NV_6': 0x00000018,
|
||||
'NV_CONFIG_PCI_NV_11': 0x0000002C,
|
||||
'NV_CONFIG_PCI_NV_11_SUBSYSTEM_VENDOR_ID_NONE': 0x00000000,
|
||||
'NV_CONFIG_PCI_NV_11_SUBSYSTEM_ID_NONE': 0x00000000,
|
||||
'NV_CONFIG_PCI_NV_11_SUBSYSTEM_ID_TNT2PRO': 0x0000001f,
|
||||
'NV_CONFIG_PCI_NV_12': 0x00000030,
|
||||
'NV_CONFIG_PCI_NV_13': 0x00000034,
|
||||
'NV_CONFIG_PCI_NV_14': 0x00000038,
|
||||
'NV_CONFIG_PCI_NV_15': 0x0000003C,
|
||||
'NV_PMC_BOOT_0': (0x0, 0x00000000, {'minor_revision': (0, 3), 'major_revision': (4, 7), 'architecture_1': (8, 8), 'implementation': (20, 23), 'architecture_0': (24, 28)}),
|
||||
'NV_PMC_BOOT_0_IMPLEMENTATION_0': 0x00000000,
|
||||
'NV_PMC_BOOT_0_IMPLEMENTATION_1': 0x00000001,
|
||||
'NV_PMC_BOOT_0_IMPLEMENTATION_2': 0x00000002,
|
||||
'NV_PMC_BOOT_0_IMPLEMENTATION_3': 0x00000003,
|
||||
'NV_PMC_BOOT_0_IMPLEMENTATION_4': 0x00000004,
|
||||
'NV_PMC_BOOT_0_IMPLEMENTATION_5': 0x00000005,
|
||||
'NV_PMC_BOOT_0_IMPLEMENTATION_6': 0x00000006,
|
||||
'NV_PMC_BOOT_0_IMPLEMENTATION_7': 0x00000007,
|
||||
'NV_PMC_BOOT_0_IMPLEMENTATION_8': 0x00000008,
|
||||
'NV_PMC_BOOT_0_IMPLEMENTATION_9': 0x00000009,
|
||||
'NV_PMC_BOOT_0_IMPLEMENTATION_A': 0x0000000A,
|
||||
'NV_PMC_BOOT_0_IMPLEMENTATION_B': 0x0000000B,
|
||||
'NV_PMC_BOOT_0_IMPLEMENTATION_C': 0x0000000C,
|
||||
'NV_PMC_BOOT_0_IMPLEMENTATION_D': 0x0000000D,
|
||||
'NV_PMC_BOOT_0_IMPLEMENTATION_E': 0x0000000E,
|
||||
'NV_PMC_BOOT_0_IMPLEMENTATION_F': 0x0000000F,
|
||||
'NV_PMC_BOOT_0_ARCHITECTURE_TU100': 0x00000016,
|
||||
'NV_PMC_BOOT_0_ARCHITECTURE_TU110': 0x00000016,
|
||||
'NV_PMC_BOOT_0_ARCHITECTURE_GA100': 0x00000017,
|
||||
'NV_PMC_BOOT_0_ARCHITECTURE_GH100': 0x00000018,
|
||||
'NV_PMC_BOOT_0_ARCHITECTURE_AD100': 0x00000019,
|
||||
'NV_PMC_BOOT_0_ARCHITECTURE_GB100': 0x0000001A,
|
||||
'NV_PMC_BOOT_0_ARCHITECTURE_GB200': 0x0000001B,
|
||||
'NV_PMC_BOOT_1': (0x0, 0x00000004, {'vgpu8': (8, 8), 'vgpu16': (16, 16), 'vgpu': (16, 17)}),
|
||||
'NV_PMC_BOOT_1_VGPU8_REAL': 0x00000000,
|
||||
'NV_PMC_BOOT_1_VGPU8_VIRTUAL': 0x00000001,
|
||||
'NV_PMC_BOOT_1_VGPU16_REAL': 0x00000000,
|
||||
'NV_PMC_BOOT_1_VGPU16_VIRTUAL': 0x00000001,
|
||||
'NV_PMC_BOOT_1_VGPU_REAL': 0x00000000,
|
||||
'NV_PMC_BOOT_1_VGPU_PV': 0x00000001,
|
||||
'NV_PMC_BOOT_1_VGPU_VF': 0x00000002,
|
||||
'NV_PMC_BOOT_42': (0x0, 0x00000A00, {'minor_extended_revision': (8, 11), 'minor_revision': (12, 15), 'major_revision': (16, 19), 'implementation': (20, 23), 'architecture': (24, 29), 'chip_id': (20, 29)}),
|
||||
'NV_PMC_BOOT_42_ARCHITECTURE_GM100': 0x00000011,
|
||||
'NV_PMC_BOOT_42_ARCHITECTURE_GM200': 0x00000012,
|
||||
'NV_PMC_BOOT_42_ARCHITECTURE_GP100': 0x00000013,
|
||||
'NV_PMC_BOOT_42_ARCHITECTURE_GV100': 0x00000014,
|
||||
'NV_PMC_BOOT_42_ARCHITECTURE_GV110': 0x00000015,
|
||||
'NV_PMC_BOOT_42_ARCHITECTURE_TU100': 0x00000016,
|
||||
'NV_PMC_BOOT_42_ARCHITECTURE_GA100': 0x00000017,
|
||||
'NV_PMC_BOOT_42_ARCHITECTURE_GH100': 0x00000018,
|
||||
'NV_PMC_BOOT_42_ARCHITECTURE_AD100': 0x00000019,
|
||||
'NV_PMC_BOOT_42_ARCHITECTURE_GB100': 0x0000001A,
|
||||
'NV_PMC_BOOT_42_ARCHITECTURE_GB200': 0x0000001B,
|
||||
'NV_PMC_BOOT_42_ARCHITECTURE_AMODEL': 0x0000001F,
|
||||
'NV_PMC_BOOT_42_CHIP_ID_GA100': 0x00000170,
|
||||
}
|
||||
Reference in New Issue
Block a user