# mypy: disable-error-code="empty-body"
from __future__ import annotations
import ctypes
from typing import Literal, TypeAlias
from tinygrad.runtime.support.c import _IO, _IOW, _IOR, _IOWR
from tinygrad.runtime.support import c
@c.record
class struct_IP_BASE_INSTANCE(c.Struct):
  SIZE = 20
  segment: c.Array[ctypes.c_uint32, Literal[5]]
struct_IP_BASE_INSTANCE.register_fields([('segment', c.Array[ctypes.c_uint32, Literal[5]], 0)])
@c.record
class struct_IP_BASE(c.Struct):
  SIZE = 140
  instance: c.Array[struct_IP_BASE_INSTANCE, Literal[7]]
struct_IP_BASE.register_fields([('instance', c.Array[struct_IP_BASE_INSTANCE, Literal[7]], 0)])
MAX_INSTANCE = 7
MAX_SEGMENT = 5
ATHUB_BASE__INST0_SEG0 = 0x00000C00
ATHUB_BASE__INST0_SEG1 = 0x02408C00
ATHUB_BASE__INST0_SEG2 = 0
ATHUB_BASE__INST0_SEG3 = 0
ATHUB_BASE__INST0_SEG4 = 0
ATHUB_BASE__INST1_SEG0 = 0
ATHUB_BASE__INST1_SEG1 = 0
ATHUB_BASE__INST1_SEG2 = 0
ATHUB_BASE__INST1_SEG3 = 0
ATHUB_BASE__INST1_SEG4 = 0
ATHUB_BASE__INST2_SEG0 = 0
ATHUB_BASE__INST2_SEG1 = 0
ATHUB_BASE__INST2_SEG2 = 0
ATHUB_BASE__INST2_SEG3 = 0
ATHUB_BASE__INST2_SEG4 = 0
ATHUB_BASE__INST3_SEG0 = 0
ATHUB_BASE__INST3_SEG1 = 0
ATHUB_BASE__INST3_SEG2 = 0
ATHUB_BASE__INST3_SEG3 = 0
ATHUB_BASE__INST3_SEG4 = 0
ATHUB_BASE__INST4_SEG0 = 0
ATHUB_BASE__INST4_SEG1 = 0
ATHUB_BASE__INST4_SEG2 = 0
ATHUB_BASE__INST4_SEG3 = 0
ATHUB_BASE__INST4_SEG4 = 0
ATHUB_BASE__INST5_SEG0 = 0
ATHUB_BASE__INST5_SEG1 = 0
ATHUB_BASE__INST5_SEG2 = 0
ATHUB_BASE__INST5_SEG3 = 0
ATHUB_BASE__INST5_SEG4 = 0
ATHUB_BASE__INST6_SEG0 = 0
ATHUB_BASE__INST6_SEG1 = 0
ATHUB_BASE__INST6_SEG2 = 0
ATHUB_BASE__INST6_SEG3 = 0
ATHUB_BASE__INST6_SEG4 = 0
CLK_BASE__INST0_SEG0 = 0x00016C00
CLK_BASE__INST0_SEG1 = 0x02401800
CLK_BASE__INST0_SEG2 = 0
CLK_BASE__INST0_SEG3 = 0
CLK_BASE__INST0_SEG4 = 0
CLK_BASE__INST1_SEG0 = 0x00016E00
CLK_BASE__INST1_SEG1 = 0x02401C00
CLK_BASE__INST1_SEG2 = 0
CLK_BASE__INST1_SEG3 = 0
CLK_BASE__INST1_SEG4 = 0
CLK_BASE__INST2_SEG0 = 0x00017000
CLK_BASE__INST2_SEG1 = 0x02402000
CLK_BASE__INST2_SEG2 = 0
CLK_BASE__INST2_SEG3 = 0
CLK_BASE__INST2_SEG4 = 0
CLK_BASE__INST3_SEG0 = 0x00017200
CLK_BASE__INST3_SEG1 = 0x02402400
CLK_BASE__INST3_SEG2 = 0
CLK_BASE__INST3_SEG3 = 0
CLK_BASE__INST3_SEG4 = 0
CLK_BASE__INST4_SEG0 = 0x0001B000
CLK_BASE__INST4_SEG1 = 0x0242D800
CLK_BASE__INST4_SEG2 = 0
CLK_BASE__INST4_SEG3 = 0
CLK_BASE__INST4_SEG4 = 0
CLK_BASE__INST5_SEG0 = 0x0001B200
CLK_BASE__INST5_SEG1 = 0x0242DC00
CLK_BASE__INST5_SEG2 = 0
CLK_BASE__INST5_SEG3 = 0
CLK_BASE__INST5_SEG4 = 0
CLK_BASE__INST6_SEG0 = 0x0001B400
CLK_BASE__INST6_SEG1 = 0x0242E000
CLK_BASE__INST6_SEG2 = 0
CLK_BASE__INST6_SEG3 = 0
CLK_BASE__INST6_SEG4 = 0
DF_BASE__INST0_SEG0 = 0x00007000
DF_BASE__INST0_SEG1 = 0x0240B800
DF_BASE__INST0_SEG2 = 0
DF_BASE__INST0_SEG3 = 0
DF_BASE__INST0_SEG4 = 0
DF_BASE__INST1_SEG0 = 0
DF_BASE__INST1_SEG1 = 0
DF_BASE__INST1_SEG2 = 0
DF_BASE__INST1_SEG3 = 0
DF_BASE__INST1_SEG4 = 0
DF_BASE__INST2_SEG0 = 0
DF_BASE__INST2_SEG1 = 0
DF_BASE__INST2_SEG2 = 0
DF_BASE__INST2_SEG3 = 0
DF_BASE__INST2_SEG4 = 0
DF_BASE__INST3_SEG0 = 0
DF_BASE__INST3_SEG1 = 0
DF_BASE__INST3_SEG2 = 0
DF_BASE__INST3_SEG3 = 0
DF_BASE__INST3_SEG4 = 0
DF_BASE__INST4_SEG0 = 0
DF_BASE__INST4_SEG1 = 0
DF_BASE__INST4_SEG2 = 0
DF_BASE__INST4_SEG3 = 0
DF_BASE__INST4_SEG4 = 0
DF_BASE__INST5_SEG0 = 0
DF_BASE__INST5_SEG1 = 0
DF_BASE__INST5_SEG2 = 0
DF_BASE__INST5_SEG3 = 0
DF_BASE__INST5_SEG4 = 0
DF_BASE__INST6_SEG0 = 0
DF_BASE__INST6_SEG1 = 0
DF_BASE__INST6_SEG2 = 0
DF_BASE__INST6_SEG3 = 0
DF_BASE__INST6_SEG4 = 0
DIO_BASE__INST0_SEG0 = 0x02404000
DIO_BASE__INST0_SEG1 = 0
DIO_BASE__INST0_SEG2 = 0
DIO_BASE__INST0_SEG3 = 0
DIO_BASE__INST0_SEG4 = 0
DIO_BASE__INST1_SEG0 = 0
DIO_BASE__INST1_SEG1 = 0
DIO_BASE__INST1_SEG2 = 0
DIO_BASE__INST1_SEG3 = 0
DIO_BASE__INST1_SEG4 = 0
DIO_BASE__INST2_SEG0 = 0
DIO_BASE__INST2_SEG1 = 0
DIO_BASE__INST2_SEG2 = 0
DIO_BASE__INST2_SEG3 = 0
DIO_BASE__INST2_SEG4 = 0
DIO_BASE__INST3_SEG0 = 0
DIO_BASE__INST3_SEG1 = 0
DIO_BASE__INST3_SEG2 = 0
DIO_BASE__INST3_SEG3 = 0
DIO_BASE__INST3_SEG4 = 0
DIO_BASE__INST4_SEG0 = 0
DIO_BASE__INST4_SEG1 = 0
DIO_BASE__INST4_SEG2 = 0
DIO_BASE__INST4_SEG3 = 0
DIO_BASE__INST4_SEG4 = 0
DIO_BASE__INST5_SEG0 = 0
DIO_BASE__INST5_SEG1 = 0
DIO_BASE__INST5_SEG2 = 0
DIO_BASE__INST5_SEG3 = 0
DIO_BASE__INST5_SEG4 = 0
DIO_BASE__INST6_SEG0 = 0
DIO_BASE__INST6_SEG1 = 0
DIO_BASE__INST6_SEG2 = 0
DIO_BASE__INST6_SEG3 = 0
DIO_BASE__INST6_SEG4 = 0
DCN_BASE__INST0_SEG0 = 0x00000012
DCN_BASE__INST0_SEG1 = 0x000000C0
DCN_BASE__INST0_SEG2 = 0x000034C0
DCN_BASE__INST0_SEG3 = 0x00009000
DCN_BASE__INST0_SEG4 = 0x02403C00
DCN_BASE__INST1_SEG0 = 0
DCN_BASE__INST1_SEG1 = 0
DCN_BASE__INST1_SEG2 = 0
DCN_BASE__INST1_SEG3 = 0
DCN_BASE__INST1_SEG4 = 0
DCN_BASE__INST2_SEG0 = 0
DCN_BASE__INST2_SEG1 = 0
DCN_BASE__INST2_SEG2 = 0
DCN_BASE__INST2_SEG3 = 0
DCN_BASE__INST2_SEG4 = 0
DCN_BASE__INST3_SEG0 = 0
DCN_BASE__INST3_SEG1 = 0
DCN_BASE__INST3_SEG2 = 0
DCN_BASE__INST3_SEG3 = 0
DCN_BASE__INST3_SEG4 = 0
DCN_BASE__INST4_SEG0 = 0
DCN_BASE__INST4_SEG1 = 0
DCN_BASE__INST4_SEG2 = 0
DCN_BASE__INST4_SEG3 = 0
DCN_BASE__INST4_SEG4 = 0
DCN_BASE__INST5_SEG0 = 0
DCN_BASE__INST5_SEG1 = 0
DCN_BASE__INST5_SEG2 = 0
DCN_BASE__INST5_SEG3 = 0
DCN_BASE__INST5_SEG4 = 0
DCN_BASE__INST6_SEG0 = 0
DCN_BASE__INST6_SEG1 = 0
DCN_BASE__INST6_SEG2 = 0
DCN_BASE__INST6_SEG3 = 0
DCN_BASE__INST6_SEG4 = 0
DPCS_BASE__INST0_SEG0 = 0x00000012
DPCS_BASE__INST0_SEG1 = 0x000000C0
DPCS_BASE__INST0_SEG2 = 0x000034C0
DPCS_BASE__INST0_SEG3 = 0x00009000
DPCS_BASE__INST0_SEG4 = 0x02403C00
DPCS_BASE__INST1_SEG0 = 0
DPCS_BASE__INST1_SEG1 = 0
DPCS_BASE__INST1_SEG2 = 0
DPCS_BASE__INST1_SEG3 = 0
DPCS_BASE__INST1_SEG4 = 0
DPCS_BASE__INST2_SEG0 = 0
DPCS_BASE__INST2_SEG1 = 0
DPCS_BASE__INST2_SEG2 = 0
DPCS_BASE__INST2_SEG3 = 0
DPCS_BASE__INST2_SEG4 = 0
DPCS_BASE__INST3_SEG0 = 0
DPCS_BASE__INST3_SEG1 = 0
DPCS_BASE__INST3_SEG2 = 0
DPCS_BASE__INST3_SEG3 = 0
DPCS_BASE__INST3_SEG4 = 0
DPCS_BASE__INST4_SEG0 = 0
DPCS_BASE__INST4_SEG1 = 0
DPCS_BASE__INST4_SEG2 = 0
DPCS_BASE__INST4_SEG3 = 0
DPCS_BASE__INST4_SEG4 = 0
DPCS_BASE__INST5_SEG0 = 0
DPCS_BASE__INST5_SEG1 = 0
DPCS_BASE__INST5_SEG2 = 0
DPCS_BASE__INST5_SEG3 = 0
DPCS_BASE__INST5_SEG4 = 0
DPCS_BASE__INST6_SEG0 = 0
DPCS_BASE__INST6_SEG1 = 0
DPCS_BASE__INST6_SEG2 = 0
DPCS_BASE__INST6_SEG3 = 0
DPCS_BASE__INST6_SEG4 = 0
FUSE_BASE__INST0_SEG0 = 0x00017400
FUSE_BASE__INST0_SEG1 = 0x02401400
FUSE_BASE__INST0_SEG2 = 0
FUSE_BASE__INST0_SEG3 = 0
FUSE_BASE__INST0_SEG4 = 0
FUSE_BASE__INST1_SEG0 = 0
FUSE_BASE__INST1_SEG1 = 0
FUSE_BASE__INST1_SEG2 = 0
FUSE_BASE__INST1_SEG3 = 0
FUSE_BASE__INST1_SEG4 = 0
FUSE_BASE__INST2_SEG0 = 0
FUSE_BASE__INST2_SEG1 = 0
FUSE_BASE__INST2_SEG2 = 0
FUSE_BASE__INST2_SEG3 = 0
FUSE_BASE__INST2_SEG4 = 0
FUSE_BASE__INST3_SEG0 = 0
FUSE_BASE__INST3_SEG1 = 0
FUSE_BASE__INST3_SEG2 = 0
FUSE_BASE__INST3_SEG3 = 0
FUSE_BASE__INST3_SEG4 = 0
FUSE_BASE__INST4_SEG0 = 0
FUSE_BASE__INST4_SEG1 = 0
FUSE_BASE__INST4_SEG2 = 0
FUSE_BASE__INST4_SEG3 = 0
FUSE_BASE__INST4_SEG4 = 0
FUSE_BASE__INST5_SEG0 = 0
FUSE_BASE__INST5_SEG1 = 0
FUSE_BASE__INST5_SEG2 = 0
FUSE_BASE__INST5_SEG3 = 0
FUSE_BASE__INST5_SEG4 = 0
FUSE_BASE__INST6_SEG0 = 0
FUSE_BASE__INST6_SEG1 = 0
FUSE_BASE__INST6_SEG2 = 0
FUSE_BASE__INST6_SEG3 = 0
FUSE_BASE__INST6_SEG4 = 0
GC_BASE__INST0_SEG0 = 0x00001260
GC_BASE__INST0_SEG1 = 0x0000A000
GC_BASE__INST0_SEG2 = 0x0001C000
GC_BASE__INST0_SEG3 = 0x02402C00
GC_BASE__INST0_SEG4 = 0
GC_BASE__INST1_SEG0 = 0
GC_BASE__INST1_SEG1 = 0
GC_BASE__INST1_SEG2 = 0
GC_BASE__INST1_SEG3 = 0
GC_BASE__INST1_SEG4 = 0
GC_BASE__INST2_SEG0 = 0
GC_BASE__INST2_SEG1 = 0
GC_BASE__INST2_SEG2 = 0
GC_BASE__INST2_SEG3 = 0
GC_BASE__INST2_SEG4 = 0
GC_BASE__INST3_SEG0 = 0
GC_BASE__INST3_SEG1 = 0
GC_BASE__INST3_SEG2 = 0
GC_BASE__INST3_SEG3 = 0
GC_BASE__INST3_SEG4 = 0
GC_BASE__INST4_SEG0 = 0
GC_BASE__INST4_SEG1 = 0
GC_BASE__INST4_SEG2 = 0
GC_BASE__INST4_SEG3 = 0
GC_BASE__INST4_SEG4 = 0
GC_BASE__INST5_SEG0 = 0
GC_BASE__INST5_SEG1 = 0
GC_BASE__INST5_SEG2 = 0
GC_BASE__INST5_SEG3 = 0
GC_BASE__INST5_SEG4 = 0
GC_BASE__INST6_SEG0 = 0
GC_BASE__INST6_SEG1 = 0
GC_BASE__INST6_SEG2 = 0
GC_BASE__INST6_SEG3 = 0
GC_BASE__INST6_SEG4 = 0
HDA_BASE__INST0_SEG0 = 0x004C0000
HDA_BASE__INST0_SEG1 = 0x02404800
HDA_BASE__INST0_SEG2 = 0
HDA_BASE__INST0_SEG3 = 0
HDA_BASE__INST0_SEG4 = 0
HDA_BASE__INST1_SEG0 = 0
HDA_BASE__INST1_SEG1 = 0
HDA_BASE__INST1_SEG2 = 0
HDA_BASE__INST1_SEG3 = 0
HDA_BASE__INST1_SEG4 = 0
HDA_BASE__INST2_SEG0 = 0
HDA_BASE__INST2_SEG1 = 0
HDA_BASE__INST2_SEG2 = 0
HDA_BASE__INST2_SEG3 = 0
HDA_BASE__INST2_SEG4 = 0
HDA_BASE__INST3_SEG0 = 0
HDA_BASE__INST3_SEG1 = 0
HDA_BASE__INST3_SEG2 = 0
HDA_BASE__INST3_SEG3 = 0
HDA_BASE__INST3_SEG4 = 0
HDA_BASE__INST4_SEG0 = 0
HDA_BASE__INST4_SEG1 = 0
HDA_BASE__INST4_SEG2 = 0
HDA_BASE__INST4_SEG3 = 0
HDA_BASE__INST4_SEG4 = 0
HDA_BASE__INST5_SEG0 = 0
HDA_BASE__INST5_SEG1 = 0
HDA_BASE__INST5_SEG2 = 0
HDA_BASE__INST5_SEG3 = 0
HDA_BASE__INST5_SEG4 = 0
HDA_BASE__INST6_SEG0 = 0
HDA_BASE__INST6_SEG1 = 0
HDA_BASE__INST6_SEG2 = 0
HDA_BASE__INST6_SEG3 = 0
HDA_BASE__INST6_SEG4 = 0
HDP_BASE__INST0_SEG0 = 0x00000F20
HDP_BASE__INST0_SEG1 = 0x0240A400
HDP_BASE__INST0_SEG2 = 0
HDP_BASE__INST0_SEG3 = 0
HDP_BASE__INST0_SEG4 = 0
HDP_BASE__INST1_SEG0 = 0
HDP_BASE__INST1_SEG1 = 0
HDP_BASE__INST1_SEG2 = 0
HDP_BASE__INST1_SEG3 = 0
HDP_BASE__INST1_SEG4 = 0
HDP_BASE__INST2_SEG0 = 0
HDP_BASE__INST2_SEG1 = 0
HDP_BASE__INST2_SEG2 = 0
HDP_BASE__INST2_SEG3 = 0
HDP_BASE__INST2_SEG4 = 0
HDP_BASE__INST3_SEG0 = 0
HDP_BASE__INST3_SEG1 = 0
HDP_BASE__INST3_SEG2 = 0
HDP_BASE__INST3_SEG3 = 0
HDP_BASE__INST3_SEG4 = 0
HDP_BASE__INST4_SEG0 = 0
HDP_BASE__INST4_SEG1 = 0
HDP_BASE__INST4_SEG2 = 0
HDP_BASE__INST4_SEG3 = 0
HDP_BASE__INST4_SEG4 = 0
HDP_BASE__INST5_SEG0 = 0
HDP_BASE__INST5_SEG1 = 0
HDP_BASE__INST5_SEG2 = 0
HDP_BASE__INST5_SEG3 = 0
HDP_BASE__INST5_SEG4 = 0
HDP_BASE__INST6_SEG0 = 0
HDP_BASE__INST6_SEG1 = 0
HDP_BASE__INST6_SEG2 = 0
HDP_BASE__INST6_SEG3 = 0
HDP_BASE__INST6_SEG4 = 0
MMHUB_BASE__INST0_SEG0 = 0x0001A000
MMHUB_BASE__INST0_SEG1 = 0x02408800
MMHUB_BASE__INST0_SEG2 = 0
MMHUB_BASE__INST0_SEG3 = 0
MMHUB_BASE__INST0_SEG4 = 0
MMHUB_BASE__INST1_SEG0 = 0
MMHUB_BASE__INST1_SEG1 = 0
MMHUB_BASE__INST1_SEG2 = 0
MMHUB_BASE__INST1_SEG3 = 0
MMHUB_BASE__INST1_SEG4 = 0
MMHUB_BASE__INST2_SEG0 = 0
MMHUB_BASE__INST2_SEG1 = 0
MMHUB_BASE__INST2_SEG2 = 0
MMHUB_BASE__INST2_SEG3 = 0
MMHUB_BASE__INST2_SEG4 = 0
MMHUB_BASE__INST3_SEG0 = 0
MMHUB_BASE__INST3_SEG1 = 0
MMHUB_BASE__INST3_SEG2 = 0
MMHUB_BASE__INST3_SEG3 = 0
MMHUB_BASE__INST3_SEG4 = 0
MMHUB_BASE__INST4_SEG0 = 0
MMHUB_BASE__INST4_SEG1 = 0
MMHUB_BASE__INST4_SEG2 = 0
MMHUB_BASE__INST4_SEG3 = 0
MMHUB_BASE__INST4_SEG4 = 0
MMHUB_BASE__INST5_SEG0 = 0
MMHUB_BASE__INST5_SEG1 = 0
MMHUB_BASE__INST5_SEG2 = 0
MMHUB_BASE__INST5_SEG3 = 0
MMHUB_BASE__INST5_SEG4 = 0
MMHUB_BASE__INST6_SEG0 = 0
MMHUB_BASE__INST6_SEG1 = 0
MMHUB_BASE__INST6_SEG2 = 0
MMHUB_BASE__INST6_SEG3 = 0
MMHUB_BASE__INST6_SEG4 = 0
MP0_BASE__INST0_SEG0 = 0x00016000
MP0_BASE__INST0_SEG1 = 0x00DC0000
MP0_BASE__INST0_SEG2 = 0x00E00000
MP0_BASE__INST0_SEG3 = 0x00E40000
MP0_BASE__INST0_SEG4 = 0x0243FC00
MP0_BASE__INST1_SEG0 = 0
MP0_BASE__INST1_SEG1 = 0
MP0_BASE__INST1_SEG2 = 0
MP0_BASE__INST1_SEG3 = 0
MP0_BASE__INST1_SEG4 = 0
MP0_BASE__INST2_SEG0 = 0
MP0_BASE__INST2_SEG1 = 0
MP0_BASE__INST2_SEG2 = 0
MP0_BASE__INST2_SEG3 = 0
MP0_BASE__INST2_SEG4 = 0
MP0_BASE__INST3_SEG0 = 0
MP0_BASE__INST3_SEG1 = 0
MP0_BASE__INST3_SEG2 = 0
MP0_BASE__INST3_SEG3 = 0
MP0_BASE__INST3_SEG4 = 0
MP0_BASE__INST4_SEG0 = 0
MP0_BASE__INST4_SEG1 = 0
MP0_BASE__INST4_SEG2 = 0
MP0_BASE__INST4_SEG3 = 0
MP0_BASE__INST4_SEG4 = 0
MP0_BASE__INST5_SEG0 = 0
MP0_BASE__INST5_SEG1 = 0
MP0_BASE__INST5_SEG2 = 0
MP0_BASE__INST5_SEG3 = 0
MP0_BASE__INST5_SEG4 = 0
MP0_BASE__INST6_SEG0 = 0
MP0_BASE__INST6_SEG1 = 0
MP0_BASE__INST6_SEG2 = 0
MP0_BASE__INST6_SEG3 = 0
MP0_BASE__INST6_SEG4 = 0
MP1_BASE__INST0_SEG0 = 0x00016000
MP1_BASE__INST0_SEG1 = 0x00DC0000
MP1_BASE__INST0_SEG2 = 0x00E00000
MP1_BASE__INST0_SEG3 = 0x00E40000
MP1_BASE__INST0_SEG4 = 0x0243FC00
MP1_BASE__INST1_SEG0 = 0
MP1_BASE__INST1_SEG1 = 0
MP1_BASE__INST1_SEG2 = 0
MP1_BASE__INST1_SEG3 = 0
MP1_BASE__INST1_SEG4 = 0
MP1_BASE__INST2_SEG0 = 0
MP1_BASE__INST2_SEG1 = 0
MP1_BASE__INST2_SEG2 = 0
MP1_BASE__INST2_SEG3 = 0
MP1_BASE__INST2_SEG4 = 0
MP1_BASE__INST3_SEG0 = 0
MP1_BASE__INST3_SEG1 = 0
MP1_BASE__INST3_SEG2 = 0
MP1_BASE__INST3_SEG3 = 0
MP1_BASE__INST3_SEG4 = 0
MP1_BASE__INST4_SEG0 = 0
MP1_BASE__INST4_SEG1 = 0
MP1_BASE__INST4_SEG2 = 0
MP1_BASE__INST4_SEG3 = 0
MP1_BASE__INST4_SEG4 = 0
MP1_BASE__INST5_SEG0 = 0
MP1_BASE__INST5_SEG1 = 0
MP1_BASE__INST5_SEG2 = 0
MP1_BASE__INST5_SEG3 = 0
MP1_BASE__INST5_SEG4 = 0
MP1_BASE__INST6_SEG0 = 0
MP1_BASE__INST6_SEG1 = 0
MP1_BASE__INST6_SEG2 = 0
MP1_BASE__INST6_SEG3 = 0
MP1_BASE__INST6_SEG4 = 0
NBIO_BASE__INST0_SEG0 = 0x00000000
NBIO_BASE__INST0_SEG1 = 0x00000014
NBIO_BASE__INST0_SEG2 = 0x00000D20
NBIO_BASE__INST0_SEG3 = 0x00010400
NBIO_BASE__INST0_SEG4 = 0x0241B000
NBIO_BASE__INST1_SEG0 = 0
NBIO_BASE__INST1_SEG1 = 0
NBIO_BASE__INST1_SEG2 = 0
NBIO_BASE__INST1_SEG3 = 0
NBIO_BASE__INST1_SEG4 = 0
NBIO_BASE__INST2_SEG0 = 0
NBIO_BASE__INST2_SEG1 = 0
NBIO_BASE__INST2_SEG2 = 0
NBIO_BASE__INST2_SEG3 = 0
NBIO_BASE__INST2_SEG4 = 0
NBIO_BASE__INST3_SEG0 = 0
NBIO_BASE__INST3_SEG1 = 0
NBIO_BASE__INST3_SEG2 = 0
NBIO_BASE__INST3_SEG3 = 0
NBIO_BASE__INST3_SEG4 = 0
NBIO_BASE__INST4_SEG0 = 0
NBIO_BASE__INST4_SEG1 = 0
NBIO_BASE__INST4_SEG2 = 0
NBIO_BASE__INST4_SEG3 = 0
NBIO_BASE__INST4_SEG4 = 0
NBIO_BASE__INST5_SEG0 = 0
NBIO_BASE__INST5_SEG1 = 0
NBIO_BASE__INST5_SEG2 = 0
NBIO_BASE__INST5_SEG3 = 0
NBIO_BASE__INST5_SEG4 = 0
NBIO_BASE__INST6_SEG0 = 0
NBIO_BASE__INST6_SEG1 = 0
NBIO_BASE__INST6_SEG2 = 0
NBIO_BASE__INST6_SEG3 = 0
NBIO_BASE__INST6_SEG4 = 0
OSSSYS_BASE__INST0_SEG0 = 0x000010A0
OSSSYS_BASE__INST0_SEG1 = 0x0240A000
OSSSYS_BASE__INST0_SEG2 = 0
OSSSYS_BASE__INST0_SEG3 = 0
OSSSYS_BASE__INST0_SEG4 = 0
OSSSYS_BASE__INST1_SEG0 = 0
OSSSYS_BASE__INST1_SEG1 = 0
OSSSYS_BASE__INST1_SEG2 = 0
OSSSYS_BASE__INST1_SEG3 = 0
OSSSYS_BASE__INST1_SEG4 = 0
OSSSYS_BASE__INST2_SEG0 = 0
OSSSYS_BASE__INST2_SEG1 = 0
OSSSYS_BASE__INST2_SEG2 = 0
OSSSYS_BASE__INST2_SEG3 = 0
OSSSYS_BASE__INST2_SEG4 = 0
OSSSYS_BASE__INST3_SEG0 = 0
OSSSYS_BASE__INST3_SEG1 = 0
OSSSYS_BASE__INST3_SEG2 = 0
OSSSYS_BASE__INST3_SEG3 = 0
OSSSYS_BASE__INST3_SEG4 = 0
OSSSYS_BASE__INST4_SEG0 = 0
OSSSYS_BASE__INST4_SEG1 = 0
OSSSYS_BASE__INST4_SEG2 = 0
OSSSYS_BASE__INST4_SEG3 = 0
OSSSYS_BASE__INST4_SEG4 = 0
OSSSYS_BASE__INST5_SEG0 = 0
OSSSYS_BASE__INST5_SEG1 = 0
OSSSYS_BASE__INST5_SEG2 = 0
OSSSYS_BASE__INST5_SEG3 = 0
OSSSYS_BASE__INST5_SEG4 = 0
OSSSYS_BASE__INST6_SEG0 = 0
OSSSYS_BASE__INST6_SEG1 = 0
OSSSYS_BASE__INST6_SEG2 = 0
OSSSYS_BASE__INST6_SEG3 = 0
OSSSYS_BASE__INST6_SEG4 = 0
PCIE0_BASE__INST0_SEG0 = 0x00000000
PCIE0_BASE__INST0_SEG1 = 0x00000014
PCIE0_BASE__INST0_SEG2 = 0x00000D20
PCIE0_BASE__INST0_SEG3 = 0x00010400
PCIE0_BASE__INST0_SEG4 = 0x0241B000
PCIE0_BASE__INST1_SEG0 = 0
PCIE0_BASE__INST1_SEG1 = 0
PCIE0_BASE__INST1_SEG2 = 0
PCIE0_BASE__INST1_SEG3 = 0
PCIE0_BASE__INST1_SEG4 = 0
PCIE0_BASE__INST2_SEG0 = 0
PCIE0_BASE__INST2_SEG1 = 0
PCIE0_BASE__INST2_SEG2 = 0
PCIE0_BASE__INST2_SEG3 = 0
PCIE0_BASE__INST2_SEG4 = 0
PCIE0_BASE__INST3_SEG0 = 0
PCIE0_BASE__INST3_SEG1 = 0
PCIE0_BASE__INST3_SEG2 = 0
PCIE0_BASE__INST3_SEG3 = 0
PCIE0_BASE__INST3_SEG4 = 0
PCIE0_BASE__INST4_SEG0 = 0
PCIE0_BASE__INST4_SEG1 = 0
PCIE0_BASE__INST4_SEG2 = 0
PCIE0_BASE__INST4_SEG3 = 0
PCIE0_BASE__INST4_SEG4 = 0
PCIE0_BASE__INST5_SEG0 = 0
PCIE0_BASE__INST5_SEG1 = 0
PCIE0_BASE__INST5_SEG2 = 0
PCIE0_BASE__INST5_SEG3 = 0
PCIE0_BASE__INST5_SEG4 = 0
PCIE0_BASE__INST6_SEG0 = 0
PCIE0_BASE__INST6_SEG1 = 0
PCIE0_BASE__INST6_SEG2 = 0
PCIE0_BASE__INST6_SEG3 = 0
PCIE0_BASE__INST6_SEG4 = 0
SDMA0_BASE__INST0_SEG0 = 0x00001260
SDMA0_BASE__INST0_SEG1 = 0x0000A000
SDMA0_BASE__INST0_SEG2 = 0x0001C000
SDMA0_BASE__INST0_SEG3 = 0x02402C00
SDMA0_BASE__INST0_SEG4 = 0
SDMA0_BASE__INST1_SEG0 = 0
SDMA0_BASE__INST1_SEG1 = 0
SDMA0_BASE__INST1_SEG2 = 0
SDMA0_BASE__INST1_SEG3 = 0
SDMA0_BASE__INST1_SEG4 = 0
SDMA0_BASE__INST2_SEG0 = 0
SDMA0_BASE__INST2_SEG1 = 0
SDMA0_BASE__INST2_SEG2 = 0
SDMA0_BASE__INST2_SEG3 = 0
SDMA0_BASE__INST2_SEG4 = 0
SDMA0_BASE__INST3_SEG0 = 0
SDMA0_BASE__INST3_SEG1 = 0
SDMA0_BASE__INST3_SEG2 = 0
SDMA0_BASE__INST3_SEG3 = 0
SDMA0_BASE__INST3_SEG4 = 0
SDMA0_BASE__INST4_SEG0 = 0
SDMA0_BASE__INST4_SEG1 = 0
SDMA0_BASE__INST4_SEG2 = 0
SDMA0_BASE__INST4_SEG3 = 0
SDMA0_BASE__INST4_SEG4 = 0
SDMA0_BASE__INST5_SEG0 = 0
SDMA0_BASE__INST5_SEG1 = 0
SDMA0_BASE__INST5_SEG2 = 0
SDMA0_BASE__INST5_SEG3 = 0
SDMA0_BASE__INST5_SEG4 = 0
SDMA0_BASE__INST6_SEG0 = 0
SDMA0_BASE__INST6_SEG1 = 0
SDMA0_BASE__INST6_SEG2 = 0
SDMA0_BASE__INST6_SEG3 = 0
SDMA0_BASE__INST6_SEG4 = 0
SDMA1_BASE__INST0_SEG0 = 0x00001260
SDMA1_BASE__INST0_SEG1 = 0x0000A000
SDMA1_BASE__INST0_SEG2 = 0x0001C000
SDMA1_BASE__INST0_SEG3 = 0x02402C00
SDMA1_BASE__INST0_SEG4 = 0
SDMA1_BASE__INST1_SEG0 = 0
SDMA1_BASE__INST1_SEG1 = 0
SDMA1_BASE__INST1_SEG2 = 0
SDMA1_BASE__INST1_SEG3 = 0
SDMA1_BASE__INST1_SEG4 = 0
SDMA1_BASE__INST2_SEG0 = 0
SDMA1_BASE__INST2_SEG1 = 0
SDMA1_BASE__INST2_SEG2 = 0
SDMA1_BASE__INST2_SEG3 = 0
SDMA1_BASE__INST2_SEG4 = 0
SDMA1_BASE__INST3_SEG0 = 0
SDMA1_BASE__INST3_SEG1 = 0
SDMA1_BASE__INST3_SEG2 = 0
SDMA1_BASE__INST3_SEG3 = 0
SDMA1_BASE__INST3_SEG4 = 0
SDMA1_BASE__INST4_SEG0 = 0
SDMA1_BASE__INST4_SEG1 = 0
SDMA1_BASE__INST4_SEG2 = 0
SDMA1_BASE__INST4_SEG3 = 0
SDMA1_BASE__INST4_SEG4 = 0
SDMA1_BASE__INST5_SEG0 = 0
SDMA1_BASE__INST5_SEG1 = 0
SDMA1_BASE__INST5_SEG2 = 0
SDMA1_BASE__INST5_SEG3 = 0
SDMA1_BASE__INST5_SEG4 = 0
SDMA1_BASE__INST6_SEG0 = 0
SDMA1_BASE__INST6_SEG1 = 0
SDMA1_BASE__INST6_SEG2 = 0
SDMA1_BASE__INST6_SEG3 = 0
SDMA1_BASE__INST6_SEG4 = 0
SMUIO_BASE__INST0_SEG0 = 0x00016800
SMUIO_BASE__INST0_SEG1 = 0x00016A00
SMUIO_BASE__INST0_SEG2 = 0x00440000
SMUIO_BASE__INST0_SEG3 = 0x02401000
SMUIO_BASE__INST0_SEG4 = 0
SMUIO_BASE__INST1_SEG0 = 0
SMUIO_BASE__INST1_SEG1 = 0
SMUIO_BASE__INST1_SEG2 = 0
SMUIO_BASE__INST1_SEG3 = 0
SMUIO_BASE__INST1_SEG4 = 0
SMUIO_BASE__INST2_SEG0 = 0
SMUIO_BASE__INST2_SEG1 = 0
SMUIO_BASE__INST2_SEG2 = 0
SMUIO_BASE__INST2_SEG3 = 0
SMUIO_BASE__INST2_SEG4 = 0
SMUIO_BASE__INST3_SEG0 = 0
SMUIO_BASE__INST3_SEG1 = 0
SMUIO_BASE__INST3_SEG2 = 0
SMUIO_BASE__INST3_SEG3 = 0
SMUIO_BASE__INST3_SEG4 = 0
SMUIO_BASE__INST4_SEG0 = 0
SMUIO_BASE__INST4_SEG1 = 0
SMUIO_BASE__INST4_SEG2 = 0
SMUIO_BASE__INST4_SEG3 = 0
SMUIO_BASE__INST4_SEG4 = 0
SMUIO_BASE__INST5_SEG0 = 0
SMUIO_BASE__INST5_SEG1 = 0
SMUIO_BASE__INST5_SEG2 = 0
SMUIO_BASE__INST5_SEG3 = 0
SMUIO_BASE__INST5_SEG4 = 0
SMUIO_BASE__INST6_SEG0 = 0
SMUIO_BASE__INST6_SEG1 = 0
SMUIO_BASE__INST6_SEG2 = 0
SMUIO_BASE__INST6_SEG3 = 0
SMUIO_BASE__INST6_SEG4 = 0
THM_BASE__INST0_SEG0 = 0x00016600
THM_BASE__INST0_SEG1 = 0x02400C00
THM_BASE__INST0_SEG2 = 0
THM_BASE__INST0_SEG3 = 0
THM_BASE__INST0_SEG4 = 0
THM_BASE__INST1_SEG0 = 0
THM_BASE__INST1_SEG1 = 0
THM_BASE__INST1_SEG2 = 0
THM_BASE__INST1_SEG3 = 0
THM_BASE__INST1_SEG4 = 0
THM_BASE__INST2_SEG0 = 0
THM_BASE__INST2_SEG1 = 0
THM_BASE__INST2_SEG2 = 0
THM_BASE__INST2_SEG3 = 0
THM_BASE__INST2_SEG4 = 0
THM_BASE__INST3_SEG0 = 0
THM_BASE__INST3_SEG1 = 0
THM_BASE__INST3_SEG2 = 0
THM_BASE__INST3_SEG3 = 0
THM_BASE__INST3_SEG4 = 0
THM_BASE__INST4_SEG0 = 0
THM_BASE__INST4_SEG1 = 0
THM_BASE__INST4_SEG2 = 0
THM_BASE__INST4_SEG3 = 0
THM_BASE__INST4_SEG4 = 0
THM_BASE__INST5_SEG0 = 0
THM_BASE__INST5_SEG1 = 0
THM_BASE__INST5_SEG2 = 0
THM_BASE__INST5_SEG3 = 0
THM_BASE__INST5_SEG4 = 0
THM_BASE__INST6_SEG0 = 0
THM_BASE__INST6_SEG1 = 0
THM_BASE__INST6_SEG2 = 0
THM_BASE__INST6_SEG3 = 0
THM_BASE__INST6_SEG4 = 0
UMC_BASE__INST0_SEG0 = 0x00014000
UMC_BASE__INST0_SEG1 = 0x02425800
UMC_BASE__INST0_SEG2 = 0
UMC_BASE__INST0_SEG3 = 0
UMC_BASE__INST0_SEG4 = 0
UMC_BASE__INST1_SEG0 = 0x00054000
UMC_BASE__INST1_SEG1 = 0x02425C00
UMC_BASE__INST1_SEG2 = 0
UMC_BASE__INST1_SEG3 = 0
UMC_BASE__INST1_SEG4 = 0
UMC_BASE__INST2_SEG0 = 0x00094000
UMC_BASE__INST2_SEG1 = 0x02426000
UMC_BASE__INST2_SEG2 = 0
UMC_BASE__INST2_SEG3 = 0
UMC_BASE__INST2_SEG4 = 0
UMC_BASE__INST3_SEG0 = 0x000D4000
UMC_BASE__INST3_SEG1 = 0x02426400
UMC_BASE__INST3_SEG2 = 0
UMC_BASE__INST3_SEG3 = 0
UMC_BASE__INST3_SEG4 = 0
UMC_BASE__INST4_SEG0 = 0x00114000
UMC_BASE__INST4_SEG1 = 0x02426800
UMC_BASE__INST4_SEG2 = 0
UMC_BASE__INST4_SEG3 = 0
UMC_BASE__INST4_SEG4 = 0
UMC_BASE__INST5_SEG0 = 0x00154000
UMC_BASE__INST5_SEG1 = 0x02426C00
UMC_BASE__INST5_SEG2 = 0
UMC_BASE__INST5_SEG3 = 0
UMC_BASE__INST5_SEG4 = 0
UMC_BASE__INST6_SEG0 = 0x00194000
UMC_BASE__INST6_SEG1 = 0x02427000
UMC_BASE__INST6_SEG2 = 0
UMC_BASE__INST6_SEG3 = 0
UMC_BASE__INST6_SEG4 = 0
USB0_BASE__INST0_SEG0 = 0x0242A800
USB0_BASE__INST0_SEG1 = 0x05B00000
USB0_BASE__INST0_SEG2 = 0
USB0_BASE__INST0_SEG3 = 0
USB0_BASE__INST0_SEG4 = 0
USB0_BASE__INST1_SEG0 = 0
USB0_BASE__INST1_SEG1 = 0
USB0_BASE__INST1_SEG2 = 0
USB0_BASE__INST1_SEG3 = 0
USB0_BASE__INST1_SEG4 = 0
USB0_BASE__INST2_SEG0 = 0
USB0_BASE__INST2_SEG1 = 0
USB0_BASE__INST2_SEG2 = 0
USB0_BASE__INST2_SEG3 = 0
USB0_BASE__INST2_SEG4 = 0
USB0_BASE__INST3_SEG0 = 0
USB0_BASE__INST3_SEG1 = 0
USB0_BASE__INST3_SEG2 = 0
USB0_BASE__INST3_SEG3 = 0
USB0_BASE__INST3_SEG4 = 0
USB0_BASE__INST4_SEG0 = 0
USB0_BASE__INST4_SEG1 = 0
USB0_BASE__INST4_SEG2 = 0
USB0_BASE__INST4_SEG3 = 0
USB0_BASE__INST4_SEG4 = 0
USB0_BASE__INST5_SEG0 = 0
USB0_BASE__INST5_SEG1 = 0
USB0_BASE__INST5_SEG2 = 0
USB0_BASE__INST5_SEG3 = 0
USB0_BASE__INST5_SEG4 = 0
USB0_BASE__INST6_SEG0 = 0
USB0_BASE__INST6_SEG1 = 0
USB0_BASE__INST6_SEG2 = 0
USB0_BASE__INST6_SEG3 = 0
USB0_BASE__INST6_SEG4 = 0
VCN_BASE__INST0_SEG0 = 0x00007800
VCN_BASE__INST0_SEG1 = 0x00007E00
VCN_BASE__INST0_SEG2 = 0x02403000
VCN_BASE__INST0_SEG3 = 0
VCN_BASE__INST0_SEG4 = 0
VCN_BASE__INST1_SEG0 = 0x00007B00
VCN_BASE__INST1_SEG1 = 0x00012000
VCN_BASE__INST1_SEG2 = 0x02445000
VCN_BASE__INST1_SEG3 = 0
VCN_BASE__INST1_SEG4 = 0
VCN_BASE__INST2_SEG0 = 0
VCN_BASE__INST2_SEG1 = 0
VCN_BASE__INST2_SEG2 = 0
VCN_BASE__INST2_SEG3 = 0
VCN_BASE__INST2_SEG4 = 0
VCN_BASE__INST3_SEG0 = 0
VCN_BASE__INST3_SEG1 = 0
VCN_BASE__INST3_SEG2 = 0
VCN_BASE__INST3_SEG3 = 0
VCN_BASE__INST3_SEG4 = 0
VCN_BASE__INST4_SEG0 = 0
VCN_BASE__INST4_SEG1 = 0
VCN_BASE__INST4_SEG2 = 0
VCN_BASE__INST4_SEG3 = 0
VCN_BASE__INST4_SEG4 = 0
VCN_BASE__INST5_SEG0 = 0
VCN_BASE__INST5_SEG1 = 0
VCN_BASE__INST5_SEG2 = 0
VCN_BASE__INST5_SEG3 = 0
VCN_BASE__INST5_SEG4 = 0
VCN_BASE__INST6_SEG0 = 0
VCN_BASE__INST6_SEG1 = 0
VCN_BASE__INST6_SEG2 = 0
VCN_BASE__INST6_SEG3 = 0
VCN_BASE__INST6_SEG4 = 0