forked from IQ.Lvbs/IQ.Pilot
39 lines
1.3 KiB
C
39 lines
1.3 KiB
C
#pragma once
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// The SPI slave must re-arm its RX DMA at every protocol turnaround before the
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// master clocks the next phase. Without preemption that re-arm waits behind any
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// in-flight handler (CAN RX under bus load), the master clocks into an unarmed
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// peripheral, and the transfer fails its checksum -> NACK retry storms.
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#define IRQ_PRIORITY_COMMS 0U
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#define IRQ_PRIORITY_DEFAULT 2U
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typedef struct interrupt {
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IRQn_Type irq_type;
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void (*handler)(void);
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uint32_t call_counter;
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uint32_t call_rate;
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uint32_t max_call_rate; // Call rate is defined as the amount of calls each second
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uint32_t call_rate_fault;
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} interrupt;
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void interrupt_timer_init(void);
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uint32_t microsecond_timer_get(void);
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void unused_interrupt_handler(void);
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extern interrupt interrupts[NUM_INTERRUPTS];
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#define REGISTER_INTERRUPT(irq_num, func_ptr, call_rate_max, rate_fault) \
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interrupts[irq_num].irq_type = (irq_num); \
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interrupts[irq_num].handler = (func_ptr); \
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interrupts[irq_num].call_counter = 0U; \
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interrupts[irq_num].call_rate = 0U; \
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interrupts[irq_num].max_call_rate = (call_rate_max); \
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interrupts[irq_num].call_rate_fault = (rate_fault);
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extern float interrupt_load;
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void handle_interrupt(IRQn_Type irq_type);
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// Every second
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void interrupt_timer_handler(void);
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void init_interrupts(bool check_rate_limit);
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